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REFERENCE CIRCUITS
A reference circuit is an independent voltage or
current source which has a high degree of
precision and stability.
• Output voltage/current should be
independent of power supply.
• Output voltage/current should be
independent of temperature.
• Output voltage/current should be
independent of processing variations.
I-V curves of ideal references
Concept of Sensitivity
Let
Then:
y  f ( x1 , x2 , x3 )
f
f
f
y 
x1 
x2 
x3  
x1
x1
x1
y f x1 x1 f x2 x2 f x3 x3




y x1 y x1 x1 y x2 x1 y x3
y
y x1
y x2
y x3
 S x1
 S x2
 S x3

y
x1
x2
x3
y
S xi is called the sensitivity of y with respect to xi
Total percentage change in y =
Sensitivity w.r.t. x1 * percentage
change in x1
+ Sensitivity w.r.t. x2 * percentage
change in x2
+ ……
Goal: Design reference circuits so that
the reference’s sensitivities w.r.t.
various variations are minimized.
Types of commonly used references
•
•
•
•
•
•
•
Voltage dividers - passive and active.
MOS diode reference.
PN junction diode reference.
Gate-source threshold reference circuit.
Base-emitter reference circuit.
Thermo voltage reference circuit
Bandgap reference circuit
Typical variations affecting the
references
• Power supply variation (main concern
here)
• Load variation (want ro=∞ for I-ref, ro=0 for
V-ref)
• Temperature variation (main concern also)
• Processes variation (use good process
and layout)
• Interferences and noise (not considered
here)
For temperature variation, typically use
fractional temperature coefficient:
1 y 1 y
TCF = ST =
y T
T
rather than sensitivity
Voltage references
Passive Divider
Limited accuracy,
~6-bit, or 2%
Large static power
for small ro
Large area
Power sensitivity =1
Temp coeff depends on
material
Active Dividers
These can be used as “start up” circuits.
PN Junction Voltage References
S
VREF
VCC
=
1
ln(VCC / RI s )
If VCC = 10V, R = 10 kW, and IS =
10-15A,
then
S
VREF
VCC
= 0.0362.
v
i  I s exp( ),
For a diode:
Vt
Vt  kT / q
 VGO
I s  KT exp(
)
Vt
VCC  VREF
VREF  VGO
3
 KT exp(
)
R
kT / q
Taking ∂/∂T and using: VCC − VREF + kT/q ≈ VCC − VREF:
3k
kT R
1 VREF VREF  VGO
TCF≈
=


VREF T
VREFT
VREF q VREF q RT
3
where VGO = 1.205 V is the bandgap voltage of
silicon.
If VREF = VBE = 0.6V, TCF of R = 1500 ppm,
then TCF of VREF = -3500 ppm/oC
VREF
HW: Calculate S V
Calculate TCF
CC
MOS equivalent of VBE reference:
VREF  VGS
2(VDD  VREF )
 VT 
R
VREF  VT 
1
2(VDD  VT )
1

 2 2
R
R
 R
VREF
R1  R2

VGS
R2
VREF
2(VDD  VT )
1
1
 VT 

 2 2
R
R
 R
2(VDD  VT )
1
1
 VREF  VT  
 2 2
R
R
 R
1   R VREF  VT   2(VDD  VT )  R  1
REF
SVVDD

VREF VDD

VDD VREF
1
VDD
R
2(VDD  VT )
1 VREF
 2 2
R
 R
VDD
1
2(VDD  VT )  R  1 VREF
VREF
VDD

VREF
VDD
VDD
1

1   R VREF  VT  VREF
S
S
The sensitivity w.r.t. VDD:
S
VREF
VDD

VDD
1
VREF 1  R(VREF  VT )
If VDD = 10V, W/L = 10, R = 100kW,and using
parameters from Table3.1-2,
then VREF = 1.97V and
S
VREF
VDD
= 0.29
This is not nearly as good as the VBE reference.
For temperature coefficient
mo = KT-1.5 ; VT = VT0 - aT or VT(T) = VT(To) - a(T-To)
mCoxW
VDD  VREF
VREF  VT  
2L
R
mCoxW
m mCoxW
VREF VT
2
VREF  VT   2
VREF  VT (

)
mT 2 L
2L
T
T
VDD  VREF R 1 VREF


R
RT R T
mCoxW VDD  VREF VREF
 1.5 VDD  VREF
2
(
a)
T
R
2L
R
T
VDD  VREF R 1 VREF


R
RT R T
2
Solving for ∂VREF/∂T and computer TC:
1 VREF
TC F 
VREF T
VDD  VREF  1.5 1 R 
a 



2 R  T R T 
1

1
VREF
1
2 R(VDD  VREF )
The book has one example of using this.
Widlar current source
Vgs1-Vgs2-IoutR2=0
IoR2 +rt(Io/2)-VEB1=0
Rt(Io)=(rt(1/2 +4R2VEB2)-rt(1/2))/2R2
Peaking current source:
Vgs1-IinR-Vgs2=0
VEB2=VEB1-IinR
Io=2*VEB2^2=2*(VEB1-IinR)^2
VEB1 = rt(Iin/2) is determined by Iin and (W/L)1
If VD1 is small, M2 is in weak inversion. If Iin is very small, M1 is in
weak or moderate inversion.
VGS based Current reference
MOS version: use VGS to generate a current and
then use negative feed back stabilize i in MOS
Start
up
Current mirror
VGS
Why the start up circuit?
There are two possible operating points:
The desired one and
The one that gives I1 = I2 = 0.
At power up, I1 = I2 = 0 without the start up.
RB bias M6 to be on, which turns M2 and M1 on.
Considering the l-effect, (1) is more like:
1  lPVGS 4
I 2 1  lPVDS 4


I1 1  lPVDS 3 1  lP (VDD  VDS1 )
Then:
I1 R(1  lPVGS 4 )  (1  lP (VDD  VDS1 )) I 2 R


2
I
1

 1  lP (VDD  VDS1 ) VT 1 


1 

Differentiating wrt VDD and assuming constant VDS1
and VGS4 gives the sensitivity of IOUT wrt VDD.
HW: Verify the following sensitivity expression:
VDD
I out


2
I
1

lP VT 1 


1 

R(1  lPVGS 4 )  1  lP (VDD  VDS1 )  / 2 I11
HW: Find approximately the temperature
coefficient of Iout
Start
up
Start
up
Current mirror
VGS
1. Need to add start-up circuit
VDD
2. Add MOSCAPs between
VBP and VDD, and
between VBN and VSS
VBP
3. NMOS W ratio and R
determines current value
IREF
IREF
VBN
4. Cascode to improve supply
sensitivity
5. Or use a regulated amp
VSS
6. VBN and VBP may be
directly used as biasing
voltage for non-critical use
VDD
Cascode version
VDD-Vss must be
large enough
VBP
IREF
VBP
IREF
VBN
VSS
Cascode version for low voltage
VDD
1/5(W/L)p
VBNC
IREF
VBP
IREF
VBPC
1/5(W/L)N
VBN
K(W/L)N
VSS
Sample design steps:
1. Select Iref (may be given)
2. Assume all transistors except those arrowed have the same VEB.
–
–
–
–
3.
At VDDmin, Needs all transistors in saturation.
–
–
–
4.
5.
VBN = VSS+VTN+VEB;
VBNC = VSS+VTN+VEB*rt(5);
VBP = VDD-|VTP|-VEB;
VBPC = VDD-|VTP|-VEB*rt(5).
For PMOS, need VBN < VBPC+|VTP| = VDDmin-VEB*rt(5). VEB <
(VDDmin-VSS-VTN)/(1+rt(5)).
For NMOS, need VBP>VBNC-VTN, VDDmin-|VTP|-VEB > VSS+VEB*rt(5). 
VEB < (VDDmin-VSS-|VTP|)/(1+rt(5)).
Since |VTP| is typically larger, so choose the second one. VEB ≈< (VDDminVSS-|VTP|)/(1+rt(5)).
With given VEB and Iref, all (W/L)’s can be determined.
Choose K and R: Iref*R=VEB – VEB/rt(K), so R = (11/rt(K))*VEB/Iref. Choose K so that a) R size is not too large and b)
R+1/gmn/rt(K) is quite bit larger than 1/gmn.
VEB based current reference
Start
up
VEB=VR
A cascoded version to increase ro and
reduce sensitivity:
V
DD
M7
M8
M5
VBP
M6
VBP
M3
M4
M1
M2
D
VSS
R
M9
Requires start up
M10
Not shown here
IREF
VEB reference
HW:
Analyze the sensitivity of the output I with
respect to VDD and temperature.
Come up with a start up circuit for the circuit on
the previous slide, using only active resisters
without RB. Note that you need to make sure
that at the desired operating point, the
connection from the start up circuit should be
turned off.
A thermal voltage based current reference
I1 = I2,  J1 = KJ2,
but J = Jsexp(VEB/Vt)
 J1/J2 = n =
exp((VEB1─ VEB2)/Vt)
 VEB1─ VEB2 = Vt ln(n)
I = (VEB1─ VEB2)/R
= Vt ln(n)/R  Vt = kT/q
A band gap voltage reference
Vout = VEB3 + I*x*R =
VEB3 + (kT/q)*xln(n)
Vout/T = VEB3/T +
(k/q)*xln(n)
At room temperature,
VEB3/T = ─2.2 mV/oC,
k/q = +0.085 mV/oC.
Hence, choosing
appropriate x and n can
make
Vout/T=0
When this happens, Vout
= 1.26 V
Converting to current