Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Pulse-width modulation wikipedia , lookup
Transmission line loudspeaker wikipedia , lookup
Buck converter wikipedia , lookup
Power engineering wikipedia , lookup
Mains electricity wikipedia , lookup
Distribution management system wikipedia , lookup
Opto-isolator wikipedia , lookup
Rectiverter wikipedia , lookup
Electronic engineering wikipedia , lookup
Power MOSFET wikipedia , lookup
Alternating current wikipedia , lookup
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Outline ■ Power and Energy ■ Dynamic Power ■ Static Power 6.2 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Power and Energy ■ Power is drawn from a voltage source attached to the VDD pin(s) of a chip. ■ Instantaneous Power: P(t ) I (t )V (t ) T ■ Energy: E P (t )dt 0 T ■ Average Power: 6.3 Pavg E 1 P(t )dt T T 0 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Power in Circuit Elements PVDD t I DD t VDD VR2 t PR t I R2 t R R 0 0 EC I t V t dt C dV V t dt dt VC C V t dV 12 CVC2 0 6.4 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Charging a Capacitor ■ When the gate output rises ► Energy stored in capacitor is 2 EC 12 CLVDD ► But energy drawn from the supply is 0 0 EVDD I t VDD dt CL CLVDD dV VDD dt dt VDD dV C V 2 L DD 0 ► Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor ■ When the gate output falls ► Energy in capacitor is dumped to GND ► Dissipated as heat in the nMOS transistor 6.5 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Switching Waveforms ■ Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz 6.6 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Switching Power T Pswitching 1 iDD (t )VDD dt T 0 T VDD iDD (t )dt T 0 VDD Tfsw CVDD T CVDD 2 fsw VDD iDD(t) fsw C 6.7 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Activity Factor ■ Suppose the system clock frequency = f ■ Let fsw = af, where a = activity factor ► If the signal is a clock, a = 1 ► If the signal switches once per cycle, a = ½ ■ Dynamic power: Pswitching a CVDD 2 f 6.8 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Short Circuit Current ■ When transistors switch, both nMOS and pMOS networks may be momentarily ON at once ■ Leads to a “short circuit” current. ■ < 10% of dynamic power if rise/fall times are comparable for input and output ■ We will generally ignore this component 6.9 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Power Dissipation Sources ■ Ptotal = Pdynamic + Pstatic ■ Dynamic power: Pdynamic = Pswitching + Pshortcircuit ► Switching load capacitances ► Short-circuit current ■ Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD ► Subthreshold leakage ► Gate leakage ► Junction leakage ► Contention current 6.10 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Dynamic Power Example ■ 1 billion transistor chip ► 50M logic transistors ▼ Average width: 12 l ▼ Activity factor = 0.1 ► 950M memory transistors ▼ Average width: 4 l ▼ Activity factor = 0.02 ► 1.0 V 65 nm process ► C = 1 fF/mm (gate) + 0.8 fF/mm (diffusion) ■ Estimate dynamic power consumption @ 1 GHz. Neglect wire capacitance and short-circuit current. 6.11 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Solution Clogic 50 106 12l 0.025m m / l 1.8 fF / m m 27 nF Cmem 950 106 4l 0.025m m / l 1.8 fF / m m 171 nF Pdynamic 0.1Clogic 0.02Cmem 1.0 1.0 GHz 6.1 W 2 6.12 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Dynamic Power Reduction ■ Pswitching a CVDD 2 f ■ Try to minimize: ► Activity factor ► Capacitance ► Supply voltage ► Frequency 6.13 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Activity Factor Estimation ■ Let Pi = Prob(node i = 1) ► Pi = 1-Pi ■ ai = Pi * Pi ■ Completely random data has P = 0.5 and a = 0.25 ■ Data is often not completely random ► e.g. upper bits of 64-bit words representing bank account balances are usually 0 ■ Data propagating through ANDs and ORs has lower activity factor ► Depends on design, but typically a ≈ 0.1 6.14 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Switching Probability 6.15 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Example ■ A 4-input AND is built out of two levels of gates ■ Estimate the activity factor at each node if the inputs have P = 0.5 6.16 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Clock Gating ■ The best way to reduce the activity is to turn off the clock to registers in unused blocks ► Saves clock activity (a = 1) ► Eliminates all switching activity in the block ► Requires determining if block will be used 6.17 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Capacitance ■ Gate capacitance ► Fewer stages of logic ► Small gate sizes ■ Wire capacitance ► Good floorplanning to keep communicating blocks close to each other ► Drive long wires with inverters or buffers rather than complex gates 6.18 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Voltage / Frequency ■ Run each block at the lowest possible voltage and frequency that meets performance requirements ■ Voltage Domains ► Provide separate supplies to different blocks ► Level converters required when crossing from low to high VDD domains ■ Dynamic Voltage Scaling ► Adjust VDD and f according to workload 6.19 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Static Power ■ Static power is consumed even when chip is quiescent. ► Leakage draws power from nominally OFF devices ► Ratioed circuits burn power in fight between ON transistors 6.20 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Static Power Example ■ Revisit power estimation for 1 billion transistor chip ■ Estimate static power consumption ► Subthreshold leakage ▼ Normal Vt: 100 nA/mm ▼ High Vt: 10 nA/mm ▼ High Vt used in all memories and in 95% of logic gates ► Gate leakage ► Junction leakage 6.21 5 nA/mm negligible Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Solution Wnormal-Vt 50 106 12l 0.025m m / l 0.05 0.75 106 m m Whigh-Vt 50 106 12l 0.95 950 106 4l 0.025m m / l 109.25 106 m m I sub Wnormal-Vt 100 nA/m m+Whigh-Vt 10 nA/m m / 2 584 mA I gate Wnormal-Vt Whigh-Vt 5 nA/m m / 2 275 mA Pstatic 584 mA 275 mA 1.0 V 859 mW 6.22 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Subthreshold Leakage ■ For Vds > 50 mV Vgs Vds VDD k Vsb I sub I off 10 S ■ Ioff = leakage at Vgs = 0, Vds = VDD 6.23 Typical values in 65 nm Ioff = 100 nA/mm @ Vt = 0.3 V Ioff = 10 nA/mm @ Vt = 0.4 V Ioff = 1 nA/mm @ Vt = 0.5 V = 0.1 k = 0.1 S = 100 mV/decade Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Stack Effect ■ Series OFF transistors have less leakage ► Vx > 0, so N2 has negative Vgs Vx VDD I sub I off 10 S I off 10 Vx VDD Vx VDD k Vx N2 Vx S N1 VDD 1 2 k I sub I off 10 1 k VDD 1 2 k S I off 10 VDD S ► Leakage through 2-stack reduces ~10x ► Leakage through 3-stack reduces further 6.24 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Leakage Control ■ Leakage and delay trade off ► Aim for low leakage in sleep and low delay in active mode ■ To reduce leakage: ► Increase Vt: multiple Vt ▼ Use low Vt only in critical circuits ► Increase Vs: stack effect ▼ Input vector control in sleep ► Decrease Vb ▼ Reverse body bias in sleep ▼ Or forward body bias in active mode 6.25 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Gate Leakage ■ Extremely strong function of tox and Vgs ► Negligible for older processes ► Approaches subthreshold leakage at 65 nm and below in some processes ■ An order of magnitude less for pMOS than nMOS ■ Control leakage in the process using tox > 10.5 Å ► High-k gate dielectrics help ► Some processes provide multiple tox ▼ e.g. thicker oxide for 3.3 V I/O transistors ■ Control leakage in circuits by limiting VDD 6.26 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis NAND3 Leakage Example ■ 100 nm process Ign = 6.3 nA Igp = 0 Ioffn = 5.63 nA Ioffp = 9.3 nA Data from [Lee03] 6.27 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Junction Leakage ■ From reverse-biased p-n junctions ► Between diffusion and substrate or well ■ Ordinary diode leakage is negligible ■ Band-to-band tunneling (BTBT) can be significant ► Especially in high-Vt transistors where other leakage is small ► Worst at Vdb = VDD ■ Gate-induced drain leakage (GIDL) exacerbates ► Worst for Vgd = -VDD (or more negative) 6.28 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis Power Gating ■ Turn OFF power to blocks when they are idle to save leakage ► Use virtual VDD (VDDV) ► Gate outputs to prevent invalid logic levels to next block ■ Voltage drop across sleep transistor degrades performance during normal operation ► Size the transistor wide enough to minimize impact ■ Switching wide sleep transistor costs dynamic power ► Only justified when circuit sleeps long enough 6.29 Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis