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ECNG 1014: Digital Electronics
Lecture 3: Technology
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© Lucien Ngalamou – All rights reserved
Topics
 Introduction
 Basic Operational Characteristics and Parameters of
Integrated Circuits
 CMOS Technology
 Overview of TTL Technology
 Some Practical Considerations
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1. Introduction
 Technology = Mean and physical implementation of real digital
circuits whose behaviors are dictated by digital laws (combinational
or sequential)
 To understand some of the issues related to the technology, a
number of questions must be answered such as:




What type of electronic basic element (passive or active) can be used to
implement a simple gate as an “inverter”?
How efficient is an implementation in terms of power and speed?
What is the level of integration?
How to characterize a digital electronic device?
 We are fortunate that these questions were answered properly in the
past by many physicists. We will present their outcomes in term of
technology.
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2. Basic Operational Characteristics and Parameters
 Digital components are called “Integrated circuits”. They
are implemented using transistors.
 In Digital electronics, transistors are always configured to
work in switching modes.
 The type of transistor being used defines the technology:

TTL (transistor-transistor-logic) for bipolar transistors

CMOS (complementary MOS) for MOSFET transistors

MOSFET = metal-oxide semiconductor field-effect transistor
 The following figure show an IC packages that contains
“nand” gates.
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(from Floyd’s Text)
Figure 1: IC Package containing Nand Gates.
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2.1. Logic Levels
 The concept of logic levels is used to represent logic
variables in digital electronic circuits.
 There are four different logic-level specifications:

VIL (Voltage input Low)

VIH (Voltage input high)

VOL (Voltage output low)

VOH (Voltage output high)
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 Figures 2 and 3 show clearly that these two technology
don’t support all the ranges of voltages.
 If and input falls into the restricted region the behavior of
the circuit is unpredictable, therefore its output doesn’t
represent a valuable information.
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Figure 2: Inputs and output logic levels for CMOS
(from Floyd’s Text)
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
(from Floyd’s Text)
Figure 3: Input and output Logic levels for TTL
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2.2 Noise
 Noise is unwanted voltage that is included in electrical circuits and
can present a threat to a proper operation of the circuit.
 Sources of noise are: power supply, cross talk (coupling), interference, offset,
etc.
 Examples of noise:

Thermal noise

Electromagnetic noise

Power-line voltage fluctuation noise
 In order not to be adversely affected by noise, a logic circuit must
have a certain amount of noise immunity.
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 Examples of electromagnetic noise due to coupling:

capacitive coupling



voltage change on one wire can
influence signal on the neighboring wire
cross talk
inductive coupling

v(t)
i(t)
current change on one wire can
influence signal on the neighboring wire
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 For robust circuits, we want the “0” and “1” intervals to be a s
large as possible
VDD
VDD
VOHmin
"1"
NMH = VOHmin - VIHmin
Noise Margin High
VIHmin
Noise Margin Low
VILmax
Undefined
Region
NML = VILmax - VOLmax
VOLmax
"0"
Gnd
Gate Output
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Gnd
Gate Input
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2.3 Noise Immunity
 Noise immunity expresses the ability of the system to
process and transmit information correctly in the presence
of noise
 For good noise immunity, the signal swing (i.e., the
difference between VOH and VOL) and the noise margin have
to be large enough to overpower the impact of fixed
sources of noise
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2.4 Static Gate Behavior
 Steady-state parameters of a gate – static behavior – tell how
robust a circuit is with respect to both variations in the
manufacturing process and to noise disturbances.
 Digital circuits perform operations on Boolean variables
x {0,1}
 A logical variable is associated with a nominal voltage level for
each logic state
1  VOH and 0  VOL
!
V(x)
V(y)
= complement
VOH = ! (VOL)
VOL = ! (VOH)
Difference between VOH and VOL is the logic or signal
swing Vsw
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2.5 DC Operation
Voltage Transfer Characteristics (VTC)

Plot of output voltage as a function of the input voltage
V(x)
V(y)
V(y)
f
VOH = f (VIL)
V(y)=V(x)
VM
Switching Threshold
VOL = f (VIH)
VIL
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VIH
V(x)
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2.6. Mapping Logic Levels to the Voltage Domain

The regions of acceptable high and low voltages are
delimited by VIH and VIL that represent the points on the
VTC curve where the gain = -1
V(y)
"1"
VOH
VIH
VOH
Slope = -1
Undefined
Region
VIL
"0"
VOL
Slope = -1
VOL
VIL VIH
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V(x)
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2.7. Logic Levels: Practical Scenario
 The two sets of levels are motivated by these scenarios
Valid
input
VOHMIN
Valid
output
VIHMIN
RTH
Rline
Vcc
RIN
Vdrop
Scenario 1:
Source outputs logic
high at lowest threshold,
VOHMIN
I
SINK
SOURCE
Valid
input
Vcc
VOLMAX
Valid
output
VILMAX
RTHL
Rline
RIN
Scenario 2:
Source outputs logic low
at highest threshold,
VOLMAX
I
SINK
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SOURCE
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DC Loading
 The output high and low limits are exceeded only if a device output is heavily
loaded. Logic device loading is specified by

maximum current

Fanout := max. number of similar devices that can be connected to a load without
exceeding high and low state current limits
Current Specs
IOHMAX
Max source current for which VOH  VOHMIN (valid output high)
IOLMAX
Max sink current for which VOL  VOLMAX (valid output low)
IIHMAX
Max input current for VIH  VIHMIN (valid input high)
IILMAX
Max input current for which VIL  VILMAX (valid input low)
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DC Loading: Current specs
Valid
input
 Scenario 1: Output high
IIHMAX1
1
Vo > VOHMIN
Io < IOHMAX
n
IIHMAXn
Valid
input
IILMAX1
Vo < VOLMAX
1
Io < IOLMAX
IILMAXn
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connected to more than one sink.
The current outputted by the
source increases with the
number of sinks.
Io = Iinj = nIin (for n similar sinks)
 Scenario 2: Output low
connected to more than one sink.
Note that the current now flows
into the output terminal (logic
source becomes a current sink).
Again current increases with the
number of logic sinks.
Io = Iinj = nIin (for n similar sinks)
n
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DC Loading: Fanout
 Each gate input requires a certain
amount of current to maintain it in
the LOW state or in the HIGH state.


IIL and IIH
These are specified by the
manufacturer.
 I OL max driver 
nFlow  

  I ILdriven 
Fanout calculation
–Low state fanout, nFlow:= maximum
number of similar gates that can be driven
low so that Vo < VOLMAX
–High state fanout, nFhigh:= maximum
number of similar gates that can be driven
high so that Vo > VOHMIN
–Need to do current loading calculation for
non-gate loads (LEDs, termination
resistors, etc.)
Fanout, nF  min nFlow, nFhigh
 I OH max driver 
nFhigh  

I
  IH driven 
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2.9 AC Loading
 All gate outputs have associated parasitic capacitances due to
external wiring (including their gate pins) as well as internal
semiconductor storage effects (junction capacitances).
 In addition there are parasitic capacitances associated with each
gate input. Typically the capacitance component due to IC pins is
of the order of 10-15pF.
 The final transistor which drives the gate output acts as an
electronically controlled switch with a pull-up to Vcc.
Vcc
R
Vo
Parasitic
capacitance,
Cp
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Switch closed:
Vo = 0
Switch opens: Cp charges to Vcc
with LH=RCp.
Switch closes: Cp discharges
through contact resistance, r,
with HL=rCp.
Contact
resistance, r
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2.10 The Ideal Inverter
 The ideal gate should have




infinite gain in the transition region
a gate threshold located in the middle of the logic swing
high and low noise margins equal to half the swing
input and output impedances of infinity and zero, resp.
Vout
Ri = 
Ro = 0
g=-
Fanout = 
NMH = NML = VDD/2
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Vin
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Delay Definitions
Vin
Vout
Vin
Propagation delay
input
waveform
50%
tp = (tpHL + tpLH)/2
tpHL
t
tpLH
Vout
90%
output
waveform
signal slopes
50%
10%
tf
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tr
t
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2.12 Modeling Propagation Delay
Model circuit as first-order RC network
vout (t) = (1 – e–t/)V
R
vout
where  = RC
C
vin
Time to reach 50% point is
t = ln(2)  = 0.69 
Time to reach 90% point is
t = ln(9)  = 2.2 
Matches the delay of an inverter gate
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2.13 Power and Energy Dissipation
 Power consumption: how much energy is consumed
per operation and how much heat the circuit
dissipates

supply line sizing (determined by peak power)
Ppeak = Vddipeak

battery lifetime (determined by average power dissipation)
p(t) = v(t)i(t) = Vddi(t)

Pavg= 1/T  p(t) dt = Vdd/T  idd(t) dt
packaging and cooling requirements
 Two important components: static and dynamic
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 Propagation delay and the power consumption of a gate are
related
 Propagation delay is (mostly) determined by the speed at which
a given amount of energy can be stored on the gate capacitors

the faster the energy transfer (higher power dissipation) the faster the
gate
 For a given technology and gate topology, the product of the
power consumption and the propagation delay is a constant

Power-delay product (PDP) – energy consumed by the gate per switching
event
 An ideal gate is one that is fast and consumes little energy, so
the ultimate quality metric is

Energy-delay product (EDP)
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3. CMOS Technology
 The basic building blocks in CMOS logic circuits are
MOSFET Transistors .
 MOSFET transistors are further broken down into
depletion type and enhancement type.
 The terms depletion and enhancement define their basic
mode of operation.
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MOS Transistors
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Depletion-type MOSFET
 The basic construction of an n-channel MOS is provided
below:

Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Figure 3.1. n-Channel depletion-type MOSFET
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Basic Operation and Characteristics
 Gate-to-source voltage = 0 (figure 3.2)
 Results :

Attraction for the positive potential at the drain by the free
electrons of the n-channel.

A current (IDSS) is established between the drain and the source
(figure 3.3.).
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Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Figure 3.2: n-channel depletion-type MOSFET with VGS = 0 and
an applied VDD
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Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Figure 3.3: Drain and transfer characteristics for an nchannel depletion-type MOSFET
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Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Figure 3.4: Reduction in free carries in channel
due to a negative potential at the gate terminal
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 By applying a negative potential at the gate (VGS < 0), the
electrons are pressured toward the p-type region substrate
(charge repel) and the holes are attracted from the p-type
substrate (opposite charge attraction) as shown in figure
3.4.
 Depending on the magnitude of VGS, a level of
recombination between electrons and holes will occur that
will reduce the number of free electrons in the n-channel
available for conduction.
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 The more VGS is negative, the higher the rate of recombination.
 The resulting level of drain current is therefore reduced with
increasing negative bias for VGS. The pinch-off level (VGS = VP)
yields ID = 0.
 Positive values of VGS will draw additional electrons from p-type
substrate, resulting in an increase of the drain current.
 As the gate-source voltage continue to increase in the positive
direction, Fig.3.3 reveals that the drain current will increase at a
rapid rate.
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P-channel depletion-type MOSFET
 Its behavior and characteristics are reverse to those of an –channel MOSFET.
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Figure 3.5: p-channel depletion-type MOSFET with IDSS = - 6 mA
ad VP = + 6V
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Symbols
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Fig. 3.6. Graphic symbols for (a) n-channel depletion-type MOSFETs
and (b) p-channel depletion-type MOSFETs.
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2N3797 Motorola n-channel depletion-type
MOSFET.
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
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Enhancement-type MOSFET
 Inexistence of channels
between the drain and the source.
 VGS will allow or disallow the
formation of a channel.
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Fig. 3.7. n-Channel enhancement-type MOSFET.
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Basic Operation and Charcteristics
 VGS = 0 => no current (no channel)
 As VGS increases in magnitude, the concentration of
electrons near the SiO2 surface increases until eventually
the induced n-type region can support a measurable flow
of current between the drain and the source.
 The level of VGS that results in a significant increase in the
current id called the threshold voltage VT or VGS(Th).
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Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
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Fig. 3.8. Channel formation in the n-channel
enhancement type MOSFET.
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 As VGS is increased beyond the threshold level, the density
of free careers in the channel will increase, resulting in an
increased level of a drain current.
 If VGS is hold constant and increase the level of VDS, the
drain current will eventually reach a saturation level. The
levelling off of ID is due to a pinching-off process.
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Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
Fig. 3.9. Change in channel and depletion region with
increasing level of VDS for a fixed value of VGS.
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Symbols
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
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Summary Table
Electronic Devices and
Circuit Theory:9/e
Robert Boylestad
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Gate
Source
Drain
Substrate (Body)
(a) NMOS transistor
VG
VS
VD
(b) Simplified symbol for an NMOS transistor
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NMOS transistor
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Gate
Drain
Source
Substrate (Body)
VDD
(a) PMOS transistor
VG
VS
VD
(b) Simplified symbol for an PMOS transistor
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PMOS transistor
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(from MIT’s Open Web Course)
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Defining the CMOS Technology
 Static complementary CMOS - except during switching, output
connected to either VDD or GND via a low-resistance path

high noise margins


full rail to rail swing
VOH and VOL are at VDD and GND, respectively

low output impedance, high input impedance

no steady state path between VDD and GND (no static power consumption)

delay a function of load capacitance and transistor resistance

comparable rise and fall times (under the appropriate transistor sizing
conditions)
 Dynamic CMOS - relies on temporary storage of signal values on
the capacitance of high-impedance circuit nodes

simpler, faster gates

increased sensitivity to noise
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CMOS Circuit Topology

Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
In2
PUN
InN
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
F(In1,In2,…InN)
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
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b) Dual PUN and PDN
 PUN and PDN are dual networks

DeMorgan’s theorems



(A + B)’ = A’.B’
(A.B)’ = A’ + B’
a parallel connection of transistors in the PUN corresponds to a series
connection of the PDN
 Complementary gate is naturally inverting (NAND, NOR, NOT)
 Number of transistors for an N-input logic gate is 2N
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CMOS Complements
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PDN
PUN
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Examples of CMOS Gates
VDD = 5V
Vi
0(L)
5(H)
Q1
OFF
ON
Q2
Vo
ON 5(H)
OFF 0(L)
Q2
p-channel
Vo
Vi
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Q1
n-channel
CMOS inverter
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CMOS NAND
 Use 2n transistors for n-input gate
 p-channel in parallel, n-channel in series
 Add output inverter to convert to AND
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CMOS NOR
Like NAND -- 2n transistors for n-input gate
p-channel series, n-channels in parallel
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(from Wakerly’s Text)
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NAND vs NOR
 For a given silicon area, PMOS transistors are have higher ON resistance than
NMOS transistors => Output High voltage is lower due to series connection in
NOR.
NOR
NAND
(from Wakerly’s Text)
•NAND output
LOW voltage is
not as badly
compromised
Result: NAND gates are preferred in CMOS.
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CMOS characteristics
 Essentially no DC current flow into MOS gate terminal
 Gate has capacitance, C which MUST be charged then discharged for switching
 Required power is CPDV2f ; where f is switching frequency, CPD is the power
dissipation capacitance
 Very little (0(nA)) current in output chain, except during switching when both transistors
are partially on
 More power required when signal rise times are small since transistors are on longer
 Symmetric output structure ==> equally strong drive (IOH, IOL) in LOW and HIGH states
This is why..
1. Power dissipation in PCs increase with
clock frequency
2. There is a lot of research on low
voltage logic devices (5V, now 3.3V
common)
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CMOS families and typical specifications
 VOHMIN=VDD-0.1V, VIHMIN=0.7Vcc, VILMAX=0.3VDD, VOLMAX=0.1V
 3V  VDD  18V (original 4000 family), 2V  VDD  6V (newer HC family)
 Input source and leakage currents: <1A
 Output current: typically 4mA but can be as high as 24mA
 Families: original 4000 family (slower, lower power dissip.)

74FAMnnn: FAM = family type, nnn=function number – faster

54FAMnnn: same as 74FAMnnn but for military apps.

FAM : HC (High Speed CMOS), HCT (HC TTL compatible), VHC/VHCT (Very High
speed), FCT/FCT-T(Fast CMOS TTL compatible/ with TTL VOH)

Egs: 74HC04 – hex inverter. IOLMAX=20  A, IOHMAX=-20A.
 NB: Special handling precautions hold as CMOS can be damaged by very a
small electrostatic discharge
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