Download A Low-Power Low-Voltage 10-bit 100

A Low-Power Low-Voltage 10-bit 100MSample/s Pipeline A/D Converter Using
Capacitance Coupling Techniques
Kazutaka Honda, Student Member, IEEE, Masanori Furuta, Member, IEEE, and
Shoji Kawahito, Senior Member, IEEE
Adviser : Hwi-Ming Wang
Student : Wei-Guo Zhang
Date : 2009/7/14
Outline
 ABSTRACT
 INTRODUCTION
 DESIGN OF KEY BUILDING BLOCKS
 MEASUREMENT RESULTS
 CONCLUSION
 REFERENCES
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Abstract
 This paper presents a low-power low-voltage
 10-bit 100-MSample/s pipeline analog-to-digital converter
using capacitance coupling techniques
 A capacitance coupling sampleand-hold stage achieves high
SFDR with 1.0-V supply voltage at a high sampling rate
 A capacitance coupling folded-cascode amplifier
 effectively saves the power consumption of the gain
stages of the ADC in a 90-nm digital CMOS technology
 SNDR of 55.3dB ;SFDR of 71.5 dB
 power consumption is 33mW at 1.0V supply voltage
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Introduction
 High-performance ADC is one of the key analog building
blocks in system-on-a-chip (SoC)
 visual and telecommunication
 To exploit advanced sub-100-nm CMOS technology
optimized for digital systems, the ADC is desired to be
designed with the same devices and supply voltage as those
used for the digital system.
 As device feature size is scaled down, digital circuits benefit
greatly from both speed and power dissipation. For analog
circuits, however, the decrease of supply voltage
consequently causes reduced signal swing and degraded
performances in switches and amplifiers
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Introduction
 Pipeline architectures have been widely employed in
applications requiring
 high speed and high resolution with relatively low power
dissipation
 supply voltage of 1.2 v
 For lower-voltage operation,the switched opamp (SO)
technique is proposed to overcome the switch driving
problem caused by an insufficient gate-source voltage
 This technique tends to slow operation due to slow transients
from the opamp being switched on and off. Moreover, to
maintain the same signal-to-noise ratio (SNR) with a lower
supply voltage, the thermal noise in the circuit must also be
proportionately reduced .This means that the sampling
capacitance must be increased to reduce KT/C noise.
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Introduction
 This paper proposes two capacitance coupling techniques for
low-power low-supply-voltage pipeline ADCs in sub-100-nm
CMOS technology
 A prototype 10-bit 100-MSample/s pipeline ADC employing
these techniques achieves low-power and low-distortion
characteristics in 1.0-V 90-nm CMOS
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DESIGN OF KEY BUILDING BLOCKS
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DESIGN OF KEY BUILDING BLOCKS
 In low-voltage operation, one of the most difficult problems in
a S/H stage is the high on-resistance of sampling switches
due to the reduced gate-source voltage
 The switched opamp formed in a charge transfer S/H
architecture has disadvantages in terms of gain bandwidth
and noise
 The flip-around architecture.This technique requires
 Additional time for starting up from the off-state of the
opamp
 limits the sampling rate
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DESIGN OF KEY BUILDING BLOCKS
 The schematic of the proposed S/H circuit with a capacitance
coupling technique.
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DESIGN OF KEY BUILDING BLOCKS

 This configuration
achieves high sampling
rate with low distortion,
because of the low onresistance of switches
and no start-up time of
the amplifier
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 In our design,  is 0.82
with Csh=2pF Cc=1pF
Cin=0.15pF

Csh / / Cc
Csh / / Cc  Cin
T
10
Cl
 gm
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DESIGN OF KEY BUILDING BLOCKS
 This amplifier utilizes a dynamical-bias gain boosting
technique to have sufficient signal swing and allows the
output swing of 0.8 vpp in differential signal under a 1.0-V
power supply
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DESIGN OF KEY BUILDING BLOCKS
 The conventional S/H
stage has a relatively
large harmonic distortion
 SFDR=61.2dB
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 Using the capacitance
coupling technique
 SFDR=84.8dB
 It indicates that the
CCSH architecture can
achieve low-distortion
sampling with 1.0-V
supply voltage
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DESIGN OF KEY BUILDING BLOCKS
 A class-AB capacitance coupling folded-cascode (CCFC)
amplifier. The simulated DC open-loop gain is about 76 dB
and the gain bandwidth (GBW) of the first stage’s amplifier is
1.5 GHz
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DESIGN OF KEY BUILDING BLOCKS
 Vod is the overdrive
voltage of the input
transistor and Io is the
unit bias current
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 The settling time can be
reduced to 40% without
increasing the static
power
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DESIGN OF KEY BUILDING BLOCKS
 Including the bias circuits, and clock generator, the total static
power dissipation of the ADC is estimated to be 26.6 mW with
1.0-V supply voltage
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MEASUREMENT RESULTS
 Two types of prototype pipeline ADCs were fabricated in a
90-nm, six-metal one-poly (6M1P) digital CMOS technology
 The total power consumption of the first prototype is only
30 mW consisting of 28.5 mW for analog and 1.5 mW for
digital at 100 MSample/s with a 1.0-V supply excluding the
digital output drivers
 The second prototype consumes 33 mW, which means that
the on-chip error correction logic consumes 3 mW at 100
MHz
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MEASUREMENT RESULTS
 Differential Non-Linearity and Integral Non-Linearity
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MEASUREMENT RESULTS
 The FFT spectra for 12
MHz input sampled at
100 MSample/s
 The SNDR and SFDR
are improved by 11 and
26 dB
 ENOB=8.9bit
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 Without calibration
 SNDR and SFDR by
44 and 45.5 dB
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MEASUREMENT RESULTS
 SNDR and SFDR of
both prototypes as a
function of conversion
rate at an input
frequency of 10 MHz
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 SNDR and SFDR of 2nd
by 53.1and 68.4dBat the
Nyquist frequency of 50
MHz
 The SNDR keeps above
50 dB up to 200 MHz
while the SFDR
degrades for over
Nyquist input frequency
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MEASUREMENT RESULTS
 The SNDR and SFDR
of the second
prototype atVDD=0.9V
are 54.1 and 69.8 dB
 The SFDR remain
above 64 dB down to
 SNDR and SFDR=55.3
and 71.5 dB
0.8 V at 100MS/s.
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MEASUREMENT RESULTS
 FOM1 of ADC given by
FOM 1 
Power
2 ENOB  Fs
 FOM2 which reflect the
difficulties for dynamic
range limited designs,
defined by
FOM 2 
Power
VDD
2 ENOB  Fs
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Conclusion
 This paper describes capacitance coupling techniques to
reduce the power dissipation of a 10-bit 100-MSample/s
pipeline ADC while keeping low distortion in 90-nm CMOS
process
 The prototype ADC at 100 MSample/s achieves 8.9 ENOB
and SFDR of 71.5 dB at 1.0-V supply voltage and dissipates
only 33 mW
 This ADC is useful for wideband visual and communication
systems.
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REFERENCES
 [1] International Technology Roadmap for Semiconductors, Semiconductor Industry
Association, 2005.
 [2] B. Hernes, A. Briskemyr, T. N. Andersen, F. Telstø, T. E. Bonnerud,andØ.Moldsvor,
“A1.2V220 MS/s 10 bit pipeline ADCimplemented in 0.13 m digital CMOS,” in IEEE ISSCC
2004 Dig. Tech. Papers,Feb. 2004, pp. 256–257.
 [3] R. Wang, K. Martin, D. Johns, and G. Burra, “A 3.3 mW 12 MS/s 10 bit pipelined ADC in
90 nm digital CMOS,” in IEEE ISSCC 2005 Dig.Tech. Papers, Feb. 2005, pp. 278–279.
 [4] M.Waltari and K. A. I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE J. SolidState Circuits, vol. 36, no. 1, pp. 129–134, Jan.2001.
 [5] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital
converter,” IEEE J. Solid-State Circuits, vol. 34, no.5, pp. 599–606, May 1999.
 [6] K. Honda, M. Furuta, and S. Kawahito, “A 1 V 30 mW 10 bit 100 MSample/s pipeline A/D
converter using capacitance coupling techniques,”in Symp. VLSI Circuits 2006 Dig. Tech.
Papers, Jun. 2006, pp.276–277.
 [7] M. Furuta, S. Kawahito, and D. Miyazaki, “A digital calibration technique for capacitor
mismatch for pipelined analog-to-digital converters,” IEICE Trans. Electron., vol. E85-C, no.
8, pp. 1562–1568, Aug. 2002.
 [8] D. Miyazaki, M. Furuta, and S. Kawahito, “A 75 mW 10 bit 120 MSample/s parallel
pipeline ADC pipeline A/D,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC 2003), Sep.
2003, pp. 719–722.
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