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Transcript
Decoupling Capacitance Allocation for Power Supply Noise Suppression Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh School of Electrical & Computer Engineering Purdue University Supported in part by SRC, Intel, NSF Outline • • • • • • Motivation Power Supply Noise Estimation Decoupling Capacitance (decap) Budget Allocation of Decoupling Capacitance Experiment Results Conclusion Motivation • Power supply noise is a serious issue in DSM design – – – – Noise is getting worse as technology scales Noise margin decreases as supply voltage scales Power supply noise may slow down circuit performance Power supply noise may cause logic failures • Decoupling capacitance is an effective way to alleviate power supply noise – Decap buffers switching activities by supplying part of the current demand – Peak noise can be reduced Problem Formulation • Given a floorplan with switching activities information available for each module: – Determine how much decap is required by each module to keep the supply noise below a specified upper limit – Allocate white-space to each module to meet its decap budget • Related issue – Determine worst case power supply noise for each module in the floorplan – Allocate the existing white space in the floorplan Power Supply Network—RLC Mesh VDD Rp :Current Source Lp : VDD pin VDD VDD VDD Current Distribution in Power Supply Mesh Illustration :Connection point, Current contribution Current flowing path VDD (1) (3) :VDD pin (5) VDD (2) (6) Module A B C Current Distribution in Power Supply Network • Distribute switching current for each module in the power supply mesh • Observation: Currents tend to flow along the leastimpedance paths • Approximation: Consider only those paths with minimal impedance --shortest, second shortest, … I1 I 2 I n I Z1 I1 Z 2 I 2 Z n I n Ij Yj n Yi i 1 I, j 1,2, n Current Flowing Paths and Power Supply Noise Calculation • Power supply noise at a target module is the voltage difference between the VDD pin and the module i3(t)• Apply KVL: VDD R2 L2 R1 L1 C1 i1(t) C2 k i2(t) V (k ) noise Pj T ( k ) (i j RP LP jk jk di j dt ) Decoupling Capacitance Budget • Decap budget for each module can be determined based on its noise level • Initial budget can be estimated as follows: Ch arg e : Q (k ) I ( k ) (t )dt 0 Noise ratio : Decap : max(1, V V (k ) noise (lim) ) noise 1 (lim) C ( k ) (1 )Q ( k ) /V noise, k 1,2, M • Iterations are performed if necessary until noise at each module in the floorplan is kept under certain limit Allocation of Decoupling Capacitance • Decap needs to be placed in the vicinity of each target module • Decap requires WS to manufacture on – Use MOS capacitors • Decap allocation is reduced to WS allocation • Two-phase approach: – Allocate the existing WS in the floorplan – Insert additional WS into the floorplan if required Allocation of Existing White Space B w2 A D WS C w1 E w3 Allocation of Existing WS--Linear Programming (LP) Approach • LP Approach: • Objective: Maximize the utilization of available WS • Existing WS can be allocated to neighboring modules using LP • Notation: S: Sk : ( j) S : sum of allocated area of WS k decap budget H k 1 jN k s.t. xk( j ) : ws allocated to mod j N k : neighbors set of WS k ( j) x k Sk , jN k WS of S xk( j ) , max imize k 1, 2 ,, H k H ( j) ( j) x S , k mod j from WS k k 1 xk( j ) 0, j, k j 1, 2 ,, M Insert Additional WS into Floorplan If Necessary • Update decap budget for each module after existing WS has been allocated • If additional WS if required, insert WS into floorplan by extending it horizontally and vertically • Two-phase procedure: – insert WS band between rows based the decap budgets of the modules in the row – insert WS band between columns based on the decap budgets of the modules in the column Moving Modules to Insert WS Original floorplan 0 Moving modules in y+ direction ExtY B A 1 A 2 B 1 D 3 E D C 2 C WS band F 3 F E 4 G (a) G (b) Experimental Results Comparison of Decap Budgets (Ours vs “Greedy Solution”) Circuit decap budget (nF) (our method) decap budget (nF) (“greedy solution”) Percentage (%) apte 27.73 32.64 85.04 xerox 8.00 13.50 59.30 hp 3.45 6.18 55.80 ami33 0 0.80 0.00 ami49 10.28 24.80 41.50 playout 42.91 61.67 69.6 Experimental Results for MCNC Benchmark Circuits Modules Existing WS (m2) (%) 9 751652 (1.6) decap Inacc. 27.73 WS (m2) (%) 0 (0) xerox 10 1071740 (5.5) 8.00 hp 11 695016 (7.8) ami33 33 ami49 playout Circuit apte Added WS (m2) (%) 4794329 (10.3) Est. Peak Noise (V) before 1.95 Est. Peak Noise (V) after 0.24 0 (0) 528892 (2.7) 0.94 0.20 3.45 306076 (3.5) 300824 (3.4) 1.09 0.23 244728 (21.3) 0 N/A 0 0.16 0.16 49 2484496 (7.0) 10.28 891672 (2.5) 463615 (1.3) 1.45 0.25 62 5837072 (6.6) 42.91 792110 (0.9) 3537392 (4.0) 1.23 0.24 Budget (nF) Floorplan of playout Before/After WS Insertion Conclusion • A methodology for decoupling capacitance allocation at floorplan level is proposed • Linear programming technique is used to allocate existing WS to maximize its utilization • A heuristic is proposed for additional WS insertion • Compared with “Greedy” solution, our method produces significantly smaller decap budgets