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Free-space parallel multichip interconnection system
Xuezhe Zheng, Philippe J. Marchand, Dawei Huang, and Sadik C. Esener
A parallel data-communication scheme is described for interchip communication with free-space optics.
We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach
in which free-space optical interconnect modules can be simply integrated on top of an electronic
multichip module 共MCM兲. Our packaging architecture is based on a modified folded 4-f imaging system
that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive
assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built,
supports 48 independent free-space channels with eight separate laser and detector chips, in which each
chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic
carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic 共OE兲 free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact
at only 10 in.3 共⬃164 cm3兲 and is scalable because it can easily accommodate additional chips as well as
two-dimensional OE device arrays for increased interconnection density. © 2000 Optical Society of
America
OCIS codes: 200.4650, 200.2610, 200.0200, 250.0250.
1. Introduction
Exchanging data at high speed over sufficiently long
distances is perceived as a potential bottleneck in
future high-performance electronic processing
systems.1–3 New approaches to dense and highspeed interconnections are needed at various levels of
a system-interconnection hierarchy: board to board,
MCM to MCM on a board 共MCM is multichip module兲, chip to chip on a MCM, and on chip. Over the
next ten years free-space optical interconnects
共FSOI’s兲, when combined with electronics, offer a potential solution4 –9 at the inter- and the intra-MCMlevel interconnects, promising large interconnection
density, high distance–bandwidth product, low power
dissipation, and superior cross-talk performance at
high speeds.10 –13
Optoelectronic 共OE兲 devices including VCSEL’s,
light modulators, and light detectors have now been
developed to a point at which they can enable highspeed and high-density FSOI.14 –17 However, a key
issue that needs to be addressed is the integration of
The authors are with the Department of Electrical and Computer Engineering, University of California, San Diego, La Jolla,
California 92093-0407. X. Zheng’s e-mail address is xzheng@
ece.ucsd.edu.
Received 20 July 1999; revised manuscript received 21 March
2000.
0003-6935兾00兾203516-09$15.00兾0
© 2000 Optical Society of America
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APPLIED OPTICS 兾 Vol. 39, No. 20 兾 10 July 2000
these devices with free-space optics into a system
environment. Indeed, a packaging architecture and
associated technologies need to be developed to integrate OE devices and optical components in a way
that is compatible with conventional electronic packaging. In this paper we present a fully packaged
FSOI system for multichip interconnection. A conventional printed circuit board 共PCB兲 and ceramic
board is populated with silicon and OE chips and
mated to a FSOI layer that is assembled separately.
Design considerations, packaging approaches, and
testing results are provided.
In many MCM applications, data distribution from
and to the memory chips that may reside on a MCM
or on an adjacent board can become one of the major
bottlenecks in high-performance system implementation. This type of performance-limiting data path
can be replaced by use of an FSOI module with crossbar connectivity between point-to-point interconnects
as shown in Fig. 1. This system can be made into a
standard data-communication module for various applications 共interconnect processors, digital signal processing chips, memory, and telecom interface
circuits兲.
2. Demo System Packaging
Since system-level packaging has become the key issue hindering the feasibility and performance potential of future FSOI systems,18 –21 new techniques have
to be developed and system demonstrators have to be
built to prove the feasibility of FSOI in digital sys-
OE module 关multichip carrier containing the VCSEL,
MSM, and silicon chips兴 and 共ii兲 the optics 共FSOI兲
module. In our assembly approach and sequence a
mechanical pin–pinhole technique combined with
alignment marks makes the alignment of the two
modules a rather straightforward task.
Fig. 1. Architecture for multichip interconnection with free-space
optics
tems. To this end, a functional demonstrator system was built to evaluate module-packaging
approaches and to characterize free-space OE links.
In the current system 4 one-dimensional 共1D兲 VCSEL
chips 共1 ⫻ 12 elements each兲 and 4 1D metal–
semiconductor–metal 共MSM兲 detector chips 共1 ⫻ 12
elements each兲 are used as light source and photodetector arrays, respectively, in which laser and detector devices are on a 250-␮m pitch. The VCSEL’s
operate at 850 nm and exhibit a 15-deg divergence
angle 共full angle at 1兾e2兲, and the detector aperture is
80 ␮m ⫻ 80 ␮m. Laser-driver circuits, receiver 共amplifiers兲 circuits, and router circuits are integrated
on three silicon chips and included in the system.
VCSEL arrays are optically connected to corresponding detector arrays 共one-to-one diagonally; see Fig. 2兲.
Data can be fed electronically to any one of the silicon
chips and routed to the VCSEL’s through driver circuits. The silicon chips also contain receiver circuits
connected to the detectors; and data can be read out
electronically from each silicon chip independently.
The overall packaging approach consists of the assembly of two different packaging modules: 共i兲 the
A.
Free-Space Optical Module
The free-space optical module performs one-to-one
imaging between the VCSEL and detector arrays.
Different types of optical systems can be used to
achieve this, including diffractive or refractive microlens arrays, conventional refractive optics, or hybrid systems. Optical systems based on micro-optics
are attractive because of their potential for miniaturization, thus reducing the overall system cost and
volume. However, the performance of microlens arrays in terms of uniformity is still limited by their
fabrication and quality-control processes. Macrolenses, in contrast, lead to bulkier systems but are
presently easier to procure and have better quality
control. Hence, at the present time, our systempackaging experiments will be limited to the use of
macro-optics until the performance of microlens arrays reaches the desired standards. Hence, for demonstration purposes, an optical module that consists
of a modified folded 4-f imaging system based on offthe-shelf macro-optical components was selected and
implemented 关see Fig. 3共a兲兴. The concave mirrors
are used for folding the system as well as for aberration compensation, acting as a field lens. On the
basis of simulation and experimental results from an
earlier demonstration system,22 we know that in such
a system the most critical tolerance requirement is
Fig. 2. System schematics. 1D OE chips are optically connected by a vertical system. All the VCSEL arrays are optically connected
to their corresponding detector arrays 共one-to-one diagonally兲.
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Fig. 4. Multichip carrier is composed of two layers: 共a兲 baseboard 共ceramic兲, 共b兲 chip-registration board. Fiducial pins and
pinholes are used to register all the boards. 共c兲 Multichip carrier
after assembly.
Fig. 3. 共a兲 Optical system configuration with only commercially
available devices. 共b兲 Code V view of the optics.
the top mirror tilt, ⫾3 arc min to maintain 90% link
efficiency. The other tolerances in the system are
fairly loose and easily controlled within a reasonable
range by traditional optomechanical fabrication and
packaging technologies. Furthermore, the mirror
tilt can be used as a compensation for the image shifts
that are due to the other misalignments in the system. Essentially, by tilting of the mirrors, the optical axis of the system can be brought back to the
center of symmetry of the OE chips. Thus a plastic
module is fabricated to hold the optics and provide a
single adjustment: mirror tilt 关see Fig. 3共b兲兴. Four
registration pinholes are included on the module so
that it can be mated to the OE module later. Simulations 共performed with CodeV23兲 showed that for
VCSEL’s with a 15-deg divergence angle, and no misalignments in the system, 90% of the energy emitted
from the VCSEL will be encircled in a spot no bigger
than 17 ␮m in the output plane. With all the possible misalignments caused by both the fabrication
and the assembly of the system taken into account,
the simulated worst-case condition shows that the
spot size increases to ⬃20 ␮m with a 25-␮m maximum lateral shift at the detector plane.
B.
Optoelectronic Module
The OE module is a MCM that is made of a ceramic
or a PCB chip carrier supporting all the electronic
and OE chips 共see Fig. 4兲. The chip carrier supports
the overall package, provides positioning for the
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APPLIED OPTICS 兾 Vol. 39, No. 20 兾 10 July 2000
chips, and enables electrical input–output 共I–O兲 by
means of integrated chip 共IC兲 pins to the package. It
is composed of a ceramic base board and a PCB chipregistration board, which were procured through
standard PCB fabrication services, such as those offered by most electronic packaging companies.24
The chip-registration board is a ring with alignment
marks that are used to accurately place the VCSEL
and detector arrays with respect to the baseboard.
The two boards are registered to each other through
fiducial pins and pinholes, which match the pinholes
in the optical module to be assembled later. The
positioning information is transferred to the chips by
means of alignment marks on the chip-registration
board and to the optics through the fiducial pin and
pin holes.
The OE module assembly is carried out as follows.
First, the OE chips 共VCSEL and MSM兲 are attached
共active face up兲 on a temporary transparent substrate
that contains alignment marks both for locating the
chips and subsequently aligning the substrate itself
to the chip-registration board 共Fig. 5, top兲. The attachment of the OE chips to the transparent substrate is performed with use of photoresist as an
adhesive material. Meanwhile, the baseboard and
the chip-registration board are simply stacked together with mechanical pins. Second, the temporary substrate is aligned to the stacked baseboard
and chip-registration board 共Fig. 5, middle兲. The
chips are then die attached to the baseboard with
thermally cured epoxy. Next, all the OE chips are
released from the temporary substrate by use of a
suitable solvent 共acetone兲, and the temporary substrate is removed. Then the silicon chips are wire
bonded to the baseboard. All steps are carried out
with a standard mask aligner.
The OE module before the wire-bonding step is
shown in Fig. 6共a兲. Finally, by means of snapping
Fig. 5. Chip transfer sequence. The VCSEL and detector chips
are attached to a temporary transparent mask 共top兲. The temporary substrate is aligned to a cavity composed of the baseboard and
the chip-registration board 共or ring; middle兲. All the OE chips are
released from the temporary substrate while they are die attached
on the multichip carrier 共bottom兲.
the plastic optical module onto the OE module, the
system is completed 关see Fig. 6共b兲兴.
3. Test Setup and Limitations
To test performance, the completed FSOI module is
mounted on and interfaced to a test PCB 关see Fig.
7共a兲兴 so that testing signals can either be fed into or
read out from the system. The overall signal path in
the test setup is shown in Fig. 7共b兲, which includes
I–O connectors, metal traces on PCB 共transmission
lines兲, electrical pins, metal traces on the ceramic
base board 共another transmission line兲, wire bonds to
the ceramic chip, and the OE interconnection core.
After the OE interconnection core the signal travels
through an e.s.d.-protected output pad on the CMOS
chip, the connections and transmission lines again,
before it can be detected by external testing equipment.
At high speed the characteristics of the transmission lines and the parasitic LC 共conductance and capacitance, respectively兲 components of the electrical
connections become critical. Therefore time-domain
reflectometry measurements were performed to characterize the entire signal path. Results show that
transmission-line discontinuities and parasitic LC
exist in the signal path 共see Fig. 8兲, effectively limiting the maximum operating speed of the overall system.
To further quantify this, the overall testing environment was modeled in H-Spice by inclusion of the
signal path with the data obtained from the timedomain reflectometry measurements together with
our transceiver and receiver circuits as well as a simple attenuation model for the free-space transmission. The results indicate that the system speed is
limited mostly by the CMOS e.s.d. output pads and by
the parasitic LC that is due to the electrical pins and
the transmission-line discontinuities. Figure 9
shows the waveforms at different locations along a
link 关see Fig. 7共b兲兴 when a 250-MHz square wave
signal is propagated through the system. The signal
is degraded by the transmission lines and electrical
pins as shown in Fig. 9共a兲. It is reshaped by the
input e.s.d. pad, because it includes a superbuffer
关Fig. 9共b兲兴. The signal after the OE interconnection
core exhibits only ⬍0.5-ns rise–fall time 关Fig. 9共c兲兴.
However, the rise–fall time increases to 2 ns after the
signal passes again through the e.s.d. output pad
关Fig. 9共d兲兴. Simulations show that the rise–fall time
of the e.s.d. pad with standard high-pressure 0.5-␮m
fabrication process is as high as 0.7 ns 共this would be
improved with use of more-aggressive CMOS fabrication兲. The signal at the output end is degraded
further by the transmission lines and the electrical
board connections 关Fig. 9共e兲兴. Hence the maximum
speed of the system is limited to ⬃250 MHz, although
the OE interconnection core can potentially work up
to 1 GHz 共rise–fall 0.5 ns兲.
4. Testing Results
Fig. 6. OE module and FSOI module after assembly. 共a兲 Optoelectronic module, 共b兲 plastic free-space optics module snapped
onto the OE module.
Detailed experimental tests were performed on the
test setup. These tests include basic link parameter
measurements, high-speed parallel single-hop interconnections; bidirectional chip-to-chip parallel interconnections, and multihop interconnections.
The basic link parameters of the system were
tested previously without driver and receiver circuits
and are reported in Ref. 22 We measured high link
efficiencies 共to as great as 93%兲 and low cross talk
10 July 2000 兾 Vol. 39, No. 20 兾 APPLIED OPTICS
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Fig. 7. Free-space OE interconnection module interfaced with traditional PCB-based electronics. 共a兲 Test setup; 共b兲 schematic of the
signal path in the test setup.
共⫺20 dB dominated by electrical cross talk in the OE
device arrays兲.
High-speed link performance is tested for both sin-
Fig. 8. Time-domain reflectometry measurements to characterize
parasitic LC and discontinuity in transmission loss 共T.L.兲 on the
PCB.
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APPLIED OPTICS 兾 Vol. 39, No. 20 兾 10 July 2000
gle and parallel channels. Figure 10 shows the output from a single VCSEL-to-MSM link with a 200MHz square wave input 共close to the simulation
results described in Section 3兲.
To test the validity of the modular packaging
scheme, multiple links sharing the same optical apertures were tested simultaneously. Figure 11
shows the output signals from two channels that belong to different VCSEL–MSM links sharing the
same optical aperture. They are driven by the same
data signal. The results indicate that the free-space
optical module performs adequately for all the interconnection channels. Data in two separate chips
can be exchanged at the speed of 200 MHz in parallel
over 12 channels.
The output signal from one VCSEL–MSM link was
also used to drive another VCSEL–MSM link to implement a two-hop optical communication link. We
demonstrated the operations of such a link to as great
as 50 MHz. The result is shown in Fig. 12. The
upper curve is the input signal for the first link. The
Fig. 9. System-level simulation with H Spice. The system maximum output is 250 MHz.
lower curve is the output signal after the second
stage. Here the output signal from the first link was
used to drive the second link directly, and there was
no signal processing or logic circuit in between.
From both the simulation and the experimental results above, we know that the signal from one link
has a rise–fall time of more than 2 ns. Therefore,
compared with the first VCSEL–MSM link, the second link has the same signal path but is driven by a
lower-quality input signal. This is why the two-hop
link operation speed is limited at 50 MHz.
If signal-shaping circuits were used in between the
two links, operation should be possible at the same
speed as a single link. We also noted that a significant delay exists, resulting mostly from the electronics. The characterization of this delay and of the
signal jitter will be critical at higher speeds to understand the limitations imposed by synchronization
considerations.
5. Packaging Issues
The modular packaging approach described here allows for compensation of the lateral and the tilt misalignments of all the elements in the system with
only two tilt alignments of the top mirror. The simulation and the experimental results22 show that longitudinal 共Z in Fig. 13兲 misalignments in such a
modified 4-f system are not an issue, since their tolerance is several hundreds of micrometers, which is
much looser than the tolerance of the mechanical
fabrication means used for this module. The mirror
tilt can compensate all lateral misalignments 共in x
and y兲 and component tilt caused by fabrication, assembly, and packaging. As shown in Fig. 13, with
the first lens as the reference plane and assuming
that the mirror has misalignments of ␦x, ␦y, ␦␣ 共in the
XOZ plane兲 and ␦␤ 共in the YOZ plane兲, we get the
conjugate coordinates of an OE element by tracing
the chief ray under a thin lens and paraxial approximation,
冋
冉
共 x, y兲 ⫽ ⫺x ⫹ 2 f ⫺ d ⫺
冉
⫺y ⫹ 2 f ⫺ d ⫺
冊
f2
2f ␦x
␪x ⫹
⫺2f ␦␣;
R
R
冊
册
f2
2f ␦y
␪y ⫹
⫺2f ␦␤ ,
R
R
(1)
where d is the distance between the OE device and
the lens, f is the lens focal length, and R is the radius
of the curvature of the mirror. ␪x, ␪y are the relative
tilts between the OE module and the lens. If R, d,
and f satisfy the relationship expressed as
R ⫽ f 2兾f ⫺ d,
(2)
and if we account for the fact that d ⬍⬍ f, Eq. 共1兲 can
be simplified to
共x⬘, y⬘兲 ⬇ 关⫺x ⫹ 2␦x ⫺ 2f ␦␣; ⫺y ⫹ 2␦y ⫺ 2f ␦␤兴.
(3)
Without in-plane rotation error, the interconnection
misalignments are then obtained as
dx ⫽ ␦Vx ⫹ ␦Mx ⫹ 2␦x ⫺ 2f ␦␣,
dy ⫽ ␦Vy ⫹ ␦My ⫹ 2␦y ⫺ 2f ␦␤,
10 July 2000 兾 Vol. 39, No. 20 兾 APPLIED OPTICS
(4)
3521
Fig. 12. Two-stage interconnection. The upper curve is the input signal for the first link. The lower curve is the output signal
after two-stage interconnection
Fig. 10. 200-MHz OE parallel interconnection is achieved
through one VCSEL–MSM link. The two curves in the figure are
outputs from different channels on the same chip. 共a兲 Two channels in the same single link; 共b兲 single-link works at 200 MHz with
square wave input.
Fig. 11. Traces of independent VCSEL–MSM links sharing the
same optical aperture.
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APPLIED OPTICS 兾 Vol. 39, No. 20 兾 10 July 2000
where 共␦Vx, ␦Vy兲 and ␦Mx, ␦My are the lateral misalignments of VCSEL’s and detectors, respectively.
Once we assemble the two modules together,
共␦Vx, ␦Vy兲, 共␦Mx, ␦My兲, and 共␦x, ␦y兲 are fixed. Therefore all misalignments are linear with the mirror tilt
for small angles. By changing the top mirror tilt, we
can always compensate the lateral misalignments
caused by the other sources in the system. In addition, if the OE devices to be connected have a symmetric center, two sets of VCSEL–MSM links under
the same optical system can be aligned simultaneously, as is the case in our system.
In our demonstration system, a lithographic chip
transfer technique was used to package the OE module and ensure accurate relative positioning of OE
chips. Soon, large numbers of VCSEL’s and MSM’s
Fig. 13. Mirror tilt for misalignment compensation.
paragraph. For a MSM detector, which usually has
tens of micrometers in aperture, in-plane rotation
will therefore not be a serious issue when surfacemounting techniques are used to assemble the OE
arrays on the chip carrier.
6. Conclusions
Fig. 14. Worst case of in-plane rotation misalignment.
will be integrated into a single two-dimensional array, such that accurate VCSEL-versus-MSM positioning is obtained automatically through the
fabrication of these OE arrays. If only one array-toarray interconnection is established through a single
optical path, then the OE chip lateral positioning
error will no longer be an issue. The only parameter
of concern, then, is the OE chip in-plane rotation.
The source of in-plane rotation positioning errors is
due to the assembly of the OE chips on the chip
carrier. With proper chip assembly techniques, inplane rotation error can be readily controlled to be
quite small. For example, let us assume that an
interconnection system similar to the one described
in this paper is to be implemented between an 8 ⫻ 8
mm array of VCSEL’s and detectors in which the
array pitch is the same as for the 1D devices, i.e., 250
␮m 共32 ⫻ 32 arrays of devices兲. The maximum inplane rotation tolerance obviously depends on the
actual implementation of the optics. In the system
described above, if the chief ray location within the
detector aperture is used as the criterion, the rotation
tolerance can be expressed as
␥ ⫹ ␾ ⱕ d兾 冑2a,
(5)
where d is the detector aperture size and a is the
lateral dimension of the OE array. As shown in Fig.
14, assuming that two OE arrays to be connected
have the same rotation error in the worst case, and
assuming that the detector aperture is 50 ␮m, the
rotation tolerance is very tight at 2 mrad 关according
to relation 共5兲兴.
Popular commercially available chip assembly
techniques are through-hole mounting and surface
mounting. Through-hole mounting is probably not
good enough, because the holes are typically 1–2 mil
larger than the pins of the pin grid array 共PGA兲 or
digital image processing 共DIP兲 packages, which will
largely exceed the available rotation-tolerance budget. However, if surface-mounting techniques are
used for assembling the OE chip directly on a board,
in-plane rotation errors should be sufficiently small.
A high-resolution pick-and-place machine can
achieve ⬃1.8-mrad rotation accuracy.25 The maximum runout of the imaging spot on top of its corresponding detector is only ⬃20 ␮m for the worst case
based on the same assumptions as in the previous
Various types of free-space interconnection systems
with different link topologies can be built with stateof-the-art OE technology, but alignment issues at the
system-packaging level are still one of the major obstacles for practical implementation. In this paper
we have shown that by using commercially available
devices and services, as well as some simple assembly
techniques, high-performance 共high optical link efficiency and low optical cross talk兲 FSOI systems can
be implemented successfully. With off-the-shelf
lenses, standard PCB fabrication, and passive assembly techniques, a free-space OE system link speed of
200 MHz兾channel was demonstrated. The modular
packaging approach is quite tolerant and compatible
with conventional optomechanics and electronic
packaging techniques.
The operation speed of the system was found to be
limited by the testing environment: the CMOS
e.s.d. pads, parasitic LC of the electrical pins, and
impedance mismatch of the transmission lines. A
more careful design of the test electronics should allow for much higher speed of operation. The system
is also scalable and could easily accommodate twodimensional arrays of OE devices. With simple refinements, this packaging approach can also be
extended to three-dimensional stacked electronic
chips integrated with a two-dimensional transmitter
and receiver array for dramatically increasing the
number of silicon chips in the MCM.26 As shown in
Fig. 1, every chip stack communicates with its nearest neighbors, and the system scales as a MESH of
chip stacks. This indicates that high-performance
free-space parallel data routing schemes are achievable with this modular packaging approach.
This research was sponsored by the Defense Advanced Research Projects Agency 共DARPA兲 and by
the U.S. Air Force Research Laboratory under agreement F30602–97-2– 0122. The U.S. government is
authorized to reproduce and distribute reprints for
governmental purposes notwithstanding any copyright annotation thereon.
The authors thank Roy K. Matthies and John Gunderson from Arma Design, Incorporated, San Diego,
California, for invaluable advice on packaging technologies and for the fabrication of all the PCB’s used
in the system. The Honeywell Technology Center
graciously provided the VCSEL and MSM arrays.
References
1. A. V. Krishnamoorthy and D. A. B. Miller, “Firehose architectures for free-space optically interconnected VLSI circuits,” J.
Parallel Distrib. Comput. 41, 109 –114 共1997兲.
2. P. J. Marchand, A. V. Krishnamoorthy, G. I. Yayla, S. C. Esener, and U. Efron, “Optically augmented 3-D computer: sys10 July 2000 兾 Vol. 39, No. 20 兾 APPLIED OPTICS
3523
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
tem technology and architecture.” J. Parallel Distrib. Comput.,
Special Issue on Optical Interconnects 41, 20 –35 共1997兲.
G. A. Betzos and P. A. Mitkas, “Performance evaluation of
massively parallel processing architectures with threedimensional optical interconnections,” Appl. Opt. 37, 315–325
共1998兲.
J. W. Goodman, F. J. Leonberger, S. C. Kung, and R. A. Athale,
“Optical Interconnections for VLSI systems, ” Proc. IEEE 72,
850 – 866 共1984兲.
L. A Bergman, W. H. Wu, A. R. Johnston, R. Nixon, S. C.
Esener, C. C. Guest, P. Yu, T. J. Drabik, M. Feldman, and S. H.
Lee, “Holographic optical interconnects in VLSI,” Opt. Eng. 25,
1109 –1118 共1986兲.
W. H. Wu, L. A Bergman, A. R. Johnston, C. C. Guest, S.C
Esener, P. K. L. Yu, M. R. Feldman, and S. H. Lee, “Implementation of optical interconnections for VLSI,” IEEE Trans.
Electron. Devices 34, 706 –714 共1987兲.
R. K. Kostuk, J. W. Goodman, and L. Hesselink, “Optical imaging applied to microelectric chip-to-chip interconnections,”
Appl. Opt. 24, 2851–2858 共1985兲.
D. A. B. Miller, “Physical reasons for optical interconnection,”
Intl. J. Optoelectron. 11, 155–168 共1997兲.
A. V. Krishnamoorthy and D. A. B. Miller, “Scaling
optoelectronic-VLSI circuits into the 21st century: a technology roadmap,” IEEE J. Sel. Top. Quantum Optoelectron. 2,
55–76 共1996兲.
M. R. Feldman, S. C. Esener, C. C. Guest, and S. H. Lee,
“Comparison between optical and electrical interconnects
based on power and speed considerations,” Appl. Opt. 27,
1742–1751 共1988兲.
F. Kiamilev, P. J. Marchand, A. V. Krishnamoorthy, S. Esener,
and S. H. Lee, “Performance comparison between optoelectronic and VLSI multistage interconnection networks,” IEEE
J. Lightwave Technol. 9, 1674 –1692 共1991兲.
A. V. Krishnamoorthy, P. Marchand, F. Kiamilev, K. S.
Urquhart, and S. Esener, “Grain-size consideration for optoelectronic multistage interconnection network,” Appl. Opt. 31,
5480 –5507 共1992兲.
G. Yayla, P. J. Marchand, and S. Esener, “Speed and energy
analysis of digital interconnections: comparison of on-chip,
off-chip, and free-space technologies,” Appl. Opt. 37, 205–227
共1998兲.
R. A. Morgan, J. Bristow, M. Hibbs-Brenner, J. Nohava, S.
Bounnak, T. Marta, J. Lehman, and Y. Liu, “Vertical cavity
surface emitting lasers for spaceborne photonic interconnects,”
3524
APPLIED OPTICS 兾 Vol. 39, No. 20 兾 10 July 2000
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
in Photonics for Space Environments IV, E. W. Taylor, ed., Proc
SPIE 2811, 232–242 共1996兲.
A. V. Krishnamoorthy, L. M. F. Chirovsky, W. S. Hobson, R. E.
Leibenguth, S. P. Hui, G. J. Zydzik, K. W. Goosen, J. D. Wynn,
B. J. Tseng, J. A. Walker, J. E. Cunningham, and L. A.
D’Asaro, “Vertical-cavity surface-emitting lasers flip-chip
bonded to gigabit-per-second CMOS circuits,” IEEE Photon.
Technol. Lett. 11, 128 –130 共1999兲.
F. B. McCormick, T. J. Cloonan, A. L. Lentine, J. M. Sasian,
R. L. Morrison, M. G. Beckman, S. L. Walker, M. J. Wojcik,
S. J. Hinterlong, R. J. Crisci, R. A. Novotny, and H. S. Hinton,
“Five-stage free-space optical switching network with fieldeffect transistor self-electro-optic-effect-device smart-pixel arrays,” Appl. Opt., Special Issue on Optical Computing 33,
1601–1618 共1994兲.
A. L. Lentine, D. J. Reiley, R. A. Novotny, R. L. Morrison, J. M.
Sasian, M. G. Beckman, D. B. Buchhoz, S. J. Hinterlong, T. J.
Cloonan G. W. Richards, and F. B. McCormick, “Asynchronous
transfer mode distribution network by use of an optoelectronic
VLSI switching chip,” Appl. Opt. 36, 1804 –1814 共1997兲.
S. Patra, J. Ma, V. Ozguz, and S. H. Lee, “Alignment issues in
packaging for free-space optical interconnects,” Opt. Eng. 33,
1561–1570 共1994兲.
D. Zaleta, S. Patra, V. Ozguz, J. Ma, and S. Lee, “Tolerancing
of board-level-free-space optical interconnects,” Appl. Opt. 35,
1317–1327 共1996兲.
D. T. Neilson and E. Schenfeld, “Plastic modules for free-space
optical interconnects,” Appl. Opt. 37, 2944 –2951 共1998兲.
F. Quercioli, B. Tiribilli, A. Mannoni, and S. Acciai, “Optomechanics with LEGO,” Appl. Opt. 37, 3408 –3416 共1998兲.
X. Zheng, P. Marchand, D. Huang, O. Kibar, N. Ozkan, and S.
Esener, “Optomechanical design and characterization of a
printed-circuit-board-based free-space optical interconnect
package,” Appl. Opt. 38, 5631–5640 共1999兲.
Optical Research Associates, 3280 East Foothill Boulevard,
Suit 300, Pasadena, Calif. 91107.
ARMA Design, 7887 Dunbrook Road, Suite A, San Diego, Calif.
92126.
Versatronics American, Hayward Melville, 1110 Madera
Drive, Tracy, Calif. 95376 – 8951; http:兾兾versatronics.tstma.com兾Specs.html.
S. C. Esener and P. Marchand, “3D optoelectronic stacked
processors: design and analysis,” in Optics in Computing ‘98,
P. Chavel, D. Miller, and H. Thienpont, eds., Proc SPIE 3490,
541–545 共1998兲.