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2008 International Conference on Microelectronics 1 An Ultra-Low-Voltage Ultra-Low-Power OTA With Improved Gain-Bandwidth Product Milad Razzaghpour Abbas Golmakani Electrical Engineering Faculty, Sadjad University Mashhad, Iran Email: [email protected] Electrical Engineering Faculty, Sadjad University Mashhad, Iran Email: [email protected] Abstract— A 0.5-V ultra-low-power improved operational transconductance amplifier (OTA) using the transistors operate in weak inversion is presented in this paper. The proposed topology based on a bulk-driven input differential pair employed a gain-stage in the Miller capacitor feedback path to improve the “pole-splitting” effect. Simulations in a standard 0.18 µm CMOS process resulted on rail-to-rail input and output swings, considerable enhancement in unity-gain bandwidth and also the DC gain with the power consumption of only 1.02 μW. In this paper, an ultra-low-power and ultra-low-voltage OTA based on a bulk-driven input differential pair is modified to be able to overcome the problem of low DC gain and unitygain bandwidth. Under weak inversion, the unity-gain bandwidth is enhanced with introducing a gain-stage in the Miller capacitor feedback path. This gain-stage (commongate) eliminates the right half-plane (RHP) zero and improves the “pole-splitting” effect. Additionally, the DC gain is improved with the “cascode” technique. Index Terms— Bulk-driven differential pair, full swing, Miller compensation, operational transconductance amplifier (OTA), right half-plane zero control, ultra-low-voltage, ultra-low-power II. CONVENTIONAL RHP ZERO CONTROLLING TECHNIQUES Clearly, a disadvantage of the Miller frequency compensation technique is the inconvenience of the right halfplane (RHP) zero. This RHP zero degrades the phase margin and leads to instability of operational amplifiers. Two different approaches of controlling the RHP zero are shown in Fig. 1 [10]. As observed in Fig. 1 (a), the nulling resistor controls the RHP zero by the basis of displacement. On the other hand, as prevent the shown in Fig. 1 (b), the employed gain-stage input current from going directly through the Miller capacitor, thus, the RHP zero will eliminate [11]. As can be observed in Fig. 1 (a), at frequencies near unitygain frequency, the reactance of the compensation capacitor can be ignored. Therefore, the output resistance seen by can be derived as given by I. INTRODUCTION A S the feature size of modern CMOS processes scale down, the maximum allowable power supply continuously decreases. The main drawback on implementing low-voltage CMOS circuits is the threshold voltage which does not scale down as the same rate as power supply reduction. Therefore, some circuit structures become obsolete and there is the need for alternative architectures which is able to satisfy a wide voltage range in order to achieve a desirable signal-to-noise ratio [1]-[5]. Unquestionably, the weak inversion region of a MOS transistor is suitable for implementing ultra-low-power circuits. Nevertheless, under weak inversion the unity-gain bandwidth (UGBW) will be limited due to the extremely low currents. In the context of low-voltage and low-power design, one of the most suitable structures is the bulk-driven differential pair, which allows a large input signal swing [6]is [8]. However, since the bulk-source transconductance smaller than the gate-source transconductance and owing to the extremely low currents, the gain-bandwidth product (GBW) will be considerably limited [9]. (1) while from Fig. 1 (b), the output resistance seen by be expressed as [10] ≈ R ( ) can (2) And also, M. R. Author is with Sadjad University, Mashhad, Iran. ( corresponding author to provide phone: +98 915 123 8309; e-mail: [email protected]). A. G. Author is with Sadjad University, Mashhad, Iran (e-mail: [email protected]). 1-4244-2370-5/08/$20.00 ©2008 IEEE ≈ R = R C ∙ (3) Obviously, it can be deduced from (2) and (3) that noticeable reduction of by a factor of is the basis of 17 2008 International Conference on Microelectronics 2 Fig. 2. Improved ultra-low-voltage ultra-low-power OTA. g a b improvement in “pole-splitting” effect which is valid only for Fig. 1 (b) and not for Fig. 1 (a). Therefore, increasing the , mainly due to magnitude of the non-dominant output pole the employed gain-stage , leads to a proportional enhancement in unity-gain bandwidth. III. PROPOSED ARCHITECTURE According to the expressions that are derived from the model BSIM3v3 in weak inversion [12], the drain current of a MOS transistor can be presented by W L exp q VGS VTH T 1 − exp −q VDS T ≈ IDS T g (6) ( ) C (7) and are the transconductances of and where presented in (5) and (6) respectively. Consequently, the output pole has split from the dominant pole by a factor of ( ) + which leads to an enhancement in unitygain bandwidth, when compared to the nulling resistor approach. As discussed in [13], slew rate can be achieved with a complex approach because input transistors and will never become cut off and the current of never flows in just one of them. In this work, from the expressions in relation with the compensation capacitor , the slew rate is given by (4) where is the characteristic current, is the charge of the electron or hole, is the inclination of the curve in weak inversion, is the Boltzman constant and is the absolute temperature. The transconductance and can be found as presented in (5) and (6) respectively, where is the body effect coefficient and ∅ is the Fermi potential [10]. g =q ∅F VSB The presented architecture based on a bulk-driven input differential pair is illustrated in Fig. 2 which allows a large input signal swing. Due to the extremely low currents in ultralow-power condition, it can be deduced from (5) and (6) that the DC gain as a function of and can be limited. In this work, the output impedance of the first stage is increased, mainly thanks to the employed transistor , thus, the DC gain is improved. Under weak inversion, the unity-gain bandwidth is also enhanced using a gain-stage (common-gate) in the Miller capacitor feedback path as done by transistor . Consequently, the gain-bandwidth product (GBW) is considerably enhanced. As observed in Fig. 2, the compensation result is to keep the dominant pole roughly the same as normal Miller compensation and to increase the output pole by . As mentioned in approximately the gain of a single stage section II, under weak inversion, the magnitude of the output pole can be given by Fig. 1. The RHP zero controlling structures: (a) nulling resistor approach, (b) gain-stage (common-gate) approach. IDS = IS = (5) 18 2008 International Conference on Microelectronics 3 TABLE I OPERATIONAL AMPLIFIER PERFORMANCE BENCHMARK INDICATORS CMOS technology (µm) Power supply (V) Unity gain frequency (KHz) Open loop gain (dB) Phase margin (degree) Signal swing (V) Slew-rate (V/ms) CMRR (dB) Power consumption (μW) FoM (dB.KHz/V.nW) Passive elements Simulation or Measurement This work [13] [8] [14] 0.18 0.5 83.88 88.5 66.3 0 to 0.5 52.0 133.85 1.02 14.47 Rc = Not used S 0.35 0.6 13.02 73.5 54.1 0 to 0.6 14.7 67.4 0.55 2.89 Rc = 73 KΩ S 2.5 0.9 5.60 70 62 0.01 to 0.89 26.0 0.45 0.96 M 1.4 14 95 65 0.01 to 1.39 3 60 0.84 1.13 M So, VGS = VGS ∙ (11) With respect to (11) we can write IDS = W L W L IDS = IDS + IDS (12) Therefore, W L Fig. 3. Simulated open loop gain and phase of improved OTA. SR = IDS IDS that can be obtained from the operating point analysis given by the simulations. − and − Considering Fig. 2, transistor pairs form “composite transistors”. In terms of dc analysis, the drain-source voltage of transistor is given by (9). An analogous expression is achieved for . VDS = T ln 1 + 2 W L = VDS + VDS VGS = VDS + VDS ∙ (13) IV. SIMULATION RESULTS does not depend on the gate-source voltage, Consider that which is valid only for weak inversion and not for strong inversion [13]. In order that and are equal, and should be equal and constant. Therefore, the differential offset voltage of input transistors will reduce [13]. In order to avoid any systematic offset it is possible to derive an equation as follows. VGS W L The circuit was simulated in HSPICE with BSIM3v3.1 model based on a standard 0.18 µm CMOS process ( = 0.45 , = −0.5 ). Simulations resulted on considerable increase of unity-gain bandwidth to the value of 83.88 KHz, the improved DC gain of 88.5 dB, and a phase margin of 66.3o (see Fig. 3). The presented topology employed weak inversion transistors is capable of working at 500 mV of power supply with full rail-to-rail input and output swings and consuming only 1.02 μW. The reference current of the improved OTA, , was set equal to 130 nA. Additionally, with the large load capacitor of 15 pF and with a compensation capacitor of 5 pF, the slew rate of 52 V/ms is resulted (see Fig. 4). Table I shows a comparison with other low-voltage and low-frequency operational amplifiers to evaluate this work using a figure of merit (FoM) defined as: (9) W L W L W L There will be no systematic offset voltage as long as (13) is satisfied. Although, the weak inversion operation implies large transistors dimensions, it minimizes the noise effect, especially flicker noise which is important in a MOS transistor in low-frequency applications [10]. (8) C = W L (10) 19 2008 International Conference on Microelectronics [7] [8] [9] [10] [11] [12] [13] Fig. 4. Slew-rate of improved OTA at 500-mV supply. FoM = (P (G )∙(U .) )∙(P [14] ∙ ) (14) The proposed architecture shows a noticeable FoM even under the condition of ultra low supply voltage of 500 mV. V. CONCLUSION This work proposed a 0.5-V improved ultra-low-power OTA based on a bulk-driven input differential pair and employing a gain-stage in the Miller capacitor feedback path. Simulation results have been presented to confirm the considerable improvement in unity-gain bandwidth and also the DC gain, when compared to other ultra-low-power lowfrequency OTAs with conventional RHP zero controlling techniques. The presented topology allows rail-to-rail input and output swings at 500-mV of power supply, therefore, it works beyond the limit given by the threshold voltages. ACKNOWLEDGMENT The authors wish to thank the reviewers for their useful comments and suggestions. REFERENCES [1] [2] [3] [4] [5] [6] W. Redman-White, “A high bandwidth constant and slew-rate railto-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems,” IEEE J. Solid-State Circuits, vol. 32, pp. 701– 712, May 1997. S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design,” IEEE J. Solid-State Circuits, vol. 40, pp. 2373–2387, Dec. 2005. J. H. Huijsing and D. Linebarger, “Low-voltage operational amplifier with rail-to-rail input and output ranges,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1144–1150, Dec. 1985. J. M. Carrillo, J. F. Duque-Carrillo, G. Torelli, and J. L. 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