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Title: “CarrICool: Interposer supporting optical signaling, liquid cooling, and power conversion for 3D chip stacks” Corresponding author: Toke Meyer Andersen1,2, [email protected] Co-‐authors: Florian Krismer1, Johann W. Kolar1, Thomas Toifl2, Thomas Brunschwiler2, Arvind Sridhar2, Ningning Wang3, Zoran Pavlovic3 1 Swiss Federal University of Technology (ETH), Zurich, Switzerland 2 IBM Research – Zurich, Rüschlikon, Switzerland 3 Tyndall National Institute, University College Cork, Ireland Abstract: CarrICool is a European FP7 ICT project that aims at delivering a game-‐changing 3D packaging platform for scale-‐up of future many-‐core exascale compu-‐ ting systems. In CarrICool, advanced More-‐than-‐ Moore components required to scale to energy efficient computing performance are developed and integrated into a modular and multifunctional interposer. Three critical packaging elements are implemented on the CarrICool interposer: 1) low thermal gradients for Beyond-‐CMOS and silicon photonic devices are provided by integrating single-‐ phase water-‐cooling cavities, 2) high granularity integrated voltage regulators using integrated high-‐ Figure 1: The 2.5D integration of the CarrICool integrated voltage quality power inductors and deep trench capacitors regulator module (iVRM) with the power switches (green) being co-‐ integrated with the CPU (red), and the TSV inductor (brown) and deep to support energy-‐efficient power delivery to trench decoupling capacitors (blue) being integrated on the passive many-‐core CPU’s, and 3) increased off-‐chip I/O interposer. bandwidth enabled through low-‐cost and low-‐loss passive optical coupling to silicon photonic wave guides. The availability of through silicon vias (TSV) in the interposer and the possibility to apply MEMS processes allow for 2.5D integration of buck converters with high quality factor TSV inductors, see Fig-‐ ure 1. The TSV inductor including low-‐loss ferromagnetic cores shown in Figure 2 takes advantage of the larger volume available on the passive interposer to achieve a high quality factor. The in-‐ terposer also implements high voltage deep trench capacitors for decoupling. Only the power switches and control functionality are integrated in the CPU die. The distributed yet near-‐die implemen-‐ tation of the buck converter components significantly reduces in-‐ terconnect parasitics. The result is a fast and efficient granular Figure 2: Through silicon via (TSV) inductors with power distribution, thereby serving the static and dynamic voltage magnetic core material leverage the interposer scaling demands of multiple voltage domains. area to design a high quality factor inductor for the CarrICool integrated voltage regulator demonstra-‐ tor. The TSV inductors are designed for high in-‐ The PwrSoC 2014 E-‐poster will focus on the CarrICool integrated ductance density at large load currents, thereby voltage regulator and the TSV inductor with magnetic material. bridging the performance gap between discrete We will show our current progress, focusing on an overall multi-‐ and embedded inductors. objective optimization that identifies the efficiency versus power density Pareto limit of the suitable converter topologies, TSV in-‐ ductor, deep submicron silicon technologies, and the appropriate switching frequency range.
