Download Document

Security and Trust Issues in 3D ICs
Soha Alhelaly ([email protected])
Advisor
Prof. Jennifer Dworak ([email protected])
What
a 3D
Integrated
That’s
aCircuit?
Cool
and powerful technology 
Caniswe
reduce
this ratio
to save
TSVs
(Through ≈
Silicon
Vias)
Traditional
time and power?
Feature size of today’s transistors
22
nm
The purpose of the
System
Now, SAMSUNG is producing 3D chips TSV is to connect die
Distance from chip to chip acrossinaa board
2.2likecm
Let’s stack bare die on top
3D stack≈just
ASIC
routes on a board
of each other and put them
A 3D V-NAND
in a single chip package.
presentation
package
Memory
First mass-produced
What is the ratio?
Ratio =
Processor
𝟐.𝟐 ∗ 𝟏𝟎−𝟐
𝟐.𝟐 ∗ 𝟏𝟎−𝟖
Memory
Silicon Interposer
Processor
ASIC
=
three-dimensional
𝟏The purpose
of the
𝟔 chip
NAND
flash
=
𝟏𝟎
−𝟔
Interposer
is to make a
𝟏𝟎
connection line up.
That
is 1 million!!
Bump
Circuit BoardWhat else
has this ratio?
𝑫𝒊𝒔𝒕𝒂𝒏𝒄𝒆 𝒕𝒐 𝑴𝒂𝒓𝒔
𝑫𝒊𝒔𝒕𝒂𝒏𝒄𝒆 𝒃𝒆𝒕𝒘𝒆𝒆𝒏 𝑫𝒂𝒍𝒍𝒂𝒔 𝒂𝒏𝒅 𝑭𝒐𝒓𝒕𝒘𝒐𝒓𝒕𝒉
=
𝟏
𝟏𝟎−𝟔
Distance between die ≈ 10 μmThat’s a big difference!!
=
SAMSUNG website: http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=12990
𝟏𝟎𝟔
Accessremove
to all die
Can’t
and
So
what
does
this mean for security?
Overall
variability
comes
only
through
AnCan’t
entirevisually
board
in a
analyze
die once
isthe
likely
to die
increase
base
package
inspect
die once
assembled
It’s
easier to hide things and harder to
assembled
find them!!
Potential 3D Security Issues
Trojan Extra Die
Trojan Firmware in
Programmable Die
Counterfeit Die or
Interposer
Trojan Circuit
Interposer
Upper Die
2D Trojan in Real
Die
Interposer
Base Die
We are currently focusing on detecting an extra die in the stack
What kinds of extra die could be
added and what could they do?
Extra Die in stack
can cause complex
Trojans
Extra processor
Extra memory
and controller die
Out of
band TSV’s
How can we detect Extra Die in the Stack?
Voltage drop
Temperature Profile
Side Channel Analysis
(Power and Delay)
X-rays or other imaging
approaches