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High Reliability Multiport Multiphase DC Hub
Weixing Lin
Member, IEEE
University of Aberdeen
Fraser Noble Building
Aberdeen, AB24 3UE, UK
[email protected]

Abstract— A Multiphase Multiport DC hub concept is
proposed in this paper. The DC hub is capable of connecting
multiple DC transmission lines with different DC voltages.
Multiphase LCL inner circuit is used to increase the power rating
and reliability of each port. Adding a phase in the inner AC circuit
increases power transfer and improves utilization of DC cables
which have higher rating than the high power switches. When
fault happens at the converter bridge of the hub, the faulted phase
of the converter bridge is tripped and the inner LCL circuit is
reconfigured to a balanced AC system with reduced number of
phases. On permanent DC fault at any DC transmission line, the
port connected to the faulted DC transmission line is tripped so
that the DC fault will not affect normal operation of the other
remaining DC transmission line. Simulation of a 3-port 4-phase
DC hub in PSCAD/EMTDC demonstrated the high reliability of
DC hub after tripping a port and after tripping a phase.
Index Terms—DC power systems, DC power transmission,
DC-DC power conversion, HVDC converters, HVDC
transmission, wind energy
I. INTRODUCTION
With the increasing size of offshore power parks and the
need for new interconnectors, there has be growing interest in
developing offshore DC grid in the Europe. The Future
offshore grid will be developed using DC transmission as the
AC transmission is not suitable with long cables, and the
onshore European Super Grid will also be based on DC
technology since AC system is already highly congested and
incapable of integrating the remote intermittent renewable
energy sources[1]-[3].
A straightforward idea of DC grid is interconnecting
different DC transmission lines using DC circuit breakers
(CB)[4]. The DC grid based on DC circuit breakers (CB)
confronts the challenge of coordination of protection for a large
DC grid [5]-[6]. Because of very small DC cable impedance,
the DC faults will cause widespread voltage collapse and
require fast (few ms) discriminative (coordinated) protection
action.
The recent proposed VSC converters with DC fault current
blocking capability [7]-[9] could reduce the requirements on
operating time and fault current breaking capability of DC CBs.
However, it requires blocking all the VSC converters in a DC
grid if any point is at DC fault. This implies there will be power
interruption of the whole DC grid and is unacceptable for large
This project is funded by European Research Council under the Ideas
program in FP7; grant no 259328, 2010.
Dragan Jovcic
Senior Member, IEEE
University of Aberdeen
Fraser Noble Building
Aberdeen, AB24 3UE, UK
[email protected]
DC grids as large power interruption will cause severe stability
problems to the AC grids where the DC grids are embedded.
Also it requires significant increase number of the used IGBTs
to achieve DC fault current blocking capability which pushes
up the cost.
A method of using anti-paralleled thyristors in each sub
module of MMC is proposed in [10] to aid the MMC ride
through temporarily DC faults. This method is suitable for
point to point VSC-HVDC but may not be suitable for large DC
grids as the method in [10] requires the AC system to be short
circuited using the anti-paralleled thyristors which will also
cause large disturbance to the AC grids.
From the above literature review, it can be concluded that it
will be very challenging to achieve high system reliability and
safety if DC CBs are used solely as protection means in DC
grids. Also, as technology progress, the future HVDC
transmission will use higher voltage level than the current
operating HVDC lines. The planned VSC-HVDC lines to the
year 2017 use different voltage levels [11]. The DC grids based
on DC CB are not able to interconnect DC lines with different
voltage levels or to incorporate HVDC lines based on LCC
which has typically higher voltage level than VSC [12].
The future DC grid might be a mixture of local DC grids
based on DC CBs and some kind of DC fault decoupling and
DC voltage stepping devices to interconnect with large regional
DC systems.
The DC-DC multiport converter based on high frequency
solid state transformers presented in [13] is able to interconnect
multiple DC lines with different voltage levels. However, all
the associated VSC converter bridges need to be blocked if any
of the connected DC line is at DC fault, which imply power
transmission of all the interconnected DC lines are interrupted.
To provide DC fault blocking capability of the technology in
[13] and similar technologies based on transformers, VSC with
fault current blocking capabilities such as the topologies
discussed in [7]-[9] are required. On any DC line fault, the VSC
associated with the fault DC line will firstly be blocked and
then the faulted line with its associated VSC will be isolated
using AC circuit breaker. As transformers are used, mass and
space requirements are increased which makes this technology
uncompetitive for offshore application. Also, VSC with fault
blocking capabilities need more IGBT which pushes up the
cost.
In order to limit propagation of DC faults and achieve high
safety and reliability of the DC grid, we are investigating a
multiport DC hub in this article. The DC hub is an update of the
2
DC/DC converter of [14]. It can intrinsically limit the
propagation of DC faults by use of a specially designed inner
LCL circuit. Also the DC hub is able to interconnect multiple
DC lines at different voltage levels.
As the hub will provide GW-level power exchange between
multiple DC systems, reliability of the hub itself is of
paramount importance. The hub should be designed and
operated that no single fault will bring down the whole hub.
To meet the reliability requirement, multiple-phase LCL DC
hub is introduced in this paper. If a phase can be
tripped/connected without affecting power transfer on other
phases, then we have excellent operating flexibility and
immunity to internal faults. Adding additional phases also
increases power capability of the port, which makes the VSC
converters in the hub to better match the power ratings of DC
cables and overhead DC line.
adopt 3-phase topology, and the power is limited by the rating
of IGBTs. Meanwhile, the available maximum power rating of
DC cable is higher than the maximum power rating of VSC
converter. A ±300kV submarine DC cable with a cross section
of 3000 mm2 has a power rating of 1484 MW if we use closed
laying and 1840MW if we use spaced laying [17]. Since DC
hub inner circuit is not restricted to 3-phase structure, we will
explore flexible expansions of the hub use multiphase topology.
Suppose the RMS current of each phase is Irms, the average
DC current through IGBT of each phase arm is:
I avg 
1
2


0
2 I rms sin(t )d (t ) 
2

I rms
(1)
Consider unit power factor, relationship of DC current of the
transmission line and current of each phase is
II. THE MULTIPHASE MULTIPORT LCL DC HUB
A. Topology of the hub
Topology of the proposed multiphase N-port LCL DC hub is
shown in Fig. 1 where a 4-phase topology is illustrated. At first
glance, the LCL DC hub looks like a number of LC-filter based
VSC converters paralleled at the AC side. However, the LC
circuit in the LCL DC hub is not used to perform harmonic
filtering but to limit fault current and provide interconnection of
VSC converters with different voltage ratings and. The usage of
the LCL circuit in the LCL DC hub is similar to the usage of
LCL circuit in LCL DC/DC converter [14] or LCL based VSC
converter [15].
The hub comprises N ports and 4 common AC buses. Each of
the N ports is comprised of 4 inductors Li, 4 capacitors Ci and
one 4-phase DC/AC bridge with switches (S1_i - S8_i). Each
phase of each port is connected to corresponding common AC
bus through a single phase AC circuit breaker CBiA − CBiD.
If any port is in permanent DC fault at the DC transmission
line, all the single phase circuit breakers associated with the
faulted port will be tripped to disconnect the port from the hub
so as not to affect the normal operation of the other un-faulted
ports in the hub.
On faults at the converter bridge(usually only one phase of
the converter bridge is at fault at a time), the single phase circuit
breaker associated with the fault phase of all the ports will be
tripped. The remaining phases are reconfigured to a new
balanced AC system by changing the phase angle differences
between phases.
If the above operating principles are achieved, the reliability
of the DC hub will be very high. Practically, there will be no
single failure that can bring down the whole DC hub.
B. Expandability of the hub using multiphase topology
It is well known that power rating of VSC is limited by the
limited current rates of IGBT[16]-[18] and the IGBT are
difficult to be paralleled.
The foreseen typical maximum power and voltage rating of
VSC converters to the year of 2015 by the three major HVDC
vendors is ±320kV, 1000MW [17]. These VSC converters
m *Vrms I rms  Vdc I dc
(2)
Where Vdc is the pole to pole DC voltage and m is the number
of phases. Relationship of RMS voltage and DC voltage is:
Vrms  M i *Vdc / (2 2)
(3)
Where Mi is the rated modulation index typically selected to be
0.95 to ensure some control margin. Substitute (3) into (2) and
considering (1), we have
I dc  m I avg / 4
(4)
The graph in Fig. 2 assumes that IGBTs are operated with
1500A DC collector current, and depicts the changes of DC
current and DC power versus number phases for a port
connecting to ±320kV DC transmission line. To extend the
power capacity of the hub, new phases instead of new port is
added.
C. Firing Logic for AC/DC converters in the ports
A fixed frequency central Voltage Controlled Oscillator
(VCO) is used to generate common reference angle for all
ports. Each phase(A,B,C,D) of each port(i=1,…, N) generates
phase j ac voltage vij given by:
vij  2Vi max M i cos(2 fot  ( j  1)  i )
(5)
where ωo=2πfo is operating frequency of all AC variables
which is fixed and common for all ports, Vmax
is the maximum
i
RMS line-neutral voltage, αi is the leading phase angle of vij
over the corresponding capacitor voltage. ∆φ is the phase
difference between adjacent phases, (2π/3 if 3 phases are
operating and π/2 if 4 phases are operating. The variables Mi
and i are control signals that enable 2 degree of freedom
control (active and reactive power) of each port.
3
There are numerous methods of generating AC voltage from
a given DC voltage, and Fig. 3 shows the bipolar modulation
that is used in the 2-level 3-port test hub of Table 1.
The switching frequency fs is selected as fs=3*fo which is the
lowest possible value giving symmetrical AC waveform, as
seen in Figure 3.
Port 1
R1dc
V1dc
C1d
S1_1
S3_1
S5_1
S7_1
L1
v1A
Port 2
CB2A
CB1A
CB1B
CB1C
CB1D
v1B
v1C
Bus_A
R1dc
C1d
S2_1
S6_1
S4_1
S8_1
S1_2
CB2B
v2A
CB2C
v2B
v2C
S3_2
S5_2
S7_2
C1d
S4_2
S6_2
S8_2
C1d
S3_i
S5_i
S7_i
Cid
S4_i
S6_i
S8_i
Cid
v2D
Bus_B
C1
R2dc
L2
CB2D
vcA
v1D
V1dc
Although we use 2-level AC/DC converters for simplicity, in
high power applications, modular multilevel converter
[19]-[20] should be one of the best choices for converting the
DC voltage to AC voltage. The power loss of each MMC
converter bridge is around 0.5% of its rated capacity[2].
V2dc
C2
vcB
S2_2
Bus_C
Bus_D
vcD Bus_G
Port N
RNdc
CNd
S1_N
S3_1
S5_1
S7_1
LN
vNA
vNB
vNC
Port i
CBiA
CBNA
CBNB
CBNC
CBiB
CBND
CBiD
Ridc
Li
RNdc
CNd S
2_N
S6_1
S4_N
viD
...
Vidc
viB
viC
CBiC
CN
S8_1
S1_i
viA
vND
VNdc
R2dc
...
vcC
VNdc
V2dc
Ci
S2_i
Vidc
Ridc
Fig. 1. Multiphase N-port DC hub topology
2500
Idc(kA)
3
2000
Idc
Pdc
2
1500
1000
1
Pdc(MW)
4
500
0
0
0
1
2
3
4
5
Number of phases
6
7
Fig. 2. Change of DC current and DC power versus number of phases
δ
Vidc
0
-Vidc
-π/2
vij
Mi*cos(2πfot+αi-(j-1)∆φ)
θij=2πfot+αi
-(j-1)∆φ
0
3π/2
π
Fig. 3. Bipolar Modulation for a phase "j" in port "i".
III. DESIGN AND CONTROLLABILITY OF THE LCL DC HUB
A. Parameters of the inner LCL circuit
The hub can incorporate any number of ports. The study in
this section describes design of a general port i. Each inductor
and capacitor for a port i is designed according to the following
two equations.
Li 
Ci 
M irVi max (Vcr )2  ( M ir ) 2 (Vi max ) 2
Pi r o
Pi r (Vcr )2  ( M ir ) 2 (Vi max ) 2
1
r 2
o (Vc )
M irVi max
(6)
(7)
Where Mi r is rated modulation index typically selected to be
0.95 to ensure control margin. Pir is the rated power of port i per
phase, Vcr is rated RMS magnitude of capacitor voltage.
B. Multiphase dq transformation
The multiphase dq transformation is defined as:
 xA 
 xd 
cos t cos(t   ) ... cos(t  (m  1) )   
  2

 xB  (8)
 xq   m   sin t  sin(t   ) ...  sin(t  (m  1) )   
x 
1/ 2
  
1/ 2 ...
1/ 2
 0
 xM 
x
cos t
 sin t
1
 A 
 x   cos(t   )
  xd 

sin(

t



)
1
B
 
  x  (9)
  
 q 
  
  x0 
 xM  cos(t  (m  1) )  sin(t  (m  1) ) 1
Where xA, xB, …, xM are variables in the stationary frame and
xd, xq, x0 are variables in the rotating frame. ∆φ is the phase
angle difference between adjacent phases and m is the total
number of phases.
In the multiphase LCL DC hub, dq variables obtained from
(8) or we can treat each phase separately and use single phase
dq transformation[21] to transform variables of each phase to
separate dq frames which rotate at electrical angles of
θj=2πfot+(j-1)∆φ.
Generally, dq variables obtained from (8) better reflects the
balance of the phases but large disturbances will be observed at
the dq variables during phase reconfiguration when the phases
are not balanced.
While dq variables obtained from each separate dq frame
enables each phase to be controlled independently. dq variables
of the un-faulted phases will remain unchanged if a phase is
tripped or reconnected to the hub.
4
C. Controllability of the hub
In a dq frame with d axis aligned to the common reference
angle from VCO, the AC voltage vector of the instantaneous
voltage vi is expressed as:
Vi  Vim i  Vid  jViq
(10)
Vid  Vi max M id ,Viq  Vi max M iq , M i  M id2  M iq2
(11)
Where Mid, Miq are D-Q components of PWM modulated
control signals and Vi  4Vidc / ( 2) .
Equations for the inductor current and capacitor voltages are:
ports will control local power. Suppose port k is selected to
maintain Vc and rewriting equation (18)in the following form
K cVcq 
K cVcd 
N
Viq
i 1, i  k
o Li


M kqVkmax
o Lk
Vid
M V max
 kd k
o Lk
i 1, i  k o Li
(20)
N

(21)
Mkq and Mkd are used to maintain Vcq and Vcd respectively.
max
jo Li Ii  jo Li ( Iid  jIiq )  Vi  Vc
N
N
i 1
i 1
jo Vc  Ci   I i
(12)
IV. CONTROL DIAGRAMS AND PHASE RECONFIGURATION
A. Control of power port
Mid is kept to its rated value Midr to ensure Vcd is maintained to
r
Vc according to (18). Midr is calculated according to
(13)
M idr 
M   M 
r 2
i
r 2
iq
(22)
In steady state, Vcq is maintained to be zero:
Vc  Vcd  jVcq  Vcd  Vc
Where Miqr is calculated according to:
(14)
where Vc is the RMS line-neutral AC voltage magnitude of the
capacitor voltage vc. On assumption of (14), from (10) and (12),
the AC current of port i is expressed as:
I id  Viq / (o Li )
(15)
I iq  (Vc  Vid ) / (o Li )
Considering (15), the real power per phase (Pi):
Pi  ViqVc / (o Li )  M iqVi maxVc / (o Li )
(16)
Equation (16) shows Pi can be controlled by Miq.
Considering (14) , the capacitor voltage in (13) becomes:
N
N
i 1
i 1
joVc  Ci   ( I id  jI iq ) (17)
In steady state, substitute the current expressed in (15) to (17)
we can get the following equation:
Viq


1
 o C  Vcq  

i 1 o Li
 i 1 o Li

N
N


V
1
 o C  Vcd   id

i 1 o Li
 i 1 o Li

N
N
(18)
Define
N
Kc  
1
i 1 o Li
 s C
(19)
The design of the hub ensures that Kc>0 is always guaranteed.
We will use one port to control central voltage Vc, and all other
M iqr 
Pi r o Li
Vi maxVcr
(23)
Fig. 4 shows control diagram of power controlling ports.
Each phase of each power port has its independent controller.
The phase different ∆φ between adjacent phases is set to 2π/m
so as to achieve balanced inner LCL AC circuit. The reference
angle for firing logic θj for each phase is output of voltage
controlled oscillator (VCO) plus corresponding phase shift.
Namely θj=2πfot-(j-1) ∆φ. The flag ‘Flag_Trip’ is used as an
order for reconfiguring the 4-phase AC circuit to 3-phase AC
circuit and will be discussed later.
Each power port is used to control its active power to the
power reference Pi ,puref . The power reference could be manually
set or derived from an upper layer central master. Mid is
maintained to its rated value according to (22).
Each power port controller also incorporates a droop loop
with the droop gain of Kdroop (Kdroop set to 4). If the absorbed
power exceeds the rated power of the voltage port, a positive
Vcqpu shows up. The droop loop takes Vpu
cq as an indicator to
reduce the inject power orders of each power port so that the
voltage port will not be severely over rated.
In Fig. 4, the control parameters are Kp1=0, Ki1=10. Each
per-unit power Pi pu is calculated taking the rated power of each
phase of each port as the base value.
B. Control of voltage port
Fig. 5 shows control diagram of the port that keeps capacitor
voltage vc. Similar to the power ports, each phase in the voltage
port is also independently controlled. To save space, only
controller of phase A and phase B is shown. Controller of phase
C and phase D are similar to phase A/B.
5
LCL circuit. ∆φ gradually increases from π/2 to 2π/3 during
the reconfiguration time span ∆T. ∆T is set to 0.1 sec.
Each phase of the voltage port is used to control Vcdpu and
Vcqpu . The per-unit capacitor voltages Vcdpu , Vcqpu are calculated
taking the rated AC voltage of the common buses as the base
value. Control gains are set as Kp2=0, Ki2=10.
To damp oscillations of capacitor voltage caused by large
disturbance such as DC faults, damping loop with a gain of
Kdamp (Kdamp set to 0.25)is incorporated in the controller of
voltage port. A second order low pass filter with a characteristic
frequency of 20Hz and damping ratio of 0.707 is applied to
filter the steady state values of Vcdpu , Vcqpu so as to obtain the
V. VERIFICATIONS
Detailed simulation of a 4-phase, 3-port DC hub in
PSCAD/EMTDC is used to validate the high reliability of
multiphase multiport LCL DC hub. DC voltage rating and
power rating of the 3-port hub is shown in Table 1. In Table 1
Power injecting to the hub is defined as positive power
direction (1). The operating frequency is 1250Hz, rated RMS
line to neutral capacitor voltage at the common AC bus is
378.5kV.
Table 1 Parameters of 3-port case
oscillation components of Vcdpu , Vcqpu .
C. Phase reconfiguration control
In the hub, each phase of each port is controlled
independently to enable smooth phase reconfiguration. In the
case of tripping one phase from a m phase hub, the phase
difference ∆φ is gradually increased from 2π/m to 2π/(m-1)
during the time span of ∆T. In the case of connecting additional
phase to a m phase system, the phase difference is decreased
from 2π/m to 2π/(m+1). The AC system imbalance only occurs
during the period of ∆T where phase reconfiguration takes
place. The LCL circuit is balanced before and after phase
reconfiguration.
In Fig. 4 and Fig. 5, the flag ‘Flag_Trip’ is used as an order
for reconfiguring the 4-phase LCL circuit to a balanced 3-phase
Port
1
2
3
Vidc(kV)
100
300
50
P (MW)
550
430
120
Li(H)
0.0146
0.0423
0.0341
Ci(uF)
1.054
0.207
0.469
Power direction
1
-1
-1
Ci
Ridc
CBiA
Li
iiA
viA
CBiB
S3_i
S1_i
iiB
viB
CBiC
iiC
CBiD
viC
S7_i
Vidc
Cid
iiD
viD
i1outD
Vidc
S6_i
S4_i
S2_i
fo
S5_i
S8_i
Cid
Ridc
VCO
Flag_Trip
∆φ
π/6
π/2
Cal
Pi& Qi
Cal
Pi& Qi
PiApu
1.0
Kp1+Ki1/s
pu
VcqA
-1.0
Kdroop
1.0
Mid,rate
PiBpu
Kp1+Ki1/s
pu
cqB
V
-1.0
Kdroop
1.0
Mid,rate
PiCpu
Kp1+Ki1/s
pu
VcqC
-1.0
Kdroop
1.0
PiDpu
Mid,rate
Kp1+Ki1/s
pu
cqD
V
-1.0
Kdroop
 
Mid,rate
Firing
Logic A
dq
dq
dq
dq
Cal
Pi& Qi
Pi ,ref
 
 
 
0 ∆T
Cal
Pi& Qi
θA
MiqA
MiA
MidA
αiA
MiqB
MiB
MidB
αiB
MiqC
MiC
MidC
αiC
MiqD
MiD
MidD
αiD
Fig. 4. Control Diagram of power ports
Firing
Logic B
θB
Firing
Logic C
θC
Firing
Logic D
θD
6
Fig. 6(c) shows AC currents of all the phases of port 1 and
the injected current (i1outD) of phase A to the common AC bus
Bus_A. Measuring point of i1outD is shown in Fig. 4. We can see
that the 4 phase currents are balanced before phase
reconfiguration and unbalanced during phase reconfiguration.
i1outD reduces to zero immediately following the tripping of
circuit breaker CB1D. i1D reduces to zero after a short LC
transient following the trip of CB1D.
Fig. 6(d) shows AC currents of all the phases of port 1 after
phase reconfiguration. We can see the 3 remaining phases are
balanced after phase reconfiguration.
Fig. 6(e) shows the capacitor voltage during phase
reconfiguration. The capacitor voltages are balanced before and
after phase reconfiguration and temporarily unbalanced during
phase reconfiguration.
A. Tripping of a phase
Fig. 6 shows the simulation result of tripping phase D from
the four phase hub at full power. The hub is initially operating
with four phases, and at 1.0sec phase D of all the 3 ports is
tripped by corresponding circuit breaker CB1D− CB3D. In the
reconfiguration interval (1.0s to 1.1 s) the phase difference ∆φ
is gradually increased from π/2 to 2π/3.
Fig. 6(a) shows the DC power of each port. The DC power is
per unit values taking the rated power of each phase of
corresponding port as the base value. Before tripping of phase
D, each 4-phase port is absorbing/injecting 4 pu DC power
from/to the hub. Power of each port reduces to 3pu after phase
D is tripped.
Fig. 6(b) shows the instantaneous AC voltage and
instantaneous current of phase A of port 1 in steady state. The
voltage curve in Fig. 6(b) follow the shape of curve shown in
Fig. 3. The current in Fig. 6(b) is in phase with voltage, which
confirms zero reactive power at the converter.
Ck
Rkdc
CBkA
S1_k
S3_k
S5_k
S7_k
Ckd
S2_k
S4_k
S6_k
S8_k
Ckd Rkdc
Lk
Vkdc
vcA
CBkB
vcB
CBkC
CBkD
Vkdc
fo
VCO
∆φ
π/6
Flag_Trip
 
dq
0 ∆T
π/2
 
Firing
Logic A
dq
θA
pu
cdref
V
 1.0
pu
Vcqref
0
Firing
Logic B
θB
θC
Kdamp
pu
VcdA
1.0
Kp2+Ki2/s
MkdA
θD
αkC
MkD
MkC
MiA
Firing
Logic D
αkD
αiA
Kdamp
pu
VcqA
Firing
Logic C
MkqA
Kp2+Ki2/s
Kdamp
pu
VcdB
1.0
Kp2+Ki2/s
MkdB
Kdamp
MkqB
pu
VcqB
MkB
αkB
Kp2+Ki2/s
Fig. 5. Control diagram of Voltage Port(Control of Phase C/D are not shown, they are similar to Phase A/B)
6
4
Pidc (pu)
Fig. 6(f) shows the phase difference ∆φ. ∆φ is increased from
π/2 to 2π/3 in a time span of 0.1 sec.
Fig. 6(g) shows the RMS capacitor voltages vc. Capacitor
voltages of the remaining phases remain the rated values after
phase reconfiguration. The non-zero VrmsD is due to the remnant
charge on the capacitors of phase D after tripping of CB1D –
CB3D.
From Fig. 6 we can see that the hub can be reconfigured "on
the fly" by connecting/disconnecting a phase, while operation
of other phases is unaffected.
2
P1dc
P2dc
P3dc
0
-2
-4
-6
0.9
0.95
1
1.05
Time(s)
(a) DC power
1.1
1.15
1.2
v1acA, i1acA(pu)
7
2
1.5
1
0.5
0
-0.5
-1
-1.5
0.94
v1acA
i1acA
0.9405
0.941
Time(s)
0.9415
0.942
(b) voltage and current in steady state
i1acA- i1acD, i1outD(pu)
1.5
1
i1A
i1B
i1C
i1D
i1outD
0.5
0
-0.5
-1
-1.5
0.999 0.9995
1
1.0005 1.001 1.0015 1.002 1.0025
Time(s)
(c) Currents during phase reconfiguration
i1acA- i1acD (pu)
1.5
i1A
1
0.5
i1B
0
-0.5
i1C
-1
i1D
-1.5
1.099
1.0995
1.1
Time(s)
1.1005
1.101
(d) Currents in steady state after phase reconfiguration
600
vcA
200
vcB
0
-200
vcC
-400
vcD
-600
0.999 0.9995
1
1.0005 1.001 1.0015 1.002 1.0025
Time(s)
Vidc(kV)
(e) Capacitor Voltage during phase reconfiguration
130
Δφ(deg)
120
110
100
350
300
250
200
150
100
50
0
-50
90
V2dc
V3dc
1.4
0.9
0.95
1
1.05
Time(s)
1.1
1.15
1.2
VcrmsA
VcrmsB
VcrmsC
VcrmsD
200
100
0
0.9
0.95
1
1.05
Time(s)
1.1
1.15
(g) RMS capacitor voltages
Fig. 6. Response to tripping phase D on all ports
1.6
1.7
1.8
Time(s)
(a) pole to pole DC voltage
VcA, VcdA,VcqA(pu)
400
300
1.5
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
(f) Phase angle difference between each phase
1.2
V1dc
V2dc
V3dc
V1dc
80
VcrmsA-VcrmsD (kV)
vcA- vcD(kV)
400
B. Response to permanent DC fault
Fig. 7 shows system response to permanent DC fault at port 3.
A permanent DC fault happens at the DC transmission cable at
1.5sec and all four phase totally collapse at the affected port..
AC circuit associated with port 3 is tripped by circuit breakers
CB3A− CB3D at 1.6 sec.
Fig. 7(a) shows the pole to ground DC voltage of each port.
We can see the DC fault only brings down the DC voltage at the
faulted DC line, DC voltage at the un-faulted DC line remain
unchanged.
Fig. 7(b) shows the dq component of capacitor voltages of
phase A. We can see from Fig. 7(a) that the DC fault does not
cause large disturbance to capacitor voltage. An LCL circuit
has a property that collapse of AC voltage at one port will not
significantly affect circuit operation, as studied in[14].
Capacitor voltage is maintained to rated value after the faulted
port is tripped from the hub. Fig. 7(b) also shows a none zero
component of Vcq shows up after tripping port 3.
Fig. 7(c) shows the RMS AC current of phase A of each port.
We can see the AC current of each port is within 1.3 during the
transients. RMS Current of other phases are not shown though
they are almost identical to phase A.
Fig. 7(d) shows DC power of the three ports. Before fault,
P1dc-P3dc are all around 4 pu. P3dc reduces to zero following the
DC fault. P1dc reduces from 4 pu to 3.32pu due to the droop
control. And P2dc is 4.24(about 6% over rated) as only port 2 is
used to absorb the power injected by port 1.
Fig. 7(d) also shows that power exchange between port 1 and
port 2 are still remained even during the DC fault at port 3
during 1.5-1.6s. This is a significant feature that could not be
achieved in a DC grid based on DC CB.
VcA,VcdA
1.9
2
VcA
VcdA
VcqA
VcqA
1.4
1.5
1.6
1.7
1.8
Time(s)
(b) Capacitor voltage of phase A
1.9
2
IirmsA(pu)
8
[5]
1.4
1.2
1
0.8
0.6
0.4
0.2
0
I2rmsA
[6]
I1rmsA
I1rmsA
[7]
I2rmsA
I3rmsA
I3rmsA
[8]
1.4
1.5
1.6
1.7
1.8
Time(s)
(c) RMS AC current of phase A
1.9
2
6
[9]
P1dc=3.32
Pidc(pu)
4
2
[10]
P3dc
0
-2
P2dc=-4.24
[11]
-4
-6
1.4
1.5
1.6
1.7
1.8
1.9
Time(s)
(d) DC power
Fig. 7. Response to permannet DC fault at port 3
2
VI. CONCLUSION
Multiphase multiport LCL DC hub concept is proposed. The
hub enables power exchange between numerous DC
transmission lines with different voltage ratings. The hub is of
high reliability due to its multiphase configuration. On fault at a
single phase of the converter bridge, instead of tripping the
whole port from the hub, only the faulted phase associated with
all the port is tripped from the hub and the remaining phases are
reconfigured to a balanced system with reduced number of
phases. At a DC permanent fault, the faulted port will be
tripped from the hub. The remaining healthy ports can still
operate at full power during and after the DC fault. Simulation
of a 3-port demonstration case verified the high reliability and
balanced, stable operation of the hub.
The introducing of DC hub in a DC grid will increase the
power loss and the cost DC grid. However, given the operating
benefits that could be achieved by using DC hub, it is tempting
to use DC hub in DC grids. The power loss of LCL DC hub will
be around 1% which is acceptable compared to the power loss
of DC lines. Also, as the cost of DC cables is significant higher
than the cost of converters in a DC grid. The cost increase due
to the increase number of VSCs should also be acceptable.
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BIOGRAPHIES
Weixing Lin (S’11) obtained his Bachelor’s degree in electrical engineering in
2008 from Huazhong University of Science and Technology (HUST), Wuhan,
China, where he is pursuing a PhD degree in electrical engineering since 2008.
He is currently a research associate at the Aberdeen University. His research
interest is multiport high power LCL DC hub and DC grids.
Dragan Jovcic (SM’06, M’00, S’97) obtained a Diploma Engineer degree in
Control Engineering from the University of Belgrade, Yugoslavia in 1993 and a
Ph.D. degree in Electrical Engineering from the University of Auckland, New
Zealand in 1999. He is currently a professor with the University of Aberdeen,
Scotland where he has been since 2004. He was a visiting professor at McGill
University in 2008, also worked as a lecturer with University of Ulster, in the
period 2000-2004 and as a design Engineer in the New Zealand power industry
in the period 1999-2000. His research interests lie in the FACTS, HVDC,
integration of renewable sources and DC grids.