Download design of transistor biasing circuits

PART - B
1
Experiment No. 1
PN junction diode characteristics (i) Forward bias (ii) Reverse bias
AIM: (1) To plot the V-I characteristics of given Germanium & silicon diodes.
(2) To find the cut in voltage, static forward and reverse resistance, dynamic
forward and reverse resistance.
COMPONENTS & EQUIPMENT REQUIRED:
1.
2.
3.
4.
5.
6.
D.C. Regulated Power Supply (0-30)V
D.C. Voltmeter (0-20) V
D.C. Ammeter (0-20) mA
D.C. Ammeter 0-200 μA
Diodes: IN4007
Resistor: 1kΩ
THEORY:
PN junction diode is a two terminal device consisting o a PN junction formed
either in Ge or Si crystal. The circuit symbol is shown in fig.1
A PN junction diode has the most important characteristics of conducting current
in one direction it offers very low resistance when forward biased. It behaves almost as
an insulator when reverse biased, hence diodes are mostly used as Rectifier is
converting alternating current in no direct current.
V-I CHARACTERISTICS:
The V-I characteristics of a diode can be described by the analytical equation
called ‘Boltzmann’ diode equation given as
I = Io(ev/ηVt – 1)
Where Io = diode reverse saturation current. It is of the order of nano amperes (nA) for
Si and Micro amperes (μA) for Ge
V = Voltage across junction
+Ve for forward bias
-Ve for reverse bias
η = 1 for Germanium (Ge)
η = 2 for Silicon (Si)
2
VT = Volt equivalent of temperature
= KT =
e
T
where ‘K’ is the Boltzmann constant
11,600
At room temperature T is 273+20 = 293ºK
VT =
293
= 25mV
11,600
Diodes are mostly used as rectifiers. They convert ac current in to dc current for dc
power supplies of electronic circuits.
CIRCUIT DIAGRAM:
V
V
(i) Forward bias circuit
(ii) Reverse bias circuit
PROCEDURE:
Forward bias
1. Connect the circuit as shown in Fig(i)
2. Vary the input supply voltage from zero volts, such that V F is varied in steps of
0.5V and note down the corresponding ammeter reading (I F) till IF attains a value
of 1mA.
Now vary the supply voltage such that IF is varied in steps of 2mA and note the
corresponding voltmeter reading. Do not exceed IF beyond 20mA.
3
Reverse bias
3. Connect the circuit as shown in Fig(ii)
4. Vary the supply voltage, such that VR is varied in steps of 2V and note the
corresponding ammeter reading IR. do not exceed VR beyond 10V.
Tabulate the reading and draw the graph showing V-I characteristics
OBSERVATIONS
(i) Forward bias
S.No.
VF(volts)
IF(mA)
(ii) Reverse bias
S.No.
VR(volts)
IR(μA)
EXPECTED GRAPH:
4
5
CALCULATIONS:
1) To find cut in voltage draw a line tangent to the curve cutting at X-axis this is the
cut in voltage.
𝑉
2) Static resistance Rdc = 𝐼 in the forward region and reverse region
3) Dynamic resistance rac=
ΔV
ΔI
RESULT:
1) Cut in voltage (Vr): Ge and Si
2) Statis forward and reverse resistance: Ge and Si
3) Dynamic forward and reverse resistance: Ge and Si
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA QUESTIONS:
1) Learn the semiconductor device numbering system and hence describe the
diode you have used?
2) What is a P-N diode?
3) What is doping?
4) What are trivalent and pentavalent impurities?
5) What is cut in or knee voltage? Specify typical value of cut in voltage for Ge and
Si diode?
6) What is leakage current?
7) What is the peak inverse voltage (PIV) for a diode?
8) List typical applications of P-N diode.
9) Determine the current I in the circuit shown below
10) Find the voltage ‘VA’ in the circuit shown in fig below.
6
Experiment No:2
Zener diode characteristics
AIM: (1) To plot the V-I characteristics of a Zener diode.
(2) To find Zener breakdown voltage, static and dynamic forward resistance,
static and dynamic reverse resistance in the breakdown region.
COMPONENTS & EQUIPMENT:
1.
2.
3.
4.
5.
D.C. Regulated Power Supply (0-30)V
D.C. Voltmeter (0-20) V
D.C. Ammeter (0-20) mA
Zener Diode: 5.1 V – FZ6V1
Resistor 1kΩ
THEORY:
Zener diode is a reverse biased heavily doped silicon (or Germanium) PN
junction diode which is operated in the breakdown region where current is limited by
both external resistance and power dissipation of the diode. Silicon is preferred to
germanium because of its higher temperature and current capability.
The breakdown occurs due to two effects
1) Zener
2) Avalanche
At reverse voltages less than 6V Zener effect predominates whereas above 6V
avalanche effect is predominant.
V-I characteristics:
The forward characteristics is a simply that of an ordinary forward biased PN
junction diode. The important points on the reverse characteristics are:
VZ = zener break down voltage
IZ(min) = Minimum current to obtain break down
IZ(max) = Maximum zener current limited by maximum power dissipation.
Since its reverse characteristics is not exactly vertical the diode posses some resistance
called “Zener dynamic resistance’ given by ΔVZ
ΔIZ
The circuit symbol of a zener diode is shown in fig. 1.
7
The most common application of a zener diode is in the voltage stabilizer or
regulator circuits.
CIRCUIT DIAGRAM:
(i) Forward bias circuit
(ii) Reverse bias circuit
PROCEDURE:
Forward bias
1. Connect the circuit as shown in Fig (i)
2. Vary the input supply voltage from zero volts, such that V F is varied in steps of
0.05V and note down the corresponding ammeter reading (I F) till IF attains a
value of 1mA.
Now vary the supply voltage such that IF is varied in steps of 2mA and note the
corresponding voltmeter reading. Do not exceed IF beyond 20mA.
Reverse bias
1. Connect the circuit as shown in Fig (ii)
2. Vary the supply voltage, such that VR is varied in steps of 1V and note the
corresponding ammeter reading IR till the Zener voltage is reached. Note the
voltage by changing the current in steps of 2 mA. Do not exceed I R beyond 20
mA.
Tabulate the readings and draw the graph showing V-I characteristics
8
EXPECTED GRAPH:
IF (mA)
Forward
Characteristics
Vr
VR (V)
VF (V)
Break down
voltage
Reverse
Characteristics
IR (mA)
ZENER DIODE AS VOLTAGE REGULATOR
% Voltage
Regulation
0
RL
9
OBSERVATIONS:
(i) Forward bias
S.No.
VF(volts)
IF(mA)
(ii) Reverse bias
S.No.
VR(volts)
IR(μA)
CALCULATIONS:
1) Find the Zener voltage in reverse region.
V
2) Static resistance Rdc = I in the forward region.
3) Dynamic resistance rac =
∆V
∆I
RESULT:
1) Zener breakdown voltage (VZ):
2) Static forward and reverse resistances:
3) Dynamic forward and reverse resistances.
10
LOAD REGULATION CIRCUIT
1KΩ
15V
dc
+
A
-
(0-20)mA
FZ6V1
DRB
RL = 1KΩ
(0-20)V
V
PROCEDURE:
1) Connect the circuit as shown in the figure.
2) Fix the input voltage at 30V or 15V
3) Vary the load resistance RL from 100Ω to 1kΩ in steps of 100Ω & 1kΩ-100kΩ in
steps of 1kΩ & note down the values of voltage & current in tabular form.
4) Determine the percentage regulation using the formula.
5) Percentage voltage regulation = VNL - VL x 100%
VL
TABULAR COLUMN:
Load
Resistance Load Voltage (volts)
(RL (ohm)
Load current (mA)
Percentage
Regulation
100 Ω
200 Ω
.
.
.
1kΩ
2kΩ
.
.
.
11
10kΩ
20kΩ
.
.
.
100kΩ
12
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA QUESTIONS:
1. What is a Zener diode? How does it differ from an ordinary diode?
2. Distinguish between Zener and Avalanche breakdown mechanism?
3. Discuss the application of Zener diode?
4. Define breakdown Voltage?
5. Draw the symbol of Zener diode?
6. What are the other names of Zener diode?
7. Draw the equivalent circuit of a Zener diode.
8. Draw the equivalent circuit of a Ideal Zener diode.
9. What is nominal Zener diode?
10. For the circuit shown below find.
a) Output voltage
b) Voltage drop across series resistance
c) Current through Zener diode
13
Experiment No. 3
TRANSISTOR CB CHARACTERISTICS
(Input and Output)
AIM: To study the static characteristics of a transistor in Common-Base configuration.
EQUIPMENTS AND COMPONENTS REQUIRED:
0-30V D.C Dual Regulated Power Supply 0-20mA D.C. Ammeter, Transistor BC107,
Resistor 4.7kΩ, 0-20V D.C voltmeter or a Digital Multimeter.
CIRCUIT DIAGRAM:
BC107
0-20mA
+
E
0-20mA
+
C
470 Ω
470 Ω
-
0-30V
+ VEE
VEB
V
B
0-20V
+
+
VCB
V
+
0-30V
VCC
0-30V
-
-
THEORY:
A bipolar junction transistor has three regions namely emitter, base and collector.
It has two junctions emitter base junction which is always forward biased, base collector
junction which is always reverse biased, base collector junction which is always reverse
biased transistors are of two types NPN and PNP.
When a transistor is connected with base as common terminal for both the input and
output it is called of common base configuration. The input and output it is called as
common base configuration. Te input parameters are IE and VCE and output parameters
are ‘IC’ and ‘VCB’.
PROCEDURE:
Step(1): Connect the circuit as shown in the circuit diagram above.
Step(2): Keep the collector voltage VCB constant at 0V, 3V, 6V. At each step vary VEB in
steps of 0.1V from 0-1V and notedown the emitter current IE in microamps in a
tabular form.
Step(3): Plot the volt-ampere characteristics between emitter-to-base voltage VEB on xaxis and emitter current IE on y-axis keeping collector-to-base voltage VCB
constant. This gives a set of input characteristics.
14
Step(4): Keep the emitter current constant at 1mA, 3mA, 5mA. At each step vary V CB in
steps of 1 volt from 0 to 10V and note down the collector current IC in
microamps.
Step(5): Plot the volt-ampere characteristics between collector-to-base voltage VCB on
x-axis and collector current IC on Y-axis, keeping emitter current IE constant.
This gives a set of output characteristics.
OBSERVATIONS:
For Input characteristics:
SI.No.
VRPS
VCB = 0V
VEB
(volts)
VCB = 3V
IE
(mA)
VEB
(volts)
VCB = 6V
IE
(mA)
VEB
(volts)
IE
(mA)
15
For Output characteristics:
SI.No.
VRPS
IE = 1mA
VCB
(volts)
IE = 3mA
IC
(mA)
VCB
(volts)
IE = 5mA
IC
(mA)
VCB
(volts)
IC
(mA)
16
EXPECTED GRAPH:
IE (mA)
VCB = 10V VCB = 0V
VEB (Volts)
INPUT CHARACTERISTICS
IC (mA)
IE = 6mA
IE = 5mA
IE = 4mA
IE = 3mA
IE = 1mA
VCB (Volts)
OUTPUT CHARACTERISTICS
17
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1)
2)
3)
4)
Draw I/o characteristics of CB transistor
Bringout the comparison between CB, CE & CC configuration.
What is early effect or based with modulation.
What is the i/p resistance & o/p resistance of CB transistor.
18
Experiment No. 4
Transistor CE characteristics (Input & Output)
AIM: To plot the input and output characteristics of transistor in common emitter
Configuration and find beta (β) from the output characteristics.
COMPONENTS & EQUIPMENT:
1)
2)
3)
4)
5)
6)
D.C. Regulated power supply (0-30) V.
D.C. voltmeter (0-20)V & (0-20)V.
D.C. Ammeter (0-200) mA.
D.C. Ammeter (0-200) µA.
Transitor BC107
Resistors 100kΩ, 1kΩ.
PROCEDURE:
A bipolar junction transistor has three regions namely emitter, base and collector.
It has two junctions emitter base junction which is always forward biased and base
collector junction which is always reverse biased. Transistors are of two types NPN and
PNP.
When transistor is connected with emitter as the common terminal for both input
and output, it is called as common emitter configuration. The input parameters are I B
and VBE the output parameters are IC and VCE.
INPUT CHARACTERISTICS:
1. Connect the circuit as shown in the circuit diagram.
2. Adjust the output voltage VCE to zero volts.
3. Vary the input voltage VBE in convenient steps and note the corresponding input
current IB.
4. Plot IB VS VBE for different values of VCE.
OUTPUT CHARACTERISTICS:
5. Set the input current IB to 50µA by adjusting the input power supply.
6. Vary VCE the output voltage in convenient steps and note the corresponding
output current IC.
7. Repeat step 1 and 2 for constant values of IB = 100µA & 150µA.
8. Plot IC VS VCE for different values of IB.
19
CIRCUIT DIAGRAM:
1KΩ
100KΩ
(0-200)µA
+
-
C
BC107
IC
B
E
IB
+
(0-30)v
-
+
(0-30)v
-
(0-20)V
VBE
(0-20)V
VCE
OBSERVATIONS:
Input characteristics
Output Characteristics
VCE = 0V, 0.5V, 1V
S.No.
VBE (V)
IB(µA)
IB = 50µA, 100µA & 150µA
S.No.
VBE (V)
IB(MA)
20
Expected graph:
Input Characteristics
IB (µA)
Output Characteristics
VCE=0V VCE=3V VCE=5V
IC (mA)
IB = 150µA
IB = 100µA
IB = 50µA
VBE (V)
0
VCE (V)
CALCULATIONS:
From CE output characteristics, the CE current gain (β) can be found by using the
following formula as:
∆I
β = ∆I c |VCE = constant
B
From the input and output characteristics calculate the ‘h’ parameters hie and hoe as
given below
Parameters ‘hie’ and ‘hre’ can be obtained from input characteristics.
Input impedance (hie):
Select an operation point ‘Q’ which corresponds to has current ‘IB’ and collector voltage
VCE = VC
By definition hie =
∆Vb
∆Ib
|VCE = constant
RESULT:
21
VIVA-VOCE QUESTIONS:
1. How will you determine the input and output characteristics of CE connection
experimentally?
2. Find the value of β if α = 0.99
3. What is the significance of arrow in the transistor symbol?
4. What are the specification of a transistor
5. Bringout the difference between CB, CE & CC configuration
6. Describe the transistor action.
22
Experiment No. 5
Half wave rectifier with and without filters
AIM:
1) To study the operations of half wave rectifier without filter. Measuring the dc and
rms values of output voltage hence obtain the ripple factor.
2) To find percentage of regulation of a HWR.
3) To study the operation of a half wave rectifier with shut type or C, L and π section
filters and find the ripple factor.
COMPONENTS & EQUIPMENT:
1.
2.
3.
4.
Experiment board
D.C. Ammeter (0-20)mA
Digital multimeter (DMM)
Cathode ray oscilloscope (CRO)
THEORY:
CIRCUIT DIAGRAMS:
+
+
-
-
Fig. 1. Half wave rectifier with load RL and without filter
+
+
-
-
Fig. 2. Half wave rectifier without load and filter
23
+
-
Fig. 3. Half wave rectifier with load RL and shunt capacitor filter “C”
+
+
-
-
Fig. 4. Half wave rectifier with load RL and L section filter connected
+
+
-
-
Fig. 5. Half wave rectifier with load RL and π section filter connected
24
PROCEDURE:
a) Half wave rectifier without filter:
1. Connect the circuit as shown in the Fig.1
2. Using a dual trace oscilloscope, observe the wave form at input (1-1’) and
output (2-2’) draw the waveforms.
3. Note the current Idc, voltage Vdc and Vrms at a load resistance R L=500Ω
using a DMM.
4. Repeat step 3 for RL = 1kΩ, 2kΩ, 5kΩ and 7kΩ
5. Tabulate the readings and calculate the ripple factor using formula
V
Ripple factor = Vrms
dc
6. Compare with the theoretical value of ripple factor = 1.21
To find % regulation:
7. Connect the circuit as shown on the fig.2.
8. Using a DMM measure the DC voltage at 1-1’ and note down this is the no
load voltage ‘VNL’ volts.
9. Connect the circuit as shown in fig.1. Adjust RL so that a dc current of 10mA
flows through RL observe the output waveform at output (1-1’) using a CRO.
10. Measure DC output voltage at 1-1’ using a DMM and note down. This is the
full load voltage ‘VFL’ volt. Calculate the % regulation using formula.
% regulation =
VNL −VFL
VFL
x 100%
b) Half wave rectifier with filter:
11. Connect the circuit as shown in the fig.3. adjust the RL so that a dc current of
0mA flows through RL. Observe the output waveform on a CRO at 1-1’ and
plot it with reference to half wave rectifier waveform without filter connected.
12. Measure the Vrms and Vdc voltages at the output terminals (1-1’) using a
V
DMM. Calculate the ripple factor using the formula r = Vrms . Compare with the
dc
value 1.21 ripple factor without filter.
13. Connect the circuit as shown in the Fig 4 & 5 and repeat steps 11 and 12.
OBSERVATIONS:
Ripple factor measurement:
S.No.
Load resistance RL
Idc (mA) Vac
Vdc (v)
Vrms (v), V’ac
Ripple Factor ‘r’
1kΩ
10kΩ
25
% regulation:
a) No load voltage VNL = ……………………….volts.
b) Full load voltage for a load current of Idc = 10 mA VFL = …………volts.
% regulation =
VNL − VFL
VFL
x 100%
b) half wave rectifier with filter:
S.No.
Filter Type
Vrms(v)
Vdc (v)
Ripple factor
% regulation
Draw output waveforms all filters with reference to output waveform without filter on a
graph sheet.
RESULT:
1. % Regulation of HWR =
2. Ripple factor of HWR without filter =
3. Ripple factor of HWR with capacitor filter =
4. Ripple factor of HWR with Inductor filter =
5. Ripple factor of HWR with πsection filter =
26
EXPECTED WAVEFORMS:
Input Waveform
Vac
Vm
0
π
2π
3π
4π t
HWR WITHOUT FILTER:
Vm
t
HWR WITH FILTER:
VR
Vdc
t
VR = Ripple Voltage
27
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1.
2.
3.
4.
5.
What is meant by Rectification?
What is pulsating d.c?
What is ripple factor of HWR
What is a filter?
Explain HWR with C, L, LC & CLC filter.
28
Experiment No. 6
Full wave rectifier with and without filters
AIM:
1) To study the operation of a full wave rectifier using two p-n diodes without filter
measure the dc and rms values of output voltage and hence obtain the ripple
factor.
2) To find percentage of regulation of a FWR.
3) To study the operation of a full wave rectifier with shunt type or C, L section and
π filters and find the ripple factor.
COMPONENTS & EQUIPMENT:
1.
2.
3.
4.
5.
Experiment board
D.C. Ammeter (0-20) mA
Digital multimeter (DDM)
Cathode ray oscilloscope (CRO)
Resistor 1kΩ
THEORY:
CIRCUIT DIAGRAMS:
+
(0-20)mA
-
1KΩ
RL
Fig. 1. Full wave rectifier using two diodes with load RL and without filter
29
+
+
1KΩ
RL
+
-
100μF
-
-
Fig. 2. Full wave rectifier with load and filter
PROCEDURE:
a) Full wave rectifier without filter:
1. Connect the circuit as shown in the Fig.1
2. Using a dual trace oscilloscope, observe the wave form at input (1-1’) and
output (2-2’) draw the waveforms.
3. Note the current Idc, voltage Vdc and Vrms at a load resistance R L = 500Ω
using a DMM.
4. Repeat step 3 for RL = 1kΩ, 2kΩ, 5kΩ and 7kΩ.
5. Tabulate the readings and calculate the ripple factor using formula
V
Ripple factor = Vrms
dc
6. Compare with the theoretical value of ripple factor r = 0.48
To find % regulation:
7. Connect the circuit as shown on the fig 2
8. Using a DMM measure the DC voltage at 1-1’ and note down. This is the no
load voltage ‘VNL’ volts.
9. Connect the circuit as shown in fig.1. Adjust RL so that a dc current of 10mA
flows through RL observe the output waveform at output (1-1’) using a CRO.
10. Measure DC output voltage at 1-1’ using a DMM and note down. This is the
full load voltage ‘VFL’ volt. Calculate the % regulation using formula.
% regulation =
VNL − VFL
VL
x 100%
b) Full wave rectifier with filter:
1. Connect the circuit as shown in the fig 3. Adjust the RL so that a dc current of
10 mA flows through RL. observe the output waveform on a CRO at 1-1’ and
plot it with reference to full wave rectifier waveform without filter connected.
2. Measure the Vrms and Vdc voltages at the output terminals (1-1’) suing a
V
DMM. Calculate the ripple factor using the formula r = Vrms . Compare with the
dc
value 0.48 ripple factor without filter.
3. Connect the circuit as shown in the Fig 4 & 5 and repeat steps 11 and 12.
30
OBSERVATIONS:
Ripple Factor Measurement:
S.No.
Load resistance RL
Idc (mA)
Vdc (v)
Vrms (v)
Ripple Factor ‘r’
% regulation:
a) No load voltage VNL = ……………………………volts.
b) Full load voltage for a load current of Idc = 10 mA VFL = …………………..volts
% regulation =
VNL − VFL
VL
x 100%
b) Full wave rectifier with filter:
S.No.
Filter Type
Vrms(v)
Vdc (v)
Ripple Factor ‘r’
% regulation
Draw output waveforms all filter with reference to output waveform without filter on a
graph sheet.
31
Result:
1.
2.
3.
4.
5.
% regulation of FWR =
Ripple factor of FWR without filter =
Ripple factor of FWR with capacitor filter =
Ripple factor of FWR with Inductor filter =
Ripple factor of FWR with π section filter =
EXPECTED WAVEFORMS:
Input Waveform
Vac
Vm
0
π
2π
3π
4π t
FULLWAVE RECTIFIER WITHOUT FILTER:
Vac
Vm
t
0
π
2π
3π
4π
32
FULLWAVE RECTIFIER WITH FILTER:
VR
Vdc
t
VR = Ripple Voltage
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1.
2.
3.
4.
5.
What is meant by rectification and explain full wave rectifier.
What is the ripple factor of FWR
Compare FWR with HWR
Explain the FWR with capacitor and inductor
Explain the efficiency of FWR.
33
Experiment No. 7
FET CHARACTERISTICS
AIM: To draw the static characteristics of Field Effect Transistor and to find rd and gm.
EQUIPMENT AND COMPONENTS REQUIRED:
Power Supply 0-30V dual channel, 0-20V and 0-20V voltmeter, 0-20mA Ammeter, FET
BFW10
CIRCUIT DIAGRAM:
V
V
THEORY:
PROCEDURE:
Step (1): Connect the circuit as shown in figure above.
Step (2): Drain Characteristics: Keep Gate to Source Voltage VGS = 0 vary drain-source
voltage VDS from zero in steps of 0.5V upto 2V and in steps of 1volt from 2 to
10V and notedown the corresponding drain current in tabular form.
Step (3): Repeat Step(2), keeping VGS = +2V, +4V and note down the corresponding
drain current in tabular form.
Step (4): Transfer Characteristics: Keep VDS = 4V. Vary VGS from 0 Volts in steps of 0.5
Volts till the drain current ID becomes zero.
Step (5): Repeat Step(4) for VDS = 6V, 8V, 10V and note down the corresponding drain
current in tabular form.
Step (6): Graph:
i) Draw the graph between drain-source voltage VDS on x-axis and drain
current ID on y-axis, keeping VGS constant. This gives the set of drain
characteristics.
34
ii) Draw the graph between Gate-Source voltage VGS on negative x-axis and
Drain current ID on y-axis, keeping VDS constant. This gives a set of Transfer
Characteristics.
Step (7): (i) From Drain Characteristics, find the dynamic drain characteristics given by,]
V
rd = IDS |VGS = constant
D
(ii) From Transfer Characteristics find the transfer conductance given by
I
gm = V D |VDS = constant
GS
find µ = rd * gm
OBSERVATION:
For Drain Characteristics:
SI.No.
VGS = 0V
VDS
(volts)
ID
(mA)
VGS = 1V
VDS
(volts)
VGS = 1.5V
ID
(mA)
VDS
(volts)
ID
(mA)
VGS = 2V
VDS
(volts)
ID
(mA)
35
For transfer characteristics:
SI.No.
VDS = 4V
VDS = 3V
VGS
(volts)
ID
(mA)
VGS
(volts)
VDS = 2V
ID
(mA)
VGS
(volts)
VDS = 1V
ID
(mA)
VGS
(volts)
ID
(mA)
CALCULATIONS:
JFET Parameters:
1. Drain dynamic resistance, rd =
∆vDS
∆iD
|vGS = constant
∆i
2. Mutual Conductance, gm = ∆v D |vDS = constant
GS
∆vDS
3. Amplification factor, µ = ∆v |iD = constant
GS
These parameters are related by the equation
µ = rd & gm
S.No.
Parameter
Value determined
1
rd
kΩ
2
gm
mS
3
µ
36
EXPECTED GRAPH:
ID (mA)
VGS = 0V
VGS = +1V
VGS = +2V
VDS = 3V
VDS = 4V
VGS = +3V
VGS = +4V
VGS (Volts)
Transfer Characteristics
VDS (Volts)
Drain Characteristics
37
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1.
2.
3.
4.
5.
Explain FET
Compare FET WITH Bipolar Transistor
Explain FET Biasing
Give Few FET applications
Explain various FET Connections.
38
Experiment No. 8
MEASUREMENT OF h-PARAMETERS IN CB,CE, CC CONFIGURATION
AIM: To Calculate the hybrid parameter of transistor in Common Emitter Configuration.
EQUIPMENT REQUIRED:
1.
2.
3.
4.
5.
h-parameter trainer kit
Function Generator (0.1Hz to 1MHz)
CRO (0-20MHz)
Digital Multimeter
Connecting Wires, etc.
THEORY:
The terminal behavior of a two port large network is specified by two voltages and two
currents we may select two of the four quantities as independent variables and express
the remaining two in terms of the chose independent variables.
+
V1
i1
Input port
i2
TWO PORT
NETWORK
+
V2
Output port
-
-
TYPICAL TWO PORT
If the current Il and voltage Vz are the independent parameters and if the two port is
linear, we may write
v1 = h11i1 + h12v2
i2 = h21i1 + h22v2
CIRCUIT DIAGRAM:
39
CE configuration:
PROCEDURE:
1. Connect VEE and VCC at respective given points in circuit (1)
2. Connect input signal through function generator.
3. Connect the CRO output terminals at output point and measure the parameters
hie, hfe for Common Emitter mode.
4. For circuit (2), repeat steps (1) and (2)
5. Measure the parameters hoe and hre respectively.
TABULAR COLUMN:
Parameter
CE
Vi = 1.5V
Vi = 3V
Vi = 5
hie
hre
hfe
40
hoe
1/hoe
Vb = mV; VC = Vo
1st Circuit:
V
V
V ∗R
hie = I b = Vbi = hV i
b
I
hfe = I c =
b
i
Ri
Vc /RL
VC
1
=R
L
Typical h-parameter values for n transistor in three different configurations:
Parameter
CE
CC
CB
hi
1100Ω
1100Ω
22Ω
hr
2.5 x 10-4
1
3 x 10-4
hf
50
-51
-0.98
ho
25µA/V
25µA/V
0.49µA/V
Comparison of Transistor Amplifier configurations:
(Typical values)
Quantity
CE
CC
CB
AI
-46.5
47.5
0.98
AV
-131
0.989
131
AP
6091.5
46.98
128.38
Ri
1065Ω
144kΩ
22.6Ω
Ro
45.5kΩ
80.5kΩ
1.72MΩ
PRECAUTIONS:
VIVA-VOCE QUESTIONS:
1. What is meant by h-parameters
2. Define voltage and current gains
3. Explain input impedance of an amplifier.
4. Explain output impedance of an amplifier.
5. Explain the relation between gain and impedance of an amplifier.
41
Experiment No. 9
FREQUENCY RESPONSE OF CC AMPLIFIER
AIM: To find the frequency response of a Common Collector Amplifier and bandwidth of
it.
EQUIPMENT REQUIRED:
1.
2.
3.
4.
5.
Common Collector Amplifier trainer kit
Function Generator (0.1Hz-1MHz)
CRO
Digital Multimeter
Connecting wires, etc.;
CIRCUIT DIAGRAM:
THEORY:
The common collector transistor amplifier is also termsed as emitter follower. The
voltage gain if this configuration is equal to unity, so any change in bias voltage results
in equal change of load voltage, since the load is in the emitter circuit, it looks like
emitter follows the input voltage, hence name emitter follower.
The input signal is given to base collector circuit and the output signal is taken from
emitter collector circuit C1 and C2 capacitors acts as coupling capacitors.
The output voltage is Vo = IERE = βIBRE
PROCEDURE:
1. Connections are made as per the circuit diagram
42
2. Set the input voltage to 20mV at the frequency of 1KHz using Function
Generator.
3. Vary the frequency in steps of 50Hz, 1kHz,……………..,1MHz and notedown the
corresponding voltage in CRO.
4. Calculate the voltage gain, AV and Voltage gain in dB and Tabulate it.
5. Plot the frequency response with frequency on x-axis and Gain (in dB) on y-axis
using Semilog graph sheet.
TABULAR COLUMN:
S.No.
Frequency (in Hz)
Output voltage Vo (volts)
𝑉
Gain = 𝑉𝑜
Gain in (dB)
𝑖
(AV)
43
EXPECTED GRAPH:
Gain
in dB
AVm
3 dB
AVm
Bandwidth = f2 – f1
f1
f2 Frequency
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the circuit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1.
2.
3.
4.
Why CE amplifier is also called Emitter follower.
Explain the Gain for CE amplifier
Define Amplifier
Define Bandwidth of an amplifier.
44
Experiment No. 10
FREQUENCY RESPONSE OF A CE AMPLIFIER
AIM:
1) To obtain maximum input signal without distortion.
2) To measure the amplifier gain AV.
3) To measure input and output impedances.
COMPONENTS & EQUIPMENT REQUIRED:
1.
2.
3.
4.
5.
6.
D.C. Regulated Power supply (0-30) V
Audio Signal generator
Cathode ray oscilloscope
DMM
Experimental kit with components as per the circuit diagram.
Decade resistance box.
CIRCUIT DIAGRAM:
45
PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. Switch on the power supply VCC. with the help of a DMM measure the quiescent
voltages VBE and VCE and note down. Ensure that the transistor is in active
region.
Maximum input signal without distortion
3. Switch ON the audio signal generator and connect to the input of the amplifier.
Set the frequency at 1KHz and signal at minimum.
4. Connect a CRO at the output terminals and monitor the amplifier signal by
increasing the input to the amplifier. Increase the input signal until the output of
the amplifier is just below distortion i.e. when the output signal looks clipped.
Note the amplitude of the input signal using a CRO. This is the maximum input
signal without distortion. It gives the maximum signal handling capacity of the
amplifier.
Amplifier gain measurement ‘AV’
5. Apply an input signal of 1KHZ to get an undistorted output V O. Observe the
output waveform on a CRO.
6. Using CRO measure the voltage Vin at point A and Vo at point O.
V
Evaluate AV, voltage gain using the equation AV = V O and record the gain of the
in
amplifier.
Input impedance ‘Ri’
7. Without disturbing the setting of audio signal generator, measure the drop across
10kΩ resistor i.e. measure voltages VAG and VBG. Calcuate the current Iin as
Iin =
VAG −VBG
10KΩ
Evaluate the input impedance using the relation
Rin =
VBG
Iin
Output impedance ‘Ro’
8. Measure the output voltage Vo using CRO.
9. Connect a DRB across the output terminals as load RL. Adjust the value of DRB
V
such that the output voltage is equal to 2O , this value of RL is the output
impedance Ro. Record the output impedance.
10. Find the output impedance for two values of input signal.
46
OBSERVATIONS:
TABULAR COLUMN:
S.No. Frequency Output voltage
(Hz)
Vo (volts)
AV =
𝐕𝐎
Gain in dB
𝐕𝐢
𝐕
Av(dB) = 20log10 𝐕𝐎
𝐢
1
2
3
4
5
6
7
8
9
10
11
12
13
1. Quiescent Voltages:
VBE = -----------------------volts
VCE = -----------------------volts
2. Maximum input signal without distortion = ------------------------- volts.
3. Amplifier gain AV
Input voltage Vin = ------------------------- volts
Input voltage Vo = ------------------------- volts.
V
Amplifier gain AV = V O
in
4. Input impedance:
Voltage at ‘A’ VAG = ------------------------ volts
Voltage at ‘B’ VBG = ------------------------ volts
47
Iin =
VAG −VBG
10KΩ
= -------------------------------------
Input impedance Rin =
VBG
Iin
= --------------------------ohms.
5. Output impedance:
Ro = ---------------------------- ohms
EXPECTED GRAPH:
Gain
in dB
|AV|
3 dB|AV|
Band width = f2 – f1
f1
f2
Frequency
Note: Plot the graph on semi-log paper
RESULT:
1.
2.
3.
4.
Maximum input signal without distortion = ---------------------Amplifier gain AV = ---------------------Input impedance =---------------------Output impedance =----------------------
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
48
.
VIVA QUESTIONS:
1) What is biasing? What is the need for biasing?
2) What is Q point or operating point?
3) What are the different biasing circuits?
4) Which is the most commonly used biasing circuit and why?
5) What do you understand by dc and ac load lines? How will you construct them on
the output characteristics?
6) Draw a single stage CE amplifier and draw its dc and ac equivalent circuits.
7) Compare CB, CE and CC transistor configurations
8) Draw the hybrid equivalent circuit of CE Amplifier
9) Compare CB, CE and CC Transistor Amplifier configuration in terms of Ai, Av, Ri
and Ro
10) What is the phase difference between output and input voltage in CE amplifier.
49
Experiment No. 11
FREQUENCY RESPONSE OF COMMON SOURCE FET AMPLIFIER
AIM: 1) To measure the amplifier gian AV of common source FET amplifier and hence
evaluate gm.
2) To measure output impedance Zo and evaluate rd
COMPONENTS & EQUPIMENT:
1.
2.
3.
4.
5.
6.
D.C. Regulated Power supply (0-30) V
Audio signal generator
Cathode ray oscilloscope
DMM (Digital Multimeter)
Experimental kit.
Decade resistance box.
THEORY:
FET is a three terminal device. The terminals are source, drain and gate. There
are three basic configurations of FET amplifiers depending on which of the three
terminals is grounded. They are:
(a) Common source (CS)
(b) Common drain (Source follower) (CD)
(c) Common gate (CG)
The parameters of interest of FET amplifiers are its input impedance (Z in), output
impedance (Zo) and voltage gain (AV). the current gain AI is usually infinity. Since its
input current is always zero and hence not measured.
Since the gate source junction of FET is usually operate din reverse bias, the
input impedance, Zin is greater than BJT while the output impedance Z o is comparable
with that of a BJT.
The common source connection is the most widely used arrangement. This is
FET equivalent of common emitter transistor amplifier in BJT. The source terminal is
common to both the input and output. As in the case of common emitter configuration,
common source configuration also introduces a phase shift of 180º.
This configuration has high voltage gain, high input impedance and moderate
output impedance.
50
COMPARISON OF THE THREE CONFIGURATIONS
Quantity
CS
CD
CG
1
Input resistance Zi
RG
RG
RS ||
gm
Output resistance Ro
RD
RS || 1/gm
RD
gmRs
Voltage gain AV
- gm RD
1+gmRs
gm RD
In phase
Phase relationship output 180º out of phase
and input
In phase
In the three amplifier configurations,
RS is the resistance connected between source and ground.
RG is the resistance connected between gate and ground.
RD is the resistance connected between drain and the power supply V DD.
‘gm’ is the transconductance of the JFET used
51
CIRCUIT DIAGRAM:
52
PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. Switch on the power supply VCC. with the help of a DMM measure the quiescent
voltages VGSQ and IDQ and note down.
Amplifier gain measurement ‘AV’
3. Apply an input signal Vin of frequency 1 KHZ to get an undistorted output V O.
observe the output waveform on a CRO.
4. Using DMM / CRO measure the voltage Vin at point A and Vo at point O. Evaluate
Av, voltage gain using the equation
V
Av = V O
in
and record the gain of the amplifier.
5. From the above measurement, evaluate the gm, transconductance of the
amplifier as:
AV = gmRD, where RD = 2KΩ.
Output impedance ‘Zo’
6. Without disturbing the setup measure the output voltage V O. connect a DRB at
the output terminals as load RL. Adjust the values of DRB such that the output
V
voltage is equal to 2O . This value of RL is the output impedance Zo. record the
output impedance.
7. The drain resistance rd is evaluate from the equation
1
1
1
=
+
i.e., Zo = RD || rd
Z
R
r
o
o
d
Evaluate ‘gm’ again using the equation
AV = gmZo
OBSERVATIONS:
TABULAR COLUMN:
S.No. Frequency (in Hz)
Vo (volts)
Voltage gain =
VBG
Iin
Voltagegain in dB, AV =
20log10(Vo/Vi)
(Av)
53
EXPECTED GRAPH:
Gain
in dB
|AV|max
3dB|AV|max
Bandwidth = f2 – f1
fl
fh
Frequency
1. Quiescent Voltages:
VGSQ = ----------------------------- volts
ID = --------------------------------mA
2. Amplifier gain AV:
Input voltage Vin at point A = ----------------------------volts
Output voltage Vo at point O = -------------------------- volts.
V
Amplifier gain AV = V O
A
in
Gm = R V = -------------------------------, where RD = 2KΩ
D
3. Output impedance:
Ro = ---------------------------------ohms
54
RESULT:
1.
2.
3.
4.
Amplifier gain AV = ---------------------------------gm = --------------------------------------Output impedance = ----------------------------rd = --------------------------------
CONCLUSION:
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA QUESTIONS:
1) Compare the JFET and BJT amplifiers.
2) Draw the small signal ac equivalent circuit for a JFET.
3) What are the applications of JFET amplifiers?
4) What is the input impedance of a common source JFET amplifier?
5) Compare the three configurations of JFET amplifiers.
6) Compare FET and BJT amplifiers.
55
Experiment No. 12
SCR CHARACTERISTICS
AIM: To determine the V-I characteristics of SCR and find
(i)
Break Over Voltage
(ii)
Avalanche Breakdown voltage
EQUIPMENT REQUIRED:
1.
2.
3.
4.
5.
SCR characteristics trainer kit.
Milli ammeters (0-200mA)
Voltmeter (0-20V)
D.C. regulated power supply
Connecting wires, etc.
CIRCUIT DIAGRAM:
A
A
V
THEORY:
The silicon control rectifier is a 4 layer p-n-p-n device. It is made up of Silicon
because of its high temperature and power capabilities the operation of SCR is different
from d layer semiconductor diode, in SCR 2 third terminal ‘gate’ is used to control the
operations when SCR enter in the conduction region the corresponding voltage is
known as forward breakdown voltage VBRF. The reverse breakdown voltage is
equivalent to zener or avalanche region of fundamental 2 layer semiconductor diode.
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Give the triggering voltage to the Gate, the gate trigger current I GT flows into the
Gate.
3. Now apply the supply voltage VFA in forward bias, note down the corresponding
current IFA. There will be slow increment of current till break over voltage, then
voltage across SCR suddenly drops and current IFA increases abruptly. This
gives the forward characteristics.
56
4. To get the reverse characteristics, invert the supply terminals. If the reverse
voltage is gradually increased, at first the anode current remains small and at
some reverse voltage, avalanche breakdown occurs and the SCR starts
conducting heavily in the reverse direction. This maximum reverse voltage at
which SCR starts conducting heavily is known as reverse breakdown voltage.
5. Repeat the above procedure for different values of Gate trigger voltage.
6. Plot the Forward bias and Reverse bias characteristics of SCR.
TABULAR COLUMN:
S.No.
RPS
IG = 5µA
VFA
IG = 10µA
IFA
57
EXPECTED GRAPH:
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the circuit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1.
2.
3.
4.
5.
Define a rectifier
What is break over voltage
What is Avalanche Break down voltage
Explain SCR characteristics
What is meant by trigger voltage.
58
Experiment No. 13
UJT CHARACTERISTICS
AIM: To plot the V-I characteristics of given uni-junction transistor (UJT)
EQUIPMENT & COMPONENTS REQUIRED:
UJT 2N2646, Resistor 100Ω. 1KΩ, Ammeter (0-25mA), Multimeter, Dual
Regulated Power Supply unit voltmeter (0-20V) – 2 No.
CIRCUIT DIAGRAM:
A
VBB
IE
2N2646
VE
THEORY:
PROCEDURE:
1) Connect the circuit as shown in figure above.
2) Keep the interbox voltage VBB at 0 volt and vary the VEE such that the voltage VE
increase instep of 0.1 volt.
3) Note the corresponding emitter current and increase the voltage V E upto 1V and
tabulate the values.
4) Keep the inter bare voltage at 5 volts and increase VEE such that VE increase in
step of 1volt. Note down the corresponding ammeter reading.
5) At a particular value of VE, voltage drops and only the current IE shoot up. Note
the value of VE & IE at which the voltage drop.
6) Vary the voltage VEE such that VE varies in steps of 0.1 volt. Note down the
corresponding ammeter readings take about 2 or 3 reading.
7) Repeat steps 4, 5, & 6 for two different volts of VBB and tabulate the value.
8) Draw the graph between the values VE & IE
59
OBSERVATIONS:
S.No.
VBB = 0V
VE
IE (mA)
VBB = 5V
VE
IE (mA)
EXPECTED GRAPH:
INPUT CHARACTERISTICS OF UJT
60
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1. Define UJT
2. Explain UJT characteristics
3. Give few applications of UJT
4. Define Gain
5. Explain Ammeter and Voltmeter
61
Experiment No. 14
RC PHASE SHIFT OSCILLATOR
AIM:
To study the RC phase shift oscillator.
COMPONENTS & EQUIPMENT:
1.
2.
3.
4.
D.C. Regulated Power supply (0-30) V
RC phase shift oscillator board.
Cathode ray oscilloscope (CRO).
Connecting wires.
THEORY:
RC phase shift oscillator is used for generation of low frequency oscillations.
Because of resistive and capacitive elements good frequency stability and waveform is
obtained when compared to oscillators using LC elements.
The circuit of a RC oscillator consists of
a) An amplifier which produces a phase shift of 180º
b) A three-section RC phase shift network.
At the frequency of oscillations each RC section produces a phase shift of 60º.
Thus the RC ladder/phase shift network produces a total phase shift of 180º. Therefore
the total phase shift around the amplifier and the phase shift network becomes 360º,
thereby satisfying Barkhausen conduction for oscillations.
1
The frequency of oscillations is fo= 2𝜋𝑅𝐶√6
Amplifier gain > 29
1
Feedback factor β = 29
The minimum value required for the transistor hfe is 44.5.
RC phase shift oscillators are specially suited for generating frequencies lying in the
range from several Hz to several hundred KHz. For higher frequencies i.e. frequencies
in MHz range, it has no definite advantage over LC tuned oscillator.
Its main drawback is that three capacitors or resistors should be changed
simultaneously to change the frequency of oscillations and it is difficult to control the
amplitude of oscillations without affecting the frequency of oscillations.
62
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the Circuit as shown in the circuit diagram.
2. Connect the three capacitors of value C = 0.0022µf at pts 1-1, 2-2 & 3-3 as
shown in the Circuit diagram.
3. Switch ‘ON’ the power supply and connect the output of the R-C Phase shift
oscillator to the CRO.
4. Observe the waveform on the CRO.
5. Find the frequency of oscillations by measuring the time period of the output
waveform.
6. Compare with the theoretical value.
1
7. The theoretical value of frequency is given by f o =
2πRC√6
8. Repeat steps 1 through 6 for other sets of values for capacitors
C = 0.0033µf and 0.01µf.
63
OBSERVATIONS: R = 10KΩ
S.No.
Capacitor value in µF
1.
0.0022
2.
0.0033
3.
0.01
Theoretical
frequency
Practical frequency
Time period = T Frequency f =
Result:
C = 0.0022µF
C = 0.0033µF
C = 0.01µF
Frequency of oscillations ‘fo’ =
CONCLUSION:
VIVA QUESTIONS:
1) How many RC sections are used in a RC phase shift oscillator? Justify your
answer.
2) What is the phase shift produced by the RC phase shift network?
3) What is the phase shift produced by the amplifier?
4) What are the values of the amplifier gain ‘A’ and feedback factor ‘β’ for
oscillations?
5) The frequency of oscillations is given by -------------------------6) For sustained oscillation hfe > ---------------------------7) The minimum value for hfe of the transistor for oscillations is -----------------8) What are the advantages and drawbacks of a RC phase shift oscillator?
9) RC phase shift oscillator is a low frequency oscillator. Justify
64
Experiment No. 15
CLASS – A POWER AMPLIFIER
AIM: To design and test the Class A power amplifier and find its efficiency:
APPARATUS:
1.
2.
3.
4.
5.
Class-A power Amplifier trainer
Function generator
CRO
BNC probes and connecting wires
Multimeter
THEORY:
A class – A power Amplifier is defined as a power amplifier in which output
current flows for the full-cycle (360º) of the input signal. In other words, the transistor
remains forward biased throughout the input cycle.
This is also sometimes referred to as single ended power amplifier. The term
single ended (denoting only one Transistor) is used to distinguish it from the push pull
amplifier using two transistors.
This coupling method also prevents large dc current from flowing through the
load, which otherwise could be harmful it the load were a loud speaker, since it would
cause saturation of the magnetic circuit and impair the reproduction of the audio signal.
CIRCUIT DIAGRAM:
Cb
CE
65
PROCEDURE:
1. Switch ON Class-A power amplifier
2. Set V s (say 250 to 300 mV) at 10Hz using signal generator.
3. Connect milli ammeter to the ammeter terminals.
4. By keeping the input voltage constant, vary the frequency from 0 to 1 MHz in
regular steps.
5. Note down the corresponding output voltage from CRO.
6. Calculate the DC input power using the formula P dc = V cc lc.
7. Calculate the AC output power using Pac = Vo2 /8RL.
8. Calculate the efficiency η = Pac / Pdc
9. Plot the graph between Gain (dB) and frequency.
10. Calculate bandwidth from the graph.
11. Simulate the above class-A power amplifier using multisim software.
OBSERVATIONS:
S.No.
Frequency (Hz)
Vo (Volts)
Gain AV = Vo/Vs
Gain (dB) =
20log(AV)
fh
Frequency (Hz)
EXPECTED GRAPH:
Av (3dB)
AVm
3dB(AVm)
Bandwidth
= f2-f1
fl
66
PRECAUTIONS:
1. Check all the components and devices used in the circuit for its proper
functioniong.
2. Rig-up the circuit with ut-most care and avoid loose connectoin.s
3. Check the cirucit connection throughoutly before swithcing ON.
4. Handle the equipments carefully.
5. Operate the measuring instruments gently, as they are sensitive.
6. Switch off the supply when not in use.
VIVA-VOCE QUESTIONS:
1. Give the difference between voltage and power amplifiers
2. Define power efficiency
3. Define Class-A power amplifier
4. Give few applications of class – A power amplifier.
5. Define Bandwidth of an amplifier.
67
EXPT.NO: 16 STUDY OF MICRO PROCESSOR
AIM:
To study 8085 Micro processor.
PROCEDURE:
MICRO PROCESS UNIT:
The term micro processing unit (mpu) is similar to the form centre processing unit
(cpu) used in traditional computer we define the mpu as a device or a group of device or
a group of device (as a unit) that can communicate with periphals, provide timing
signals, direct data grows and perform computing tasks as specified by the instruction in
memory the unit will have the necessary lines for the address bus, the data bus and the
control signals and would require only a power supply a crystal to be completely
functional.
Using this description the 8085 micro processing to be almost qualify as mpu but with
the following two limitations.
 The low order address bus of the 8085 micro processor is multiplexed with the
data bus. The buses need to be demultiplexed.
 Appropriate central signal need to be generated to be generate interface memory
and i/o device that donos require such control signal.
The 8085 micro processor:
The 8085 commonly known as the 8085 is at is 8-bit general purpose micro processor
capable of addressing 64 as memory. The device has forty pins. Required a +5V single
power supply and can operate with a 3MHz single phase dork.
Address bus:
The 8085 has 16 signal liens (pin8) that are used as the address bus; however these
lines are sput input the two segment: A15- A8 and AD7 – AD0. The eight signal lines, A15A8 are unidirectional and used for the most significant bits called the high order address
of a bit address. The signal lines AD1 –AD0 are used for a dual purpose as explained in
next section.
MULTIPLEXED ADDRESS/DATA BUS:
The signal lines AD7 – AD0 are bi directional they serve a dual purpose a they are used
as the low order address but as well as the data bus. In executing an instruction, during
the lateral part of the cycle these lines are used as low order address bus. During the
lateral part of the cycle these lines are used as the data bus. However the low order
address but can be separated from these signal by using a latch.
68
Control and status signals:
This group of signal include two control signal (RD and wR) these status signal (I0/m,
Si,So) to identify the nature of the operation and the special signal (FLE) to indicate the
beginning of the operation these signal are as follows:

ALE-ADDRESS LATCH ENABLE:
This is a +ve going pulse generated every time the 8085 begins on operation it
include that the bits on AD7 - AD0 are address bit. This signal is used primarily to latch
the low order address from the multiplexed bus and generate a separate set of eight
address lines A7 – A0.

̅̅̅̅
𝐑𝐃 – READ:
This is a read control signal. This signal indicate that the data on the data bus are
to be written into the selected memory ‘or’ i/o location.

̅̅̅̅̅
𝐖𝐑 – WRITE:
This is a write control signal indicate that the selection i/o are memory device is
to read and data are available on the data bus.

Io/m:
This is a status signal used to difference between i/o and memory operation
when it is high it indicates i/o operation when it is low. It indicates a memory. This signal
̅̅̅̅ (Read) and WR
̅̅̅̅̅ (Write) is combined with RD
̅̅̅̅ (Read) and WR
̅̅̅̅̅ (Write)
is combined with RD
to generated I/o and memory control signal.
 Si and So:
This status signals, similar to Io/m and identify various operation but they are rarely
used in small systems.
POWER SUPPLY AND CLOCK FREQUENCY:
The power supply and frequency signal are as follows:
 VCS : +5v power supply
 VSS : Ground Resenence
 X1, X2 : A crystal is connected at these two point the frequency is internally
divided of 0 MHz.
 CLK (out): This signal can be used as the system clock for other devices.
69
EXTERNALLY INITIATED SIGNALS INCLUDING INTERRUPTS:
The 8085 has five interrupts signals that can be used to interrupts a program execution
one of the signals INTR is identical to the 8085. A micro processor interrupts signal
(INT), the others are enhancement to the 8085A. the micro processor acknowledge as
interrupts request by the 1NTA in addition to the interrupts three pins RESET hold and
ready – accepts the externally initially signals as input to respond to the hold request the
8085 has one sig called HLDA. The functions of these signals were previously
discussed in section the RESE is again described below and other are listed in for
reference.

̅̅̅̅̅̅̅̅̅̅̅̅
RESET IN:
When the signal on this PIN goes low, the program computes is set to 0 the
buses are tri stated and mpu is reset. This signal can be used to reset other devices.

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
RESET
OUT:
The 8085 has two signal to implements the serial transmission SID and SOD. In
series transmission data bits are sent over a signal line one bit at a time such as the
transmission over telephone lines.
THE ALU:
The arithmetic / logic unit performs the computering functions it includes the
accumulator the temporary register the arithmetic and logic circuit and five flag. The
temporary register is used to hold data during an arithmetic/logic operation the result of
the operation.
The flag are affected by the arithmetic and logic operation in ALU. In most of
these operation in ALU. In most of these operation result is stored in accumulator.
These fore the flag generated reflect data conditions in the accumulator with some
exceptions the deflection and conditions of flag are as follows:
 SIGN FLAG:
After the execution of an arithmetic or logic operation if but D7 of the result is 1. The sign
flag is set. The flag is used with signal no is given byte if D 7 is 1. The no. will be viewed
as +ve no. if the it is 0 the no will be considered +ve. In arithmetic operation with signed
no. but D7 is reserved for indicating the sign and the remaining 7bits are used to
represent the magnitude of a no. however the flag is irrelevant for the operation of
unsigned no. therefore the unsigned even if but D7 of a result is 1 and flag is set. It does
not mean the result is –ve.
70

Z-ZERO FLAG:
This flag zero is set if the ALU operation result in 0 and the flag is rest if the result
is not 0. This flag is modified in the accumulated as well as in other register.

AC-AUXILLIARY CARRY FLAG:
In an arithmetic operation, when a carry is generated by digits D 3 and passé don
a digit D4 the Ac flag is set the flag is used only internally for BCD operation and is not
available for the programmer to change the sequence of a program to with a dump
instruction.

P-PARITY FLAG:
After an arithmetic ‘OR’ logical operation if the result has an even no. of is the
flag is set if it has old no. is the flag is reset.
 CY-CARRY FLAG:
If an arithmetic operation result in a carry the carry flat is set: otherwise it is reset the
carry flag used also series as borrow flag for subtraction.
TIMING AND CONTROL UNIT:
The bit position reserved for these flag in the flag resister are as follows:
D7 D6 D5 D4 D3 D2 D1 D0
S Z C AC .p
cy
Among the five flags the A.C. flag is used internally for BCD arithmetic the instruction
set does not include any conditional jump instruction based on the B.C. flag of the
remaining four flags. The Z and cy flag are those mostly commonly used.
TIMING AND CONTROL UNIT:
This unit synchronizes all the microprocessor operation with the clock and generates
the control signals necessary for communication between the microprocessor and
peripheral the control signal are databus.
71
REGISTER ARRAY:
Two programmer register were discussed in the lost chapter. The two additional
register called temporary register w and z are included in register array these register
are used to hold & but data during the execution of some instructions. However
because they are used internally. They are not available to the programmer.
DE MULTIPLEXING THE BUS AD1 - D0:
The need for demultiplezing the bus AD7 – AD0 because easier to understood after
examining fig. the fig show that the address on high order bus (20H) remains on the bus
for three clock periods. Show that ALE goes high during T 6. When the ALE is high
during T6. When the ALE is high the latch is transparent, this meant that the output
change occurring to input data during T6 the output of latch is 6.54….
GENERATING CONTROL SIGNAL:
Fig shows the ̅̅̅̅
RD(read) as a control signal because this signal is used both for
reading memory and for reading an input device, it is necessary to generate two
different read signals one for memory and another for input. Similarly two separate write
signal must be generated.
FIG show that four different control singal are generated by combining the
signals ̅̅̅̅
RD, ̅̅̅̅̅
WR and Io/m
̅ . The signal is ANDED with ̅̅̅̅
RD& ̅̅̅̅̅
WR OR gates as shown in fig.
using 74LS32 quadraple two input or gate or shown in fig. the OR gates went gate go
̅̅̅̅̅̅̅̅̅ and MEMW
̅̅̅̅̅̅̅̅̅̅ control signal it indicate the peripheral i/o
low and generate MEMR
72
operation: Fig shows that the signals is completed using ̅̅̅̅
RD & ̅̅̅̅̅
WR signals to generate
̅̅̅̅ (I/o read) and IOW
̅̅̅̅̅ (I/o write) control signals.
IOR
H
D
GND
POWER
SUPPLY
+5V
RESET
9.5
B
To demultiplex the bus and to generate the necessary control signals, the 8085
microprocessor. The mpu can be interfaced with any memory on i/o.
73
VIVA-VOCE QUESTIONS:
1) Draw the architecture of 8085 microprocessor
2) Explain Flag Register
3) What are the addressing nodes of a 8085 microprocessor.
4) How many data lines and addressing lines are available in 8085 microprocessor.
5) What are temporary and permanent registers.
6) Explain arithmetic and logic unit in 8085 microprocessor.
74
Expt No. 17
HARTLEY OSCILLATOR USING OP AMP
AIM: To design a Hartley oscillator to produce frequency of oscillations of 30 KHz.
EQUIPMENT REQUIRED:
1. Bread Board
Containing variable power supply
Digital dc voltmeter
Frequency counter 220 KHz
2. CRO
COMPONENTS REQUIRED:
µA 741 Op Amp;
capacitor 0.1µF
Inductors 10mH
Resistors 1KΩ, 820Ω, 10 K pot.
THEORY:
A Hartley’s oscillator consists of an Op Amp and a feedback circuit or tank circuit consisting of
two inductors L1, L2 and a capacitor C, the center of the inductor is tapped. 180º phase shift is
provided by the Op Amp, remaining 180º phase shift is provided by the feedback circuit.
When the circuit is turned ON, the capacitor is charged. When this capacitor is fully charged, it
discharges through the coils L1 & L2 setting up oscillations,
From the equation of LC oscillators:
X1, X2 is positive and X3 is negative.
75
The frequency of oscillation is formed from the condition
X1 + X2 + X3 = 0
i.e.
1
jwL1 + jwL2 + 𝑗𝑤𝐶 = 0
3
1
jw(L1 + L2) = - 𝑗𝑤𝐶
3
W2 = 𝑐
1
3 (𝐿1 +𝐿2 )
f=
;
1
2𝜋√𝐶(𝐿1 +𝐿2 )
CIRCUIT DIAGRAM:
Hartley’s Oscillator circuit
PROCEDURE:
1. With the given values of frequency f = 30 KHz and L1 = L2 = 10mH, find the value of the
capacitor C from the frequency of oscillations formula.
f=
1
2𝜋√𝐶(𝐿1 +𝐿2 )
2. After calculating value of the capacitor C, insert the capacitor and assemble the circuit as
shown in above fig.
3. Observe the output waveform from the CRO and note the value of Tpractical
76
4. fpractical = T
1
Practical
5. Compare & verify the values of fpractical with 30KHz (f theoretical)
WAVEFORMS:
OBSERVATIONS:
C = 0.1µf
f theoretical = 30KHz
f practical = 28KHz
Results:
verify f practical = f theoretical
77
Expt No. 18
COLPITTS OSCILLATOR USING OP AMP
AIM: To design a Colpitts oscillator to produce frequency of oscillations of 30 KHz.
EQUIPMENT REQUIRED:
1. Bread Board
Containing variable power supply
Digital dc voltmeter
Frequency counter 220 KHz
2. CRO
COMPONENTS REQUIRED:
µA 741 Op Amp;
capacitor 0.1µF
Inductors
Resistors 1MΩ, 10 K pot.
THEORY:
Colpitts oscillator consists of an Op Amp and a feedback circuit or tank circuit consisting of two
capacitors C1, C2 and a inductor L. 180° phase shift is provided by the Op Amp, remaining 180°
phase shift is provided by the feedback network.
When the circuit is turned ON, the capacitors C1 and C2 are charged. The capacitors discharge
through L, setting up oscillations of frequency determined by the equation 1. The output voltage
of the amplifier appears across C2 and feedback voltage is developed across C1. These voltage
are out of phase to each other.
From the eq of LC oscillators:
X1, X2 are negative and X3 is positive for Colpitts oscillator
The frequency of oscillation is formed from the condition
78
X1 + X2 + X3 = 0
1
𝑗𝑤𝐶1
---------------(1)
1
+ 𝑗𝑤𝐶 + jwL3 = 0
2
jwL3 =
1
𝑗𝑤
𝐶1 + 𝐶2
(
𝐶1 𝐶2
)
W2 =
=
1
𝐿3
(
𝐶1 + 𝐶2
𝐶1 𝐶2
)=
1
𝐶 +𝐶
𝐿3 ( 1 2 )
𝐶1 𝐶2
f=
∴W=
1
2𝜋√𝐿.𝐶𝑇 )
1
𝐶 +𝐶
√𝐿3 ( 𝐶1 𝐶 2 )
1 2
𝐶1 𝐶2
Where CT = 𝐶
1 + 𝐶2
CIRCUIT DIAGRAM:
Colpitts Oscillator Circuit
79
PROCEDURE:
1. With the given values of frequency f = 30 KHz and C1 = C2 = 0.1 µF, find the value of
the inductor L from the formula of frequency of oscillations.
1
f = 2𝜋√𝐿𝐶
𝑇
2. After calculating L, insert L & C1, C2 in the tank circuit and assemble the circuit as
shown in above figure.
3. From the CRO, observe the sine wave form and form it calculate Tpractical
4. fpractical = T
1
Practical
5. Compare & verify the values of fpractical with 30KHz (f practical).
WAVEFORMS:
OBSERVATIONS:
L = 10mH
f theoretical = 30KHz
f practical = 28KHz
RESULTS:
verify f practical = f theoretical
80
Expt No. 19
JFET COMMON DRAIN AMPLIFIER
AIM:
1. To obtain experimentally the voltage gain of the amplifier.
2. To obtain frequency response characteristics of the FET amplifier and to determine its
Band width.
EQUIPMENT REQUIRED:
1. Trainer module containing:
Signal generator
Bread board
DC power supply 12V
Frequency counter 220 KHz
2. C.R.O
COMPONENTS REQUIRED:
1. N channel FET BFW 11
2. Capacitors 10µf/25V
3. Resistors 8.2K, 6.8K, 1MΩ
RATINGS:
BFW 10 n-channel JFET
IDS = 20mA at VDS = 15 and VGS = 0V
ID = 20mA; Ptot = 300mW
Tj = 200d.c.
THEORY:
When drain is common to the source and gate and the output is taken from the source,
then it is called as source follower or common drain amplifier. The voltage gain is unity means
output at the source follows the input at the gate, hence the name source follower.
81
Common drain amplifier has high input impedance and near-unity voltage gain. Hence it is used
as buffer amplifier. Source follower is same as emitter follower of a transistor.
The output voltage is given by Vo = ID.RS But ID = gm VGS
∴Vo = gm VGS.RS --------------(1)
Where gm = Transconductance from small signal model of FET.
The signal to be amplified is applied between gate and source terminals. During the positive half
cycle of the input signal, reverse bias of VGS increases, so from above equation (1), output
voltage increases. During the negative half cycle, forward bias of V GS increases, that is its
reverse bias decreases so VGS decreases, hence the output voltage Vo decreases.
Thus the input and output voltage both are in phase to each other.
CIRCUIT DIAGRAM:
FET Common Drain Amplifier
82
PROCEDURE:
1. Connect the circuit as shown in above fig.
2. Connect the signal generator to the input terminals.
3. Connect the output terminals to the oscilloscope.
4. Select 1KHz sine wave signal on the generator and set the amplifier to 200m Vp-p.
5. Measure the input and output voltages of the amplifier with CRO.
6. Change the frequency of the input signal from 100Hz to 200KHz. Keep the input signal
amplitude constant over the entire frequency range. Observe the output voltage at each
frequency.
OBSERVATIONS:
Frequency Hz
Vs = 200 mV
Output Voltage, Vo, milli Volts
Gain in dB = 20log10(Vo/Vs)
100 Hz
300 Hz
500 Hz
700 Hz
900 Hz
1 KHz
3K
5K
7K
9K
10 K
20 K
40 K
83
60 K
80 K
100 K
120 K
140 K
160 K
180 K
200K
GRAPH:
Plot the frequency response characteristics on the semi-log sheet by taking frequency on the Xaxis and gain in dB on the Y-axis. Calculate Bandwidth from the graph.
Band Width = fH-100Hz
RESULT:
1. Maximum gain of the amplifier =
dB
2. Bandwidth of the amplifier =
Hz
84
Expt No. 17
DESIGN OF TRANSISTOR BIASING CIRCUITS
AIM:
1. To design a self bias circuit with the following given data VCC = 12V; Operating point
(5V, 2mA), RC = 2.2KΩ; stability factor S = 8.
2. To design the fixed bias circuit with the following given data VCC = 12V; IC = 10mA and
VCE = 1V.
EQUIPMENT REQUIRED:
Semiconductor trainer module containing:
Bread board
0-15V power supplies – 2Nos.
AC power supply 12- 0 – 12V
Digital voltmeter 0-20V DC
Digital ammeter 0-200µA/mA DC
COMPONENTS REQUIRED:
Transistor BC 107
Resistors
RATINGS OF BC 107 TRANSISTOR:
IC (max) = 2mA
VCEO = 45V
Ptot = 300mW
Tj = 175 dc
NPN transistor
THEORY:
A transistor must be dc biased in order to operate it as an amplifier. Proper dc biasing will make
the amplifier to reproduce the input signal. Achieving faithful amplification means bringing the
transistor into active region but not cutoff or saturation. Making the transistor come into active
85
region means fixing values of IC, IB with desired VCE & VBE. This fixing of voltage and current
defines a point called as dc operating point. The operating point should always be stable and
should not vary with β, ICO and various transistors. Stability factor is the measure of bias stability
of the transistor. Higher the stability factor, it indicates poor stability, lower value indicates good
stability.
Stability factor S =
1+β
dI
1−β B
dIC
Different biasing circuits are designed to ensure the stability of the operating point. The function
of these biasing circuits is to hold the operating point stable. The stability factor of fixed bias
circuit is given by S = 1 + β. As the value of beta is high for a transistor, so stability factor is
high, hence it is not a good biasing circuit. The most popular biasing circuit is the self bias circuit
with stability factor given as
R
(1+β)(1+ th )
S=
RE
R
(1+β+ th )
RE
Stability factor of self bias circuit is less, hence it is a good biasing circuit.
86
CIRCUIT DIAGRAM:
PROCEDURE:
a) For Self Bias Circuit:
1) Apply KVL to the output loop of fig (13.2)
i.e. VCC = ICRC + VCE + ICRE – (1)
on Substituting values of VCC, IC, RC & VCE in above eq – (1)
87
Then RE = 1.3KΩ
R
(1+β)(1+ th )
2) The formula of stability factor S =
RE
Rth
(1+β+
)
RE
- (2)
Take the multimeter, put it in hfe range, insert the transistor and calculate hfe = β.
Substitute β, RE and given S in Eq (2)
then Rth = 9.3 KΩ
3) Apply KVL to input loop of fig. 13.3
(IE = IB + IC, IB = IC/β)
Vth = IBRth + VBE + (IB + IC)RE
Then IB = 𝑅
𝑉𝑡ℎ − 𝑉𝐵𝐸
𝑡ℎ +(1+𝛽)𝑅𝐸
- (3)
In eq(3) substitute IB, VBE, Rth, β & RE
Then Vth = 3.36V
4) From the formulas Vth = (𝑅
𝑅2
1 +𝑅2
𝑅 𝑅
) VCC ; Rth = 𝑅 1+𝑅2
1
2
Calculate R1 & R2 after substituting Vth, Rth & VCC.
Then R1 = 33KΩ; R2 = 12KΩ
5) Now insert R1, R2, RE valued resistors in fig. 13.2
6) Practically find the value of stability factor S.
b) For Fixed Bias Circuit:
1. Apply KVL to the output loop of fig. 13.1
i.e. VCC = ICRC + VCE
- (1)
Substitute the values of VCC, VCE & IC in above equation (1)
Then RC = 1.2KΩ
2. Apply KVL to the input loop of fig. 13.1
VCC = IBRB + VBE
𝐼
∴VCC = ( 𝐶 ).RB + VBE
𝛽
- (2)
Substitute values of VCC, β, IC & VBE above equation (2)
then RB = 330KΩ
3. Insert the values of RB and RC in fig.1.
4. Practically find the value of the stability factor S.
88
OBSERVATIONS:
a) For Self Bias Circuit:
VCE
VBE
Drop across 33K, V33K
Drop across 12K, V12K
Drop across 2.2K, V2.2K
Drop across 1.3K, V1.3K
Calculations:
Emitter Current IE
Current I2
Current I1
∴ Base Current IB = I1 – I2
Collector current IC = IE – IB
Current gain β = IC / IB
𝑅 𝑅
Thevenin’s Resistance Rth =𝑅 1+𝑅2
1
Stability factor S =
2
R
(1+β)(1+ th )
RE
Rth
(1+β+
)
RE
b) For Fixed Bias Circuit:
VCE = 0.36V
VBE = 0.69V
Voltage across 330K, V330K =
Voltage across 1.2K, V1.2K =
Calculations:
Base Current IB = V330K / 330K
Collector Current IC = V1.2K / 1.2K
Current gain β = IC / IB
Stability factor S = 1 + β
Result:
Stability factor for Fixed Bias Circuit =
Stability factor for Self Bias Circuit =
89
Expt No. 18
TRANSISTOR BIASING CIRCUITS
AIM:
To determine the stability factors for the following biasing circuits:
a) Fixed bias and b) Self bias circuits.
EQUIPMENT REQUIRED:
Semiconductor trainer module containing:
Bread Board
0-15V power supplies – 2 Nos.
AC power supply 12-0-12V
Digital voltmeter 0-20V DC
Digital ammeter 0-200 µA/mA DC
COMPONENTS REQUIRED:
BC107 Transistor
Resistors
THEORY:
A transistor must be dc biased in order to operate it as an amplifier. Proper dc biasing will make
the amplifier to reproduce the input signal. Achieving faithful amplification means bringing the
transistor into active region but not cutoff or saturation. Making the transistor come into active
region means fixing values of IC, IB with desired VCE & VBE. This fixing of voltage and current
defines a point called as dc operating point. The operating point should always be stable and
should not vary with β, ICO and various transistors. Stability factor is the measure of bias stability
of the transistor. Higher the stability factor, it indicates poor stability, lower value indicates good
stability.
Stability factor S =
1+β
dI
1−β B
dIC
90
Different biasing circuits are designed to ensure the stability of the operating point. The function
of these biasing circuits is to hold the operating point stable. The stability factor of fixed bias
circuit is given by S = 1 + β. As the value of beta is high for a transistor, so stability factor is
high, hence it is not a good biasing circuit. The most popular biasing circuit is the self bias circuit
with stability factor given as
R
(1+β)(1+ th )
S=
RE
R
(1+β+ th )
RE
Stability factor of self bias circuit is less, hence it is a good biasing circuit.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect circuit diagrams as shown in the figure 12.1 and 12.2.
2. Using DC voltmeter, measure voltages across all the resistors and at the junctions of the
transistor.
3. Proceed to determine the stability factor using the steps given below.
91
OBSERVATION:
1. For fixed Bias circuit:
VCE ; VBE
Voltage across 330K; Voltage across 1K
Calculations:
Base current IB = V330K / 330K
Collector current IC = V1K / IK
Current gain β = IC / IB
Stability factor S = (1+β)
2. For Self Bias Circuit:
VCE = 5.14V ; VBE = 0.63V
Drop across 2.2K = 4.68V; Drop across 1K
Drop across 10K = 2.78V; Drop across 33K
CALCULATIONS:
Emitter current IE = V1K / 1K
Current I2 = V10K / 10K
Current I1 = V33K / 33K
Base Current IB = I1 – I2
Collector Current IC = IE – IB
Current gain = IC / IB
𝑅 𝑅
The venin resistance at the base Rth =𝑅 1+𝑅2
1
Stability factor S =
2
R
(1+β)(1+ th )
RE
Rth
(1+β+
)
RE
92
RESULT:
Stability factor for Fixed bias circuit =
Stability factor for Self bias circuit =
93