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Design of Voltage Regulator Module
for
Testing of Magnetic Components
Sean Kelly
B.E. Electronic Engineering Project Report
EE413
April 2005
ii
I hereby declare that this thesis is my original work except where stated
Signature:____________________________________ Date:__________________
iii
Abstract
The aim of this project is to design, build and test a voltage regulator module circuit (VRM)
that can be used to compare the performance of different magnetic component designs. The
VRM will be used to convert the input voltage (typically 12V) to a lower level which will
supply a microprocessor load e.g. the Intel Pentium.
The work will include review of VRM circuit topologies for VRM 10.1 specification.
Circuit design will be performed for available controller IC. Simulation and analysis of the
circuit in SPICE and characterisation under transient conditions, a circuit will be designed for
simulating a transient load change in SPICE.
Finally all required components will be ordered and the circuit will be built and can be used
for testing of inductors.
iv
Acknowledgements
I would like to thank my supervisor Dr. Maeve Duffy for the time and effort she put into helping
me throughout the year.
I would like to thank my family and friends for all their support throughout my years in college.
I would also like to thank the lab technicians at Nuns Island, Myles, Martin and Aodh for all their
help.
v
Table of Contents
Abstract ........................................................................................................................................... iii
Acknowledgements ......................................................................................................................... iv
Table of Contents ............................................................................................................................. v
List of Figures ................................................................................................................................ vii
Chapter 1 Project Outline................................................................................................................ 1
1.0 Project Outline ........................................................................................................................ 1
1.1 Background ............................................................................................................................ 1
1.2 Report Outline ........................................................................................................................ 4
Chapter 2 The Buck Converter ....................................................................................................... 5
2.0 Description of Buck Converter ............................................................................................... 5
2.1 Operation of Buck Converter ................................................................................................. 7
2.1.1 Continuous Conduction Mode ......................................................................................... 7
2.1.2 Discontinuous Conduction Mode .................................................................................. 10
2.2 Synchronous Buck Converter ............................................................................................... 11
2.3 Multiphase Topologies ......................................................................................................... 12
2.4 Pulse Width Modulation (PWM) Control ............................................................................ 14
Chapter 3 Intel VRM 10.1 Specification ...................................................................................... 16
3.0 Background .......................................................................................................................... 16
3.1 Features ................................................................................................................................ 17
Chapter 4 Component Selection ................................................................................................... 20
4.0 Output Decoupling ............................................................................................................... 20
4.0.1 Decoupling guidelines for Intel Xeon Processor with 800 MHz bus. ........................... 20
4.1 Output Inductance ................................................................................................................ 21
4.2 Power Switch ........................................................................................................................ 21
4.2.1 Selection Parameters ..................................................................................................... 23
4.2.2 Synchronous MOSFET ................................................................................................. 24
4.2.3 Main MOSFET .............................................................................................................. 24
4.2.4 Heat Sinks...................................................................................................................... 25
Chapter 5 Analog Devices ADP3188 & ADP3418 ...................................................................... 27
5.0 ADP3188 .............................................................................................................................. 28
5.1 ADP3418 .............................................................................................................................. 29
5.2 Initial Design Spec ............................................................................................................... 30
5.3 Design Procedure ................................................................................................................. 30
vi
Chapter 6 Computer Simulation ................................................................................................... 41
6.0 Pspice ................................................................................................................................... 41
6.1 Modifying Circuit ................................................................................................................ 44
6.2 Transient Analysis ............................................................................................................... 46
Chapter 7 Hardware Implementation ........................................................................................... 48
7.0 Switching Circuit ................................................................................................................. 48
7.1 Output Filter ......................................................................................................................... 50
7.2 Control Circuit ..................................................................................................................... 51
Chapter 8 Conclusions.................................................................................................................. 52
References ...................................................................................................................................... 53
vii
List of Figures
Figure 1.1 Total number of Transistors in Microprocessors has Increased Exponentially .............. 2
Figure 2.1 Buck Converter ............................................................................................................... 5
Figure 2.2 State 1 Equivalent Circuit ............................................................................................... 7
Figure 2.3 State 2 Equivalent Circuit ............................................................................................... 8
Figure 2.4 Buck Waveforms............................................................................................................. 9
Figure 2.5 Boundary Between Continuous and Discontinuous Modes .......................................... 10
Figure 2.6 Discontinuous Mode ..................................................................................................... 10
Figure 2.7 Synchronous Buck Converter ....................................................................................... 11
Figure 2.8 Multiphase Interleaved Buck Converter ....................................................................... 13
Figure 2.9 PWM Waveforms ......................................................................................................... 14
Figure 2.10 PWM Generation ........................................................................................................ 15
Figure 3.1 Load Current vs. Time .................................................................................................. 18
Figure 3.2 VRM 10.1 Processor Die Load Line ............................................................................. 18
Figure 4.1 MOSFET ....................................................................................................................... 22
Figure 4.2 MOSFET Equivalent Circuit ........................................................................................ 22
Figure 4.3 Temperature of Semiconductor vs. Operating Life ....................................................... 25
Figure 5.1 Functional Block Diagram of ADP3188 ....................................................................... 28
Figure 5.2 Functional Block Diagram of ADP3418 ....................................................................... 29
Figure 5.3 Circuit Diagram............................................................................................................. 40
Figure 6.1 Buck Circuit .................................................................................................................. 42
Figure 6.2 Output Voltage Waveform ............................................................................................ 43
Figure 6.3 Output Filter Waveforms .............................................................................................. 43
Figure 6.4 Modified Buck Circuit .................................................................................................. 44
Figure 6.5 New Output Voltage Waveform ................................................................................... 45
Figure 6.6 New Output Filter Waveforms ...................................................................................... 45
Figure 6.7 Load Transient Analysis Circuit ................................................................................... 46
Figure 6.8 Light to Heavy Load Transient ..................................................................................... 47
Figure 6.9 Heavy to Light Load Transient ..................................................................................... 47
Figure 7.1 Switching Circuit .......................................................................................................... 48
Figure 7.2 Output of Switching Circuit .......................................................................................... 49
Figure 7.3 Switching Circuit and Output Filter .............................................................................. 50
Figure 7.4 An Analogue Delay Circuit........................................................................................... 51
1
Chapter 1
Project Outline
1.0 Project Outline
The aim of this project is to design, build and test a voltage regulator module circuit (VRM)
that can be used to compare the performance of different magnetic component designs. The
VRM will be used to convert the input voltage (typically 12V) to a lower level which will
supply a microprocessor load e.g. the Intel Pentium.
The work will include circuit design and simulation, component modeling and design and
circuit testing.
1.1 Background
Moore’s law is the observation made in 1965 by Gordon Moore, co-founder of Intel, that the
number of transistors per square inch on integrated circuits had doubled every year since the
integrated circuit was invented. Moore predicted that this trend would continue for the
foreseeable future. In subsequent years, the pace slowed down a bit, but data density has
doubled approximately every 18 months, and this is the current definition of Moore's Law,
which Moore himself has blessed. Most experts, including Moore himself, expect Moore's
Law to hold for at least another two decades.
The number of transistors per die in microprocessors has increased steadily in the past decade,
as shown in Figure 1.1. As a result the microprocessor speeds have increased.
Sean Kelly - April 2005
Chapter 1. Project Outline
2
Year of Introduction
Transistors
4004
1971
2,250
8008
1972
2,500
8080
1974
5,000
8086
1978
29,000
286
1982
120,000
Intel386™ processor
1985
275,000
Intel486™ processor
1989
1,180,000
Intel® Pentium® processor
1993
3,100,000
Intel® Pentium® II processor
1997
7,500,000
Intel® Pentium® III processor
1999
24,000,000
Intel® Pentium® 4 processor
2000
42,000,000
Intel® Itanium® processor
2002
220,000,000
Intel® Itanium® 2 processor
2003
410,000,000
Figure 1.1 Total number of Transistors in Microprocessors has Increased Exponentially
The increases in microprocessor speeds and transistor number have resulted in an increase in
current demands and transition speeds. The supply voltages of the microprocessors have been
decreased in order to reduce power consumption.
Sean Kelly - April 2005
Chapter 1. Project Outline
3
As Intel predicted, with the continuous advances being made with semiconductor technology,
the microprocessors need to operate at significantly lower operating voltages, higher currents
and higher slew rates.
These low voltages, high currents and high slew rates are the challenges imposed on power
supplies for microprocessors.
The industry standard power supply architecture used is a dedicated DC-DC converter, the
voltage regulator module (VRM), placed close to the microprocessor to minimize the
impedance between the VRM and the microprocessor.
Voltage regulator modules are a special class of power converter circuits used to supply
microprocessor loads e.g. the Intel Pentium. The VRM converts the system bus voltage
(typically 12 V) to a lower level.
While current operating voltages are in the range of 1 - 1.5 V, it is expected that the required
operating voltages in the next few years will decrease below 1 V while increasing the drawn
current (the required current can easily exceed 100A) from the power supply in order to
reduce the power consumption while increasing the microprocessor speed.
With such low voltage levels, one of the main challenges of VRM design is to maintain the
constant output voltage under varying and transient load (current) conditions, when the
microprocessor switches from one state to the other, voltage drop spikes occur, these spikes
must be limited.
The main limit is caused by the large inductance values required to maintain ripple levels for
steady-state operation. The standard industry solution is a multi-phase buck converter, in
which the inductance is distributed between several phases that are controlled in parallel.
A buck derived voltage regulator module (VRM) will be designed to satisfy these
requirements.
Sean Kelly - April 2005
Chapter 1. Project Outline
4
1.2 Report Outline
This report consists of eight chapters. They are organized as follows.
Chapter 1 is a review of how ever improving advances in microprocessors are creating challenges
in VRM design. As transistor numbers increase, the required current will also increase while in
order to limit power consumption, the output voltage will need to decrease.
Chapter 2 looks into the buck converter topology which is the dominant topology in todays VRM
design. The operation of the buck converter is explained and it’s modes of operation are
discussed. In order to meet the growing VRM demands multi phase interleaved operation of the
buck converter is explored, these phases will be controlled by pulse width modulation (PWM).
Chapter 3 is a review of Intel’s VRM 10.1 specification. Its background is explained and some of
the requirements are discussed. The advantages of implementing a voltage regulator module are
assessed as opposed to implementing a regulator directly on the motherboard.
Chapter 4 discusses the main components to be selected in the circuit. The capacitance,
inductance and switching devices are all reviewed and selections are made.
Chapter 5 analyses two IC’s to be used in the circuit. The ADP3418 is the MOSFET driver; these
will be interfaced with MOSFETs to form the switching circuit. The ADP3188 is the controller
IC, its capabilities are reviewed, and a step-by-step design procedure is outlined.
Chapter 6 introduces Pspice, the software package used to simulate the circuits in this project.
Simulation is performed and analysis of the results is provided.
Chapter 7 outlines the building and testing of the circuit, which consists of the switching stage,
the output filter and the control circuit. At this stage the importance of component selection was
really appreciated.
Chapter 8 summarises the work and proposes ideas for future work.
Sean Kelly - April 2005
5
Chapter 2 The Buck Converter
2.0 Description of Buck Converter
Figure 2.1 Buck Converter
The most common power converter topology is the buck power converter, sometimes called a
step down power converter. Power supply designers choose the buck power converter because
the output voltage is always less than the input voltage in the same polarity and is not isolated
from the input.
The buck regulator circuit is a switching regulator, as shown in figure 2.1. It uses an inductor
and a capacitor as energy storage elements so that energy can be transferred from the input to
the output in discrete packets. The advantage of using switching regulators is that they offer
higher efficiency than linear regulators. The one disadvantage is noise or ripple; the ripple
will need to be minimized through careful component selection.
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Chapter 2. The Buck Converter
6
A requirement of the design is to have high current slew rate (up to 930 A/μs) to increase
switching speed of microprocessor from one state to the other but this causes voltage drop
spikes at the processor power supply. To achieve high current slew rate the inductor Lo should
be as small as possible. This in turn while achieving faster transient response will cause the
output voltage ripple to increase.
To reduce output voltage ripple, the switching frequency should be increased but this lowers
efficiency. This means that the selection of the switching devices will be an important issue.
The output voltage ripple can also be reduced by increasing the output capacitance; this
means a large capacitor in practical design.
The input current for a buck power converter is discontinuous due to the power switch, the
current pulses from 0 to Io every switching cycle. The output current for a buck power
converter is continuous because the output current is supplied by the output inductor/capacitor
combination; the output capacitor never supplies the entire load current for continuous
inductor current mode operation.
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Chapter 2. The Buck Converter
7
2.1 Operation of Buck Converter
2.1.1 Continuous Conduction Mode
Continuous inductor current mode is when current flows continuously in the inductor during
the full switching cycle. A buck converter operating in continuous conduction mode has two
unique switching states during each switching cycle.
This circuit operates as follows.
State 1
main MOSFET
Inductor
Vdc
Capacitor
Load
Figure 2.2 State 1 Equivalent Circuit
The first state corresponds to the case when the switch is ON. The equivalent circuit is shown
in Figure 2.2 In this state, the current through the inductor rises, and the energy stored in it
increases, during this state the inductor acquires energy.
Vi  Lo
di L
I
 Vo  Lo   Vo
dt
DT
I
When the switch is closed, the diode is in the OFF state. The diode is there so there will
always be a current source for the inductor.
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Chapter 2. The Buck Converter
8
State 2
Inductor
Diode
Capacitor
Load
Figure 2.3 State 2 Equivalent Circuit
The second state is when the switch is OFF and the diode is ON. The equivalent circuit is
shown in Figure 2.3 In this state, the inductor current free-wheels through the diode and the
inductor supplies energy to the RC network at the output. The energy in the inductor falls in
this state.
0  Vo  Lo
di L
I 
 Vo  Lo
dt
(1  D)T
II
***When the switch is open, the inductor discharges its energy. When all of its energy has
discharged, the current falls to zero and tends to reverse, but the diode blocks conduction in
the reverse direction. In the third state both the diode and the switch are OFF, in this state the
capacitor discharges its energy and the inductor is at rest with no energy stored in it.***
There cannot be a net change in flux in the inductor or it would saturate over a number of
cycles. The increase in current while the switch is on must exactly equal the decrease in
current while the switch is open.
Combining I and II:
Vi  Vo
Vo
DT 
(1  D)T
Lo
Lo
Vo = D x Vi
Average output voltage is determined by the duty cycle D of the switch and is less than the
input voltage. Shown in figure 2.4 are the waveforms for a continuous conduction mode buck
converter.
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Chapter 2. The Buck Converter
9
Figure 2.4 Buck Waveforms
Sean Kelly - April 2005
Chapter 2. The Buck Converter
10
2.1.2 Discontinuous Conduction Mode
The inductor current flows into the output capacitor and load resistor combination. The
average current flowing in the output capacitor is always zero so the buck converter load
current is the average of the inductor current. When the load current is decreased below a
critical level, i.e. half the inductor ripple current, the inductor current will be zero for a
portion of the switching cycle. In a non-synchronous buck converter, if the inductor current
attempts to fall below zero, it cannot due to the unidirectional current flow in the freewheeling
diode, and just stays at zero until the start of the next switching cycle.
This operating mode is called discontinuous conduction mode. A buck converter operating in
discontinuous conduction mode has three unique switching states during each switching cycle
as opposed to two states for continuous conduction mode. The load current condition where
the circuit is at the boundary between continuous and discontinuous modes is shown in Figure
2.5. This is where the inductor current (IL) falls to zero and the next switching cycle starts
immediately after the current reaches zero.
Figure 2.5 Boundary Between Continuous and Discontinuous Modes
If the load current is decreased further, the circuit is put into discontinuous mode. This
condition is shown in Figure 2.6
Figure 2.6 Discontinuous Mode
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Chapter 2. The Buck Converter
11
2.2 Synchronous Buck Converter
A variation on the buck converter is the synchronous buck converter. In this circuit, a switch
such as another power MOSFET replaces the rectifier diode. Choosing a MOSFET with a
very low on resistance (RDS(ON)) increases the efficiency of the circuit. The control circuit used
must ensure that both MOSFETs are not on at the same time. This would place a very low
resistance path from the input to ground and destructive currents would flow in the switches.
The synchronous buck converter always operates in continuous conduction mode because
current can reverse in the synchronous MOSFET. So the voltage conversion relationship and
the duty cycle to output voltage transfer function for the synchronous buck converter are the
same as for the continuous conduction mode buck converter.
Figure 2.7 shows a simplified schematic of a synchronous buck converter, with control circuit
block included, which is the dominant topology in applications today for desktop and
notebook. Both power switches are N-channel MOSFETs.
Figure 2.7 Synchronous Buck Converter
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Chapter 2. The Buck Converter
12
2.3 Multiphase Topologies
In the past VRMs used a single conventional buck or synchronous buck topology for power
conversion. They operated at lower switching frequencies with a higher filter inductance
which limited the transient response. In order to meet microprocessor demands huge output
decoupling capacitors were needed.
To reduce VRM output capacitance, a larger inductor current slew rate is needed. Smaller
inductances give larger inductor current slew rates, but smaller inductances result in larger
ripple currents in the circuits steady state operation. These current ripples result in large
output voltage ripples. It is impractical for the circuit to operate in this way.
A solution to reducing the large current ripples in the VRMs is to use interleaving technology.
Interleaving reduces the current ripple to the output capacitors, which in turn reduces the
steady state output voltage ripple. This allows the use of smaller inductances in the VRM to
improve transient response. Using smaller inductances means smaller output capacitance can
be used to meet VRM requirements.
While there is no real limit for a single phase buck regulator, the advantages of designing with
multiphase converters become apparent as load currents increase to their present large values.
These advantages include:

Reduced input-ripple current.

Substantially decreasing the number of input capacitors.

Reduced output-ripple voltage due to an effective multiplication of the ripple
frequency.

Reduced component temperature achieved by distributing the losses over more
components

Reduced-height external components.
The topology of a multi-phase buck converter is shown in Figure 2.8. It consists of n identical
converters with interconnected inputs and outputs.
Sean Kelly - April 2005
Chapter 2. The Buck Converter
13
Figure 2.8 Multiphase Interleaved Buck Converter
Multiphase converters are essentially multiple buck regulators operated in parallel with their
switching frequencies synchronized and phase shifted by 360/n degrees, (where n identifies
each phase). Paralleling converters makes output regulation slightly more complex. This
problem is solved with a current-mode control IC that regulates each inductor current in
addition to the output voltage.
The concept of applying interleaving to VRMs is so successful that it has become the standard
practice in VRM industry.
The main benefit of multiphase technology is the ripple cancellation effect, which allows the
use of small inductances to improve transient responses and minimize output capacitance.
Sean Kelly - April 2005
Chapter 2. The Buck Converter
14
2.4 Pulse Width Modulation (PWM) Control
Switch mode converters use a power semiconductor switch (usually a MOSFET) to drive a
magnetic element (inductor) whose rectified output produces a dc voltage. A common method
of controlling this type of circuit is pulse width modulation (PWM), which controls the power
switch by applying a voltage signal to its gate and varying its ON and OFF times. The ratio of
ON time to switching period is the duty cycle. Figure 2.9 shows three different variations of
PWM duty cycle, 10%, 50% and 90%.
switching
period
(a) 10%
time
(b) 50%
time
(c) 90%
time
Figure 2.9 PWM Waveforms
The generation of a pulse width modulation PWM signal can be achieved as shown in figure
2.10. In (a) a sawtooth waveform is generated and fed into an op-amp. This signal is then
compared with a constant DC voltage. When the sawtooth signal is greater than the DC
voltage, the output of the comparator is a logic ‘1’, and when the sawtooth signal is less than
the DC voltage, the output of the comparator is a logic ‘0’. (b) shows how the PWM
waveform is generated by comparing the DC voltage with the sawtooth waveform.
Sean Kelly - April 2005
Chapter 2. The Buck Converter
Sawtooth
Generator
15
+
PWM
Waveform
DC Voltage
(a)
Sawtooth Waveform
DC voltage
PWM Output
time
(b)
Figure 2.10 PWM Generation
Sean Kelly - April 2005
16
Chapter 3 Intel VRM 10.1 Specification
3.0 Background
Intel publishes specifications for VRMs intended to provide power for a particular processor
family. In addition to establishing electrical performance, these specifications also define the
mechanical dimensions, capacitors mounted on the motherboard, VRM to motherboard
connector, and environmental factors such as airflow and ambient temperature.
The Voltage Regulator (VR) 10.1 Design guidelines defines DC-to-DC converters to help
meet the power requirements of computer systems using Intel® Xeon™ processor with 800
MHz system bus. These guidelines specify the requirements for both VRM (Voltage
Regulator Module) and VRD (Voltage Regulator Down) where the VRM is plugged into a
baseboard and the VRD is embedded on a baseboard.
A voltage regulator module (VRM) is a small module that installs on a motherboard to
regulate the voltage fed to the microprocessor
The processor supply or voltage regulator module (VR10) is typically implemented with a
very efficient buck switching regulator (discussed previously) optimized for converting 12 V
main supply into the core supply voltage. Multiphase operation is important for producing the
high current (in excess of 100 A) and low voltages (1.3 V) demanded by todays
microprocessors. Handling the high currents in a single phase buck would place high thermal
demands on the components in the system such as inductors and MOSFETs (metal-oxidefield-effect-transistors).
Sean Kelly - April 2005
Chapter 3. Intel VRM 10.1 Specification
17
The VRM controller will use an internal digital-to-analog converter (DAC) to read a voltage
identification (VID) code directly from the processor, which is used to set the output voltage
between 0.8375 V and 1.6 V (1.3 V and 1.4 V during normal operation) , and will use PWM
architecture.
The voltage regulator is plugged into a baseboard, where the baseboard is designed to support
more than one processor.
3.1 Features
Intel introduced a new generation of desktop processor codenamed Prescott in 2004. A new
voltage regulator specification, VRM 10.0 was developed to support it. Subsequent versions
of VR10.x are being introduced to support the 2004-2006 generation of Intel microprocessors.
While most of the VRM features are expected to stay the same currents will increase to 150A,
and load line impedance and tolerance will see significant reductions to lower the processor
die voltage to 1V. VRM10.1 is the most recent version of VR10.x and some of the
requirements are outlined.

6 Bit VID with 0.8375-1.6V range and 12.5mV LSB

Dynamic changes in VID code.

One 12.5 mV step every 5μs, up to 36 steps (450mV) in 180μs.

1.25 mΩ load line out to 120A with 40mV tolerance band (see figure 3.2)

Differential Remote Sensing at CPU pins

Supply voltage may overshoot 50mV for 25μs during load step down.
The VRM is required to support the following:

A continuous load current of 105A

A maximum load current of 120A

A maximum load current step, within a 1us period, of 100A

A maximum current slew rate of 930A/us at the pins of the processor
Sean Kelly - April 2005
Chapter 3. Intel VRM 10.1 Specification
18
Figure 3.1 Load Current vs. Time
Figure 3.2 VRM 10.1 Processor Die Load Line
Mechanical dimensions impose further system constraints that effect VR requirements.
Dimensions are 3.8 inches by 2.3 inches with a gold finger connector to the motherboard. The
Sean Kelly - April 2005
Chapter 3. Intel VRM 10.1 Specification
19
small physical size results in higher thermal impedance requiring low power losses to avoid
overheating the components. In general reducing voltage regulator size will increase cost.
System airflow is another important factor. In most desktops there is no airflow dedicated to
VR cooling. The VR usually receives some airflow from the CPU fan.
There are several advantages of the VRM over the VRD. A VRD is mounted directly on the
motherboard while a VRM is plugged into the motherboard with the gold finger connector.
This means the VRM can be easily upgraded or replaced. Using a VRM frees up valuable
motherboard area, and improves cooling because VR is up in whatever airflow is available.
For more detailed information on Intel’s VRM 10.1 Specification refer to Design Guidelines
[3].
Sean Kelly - April 2005
20
Chapter 4 Component Selection
4.0 Output Decoupling
In switching power supply power stages, the function of output capacitance is to store energy.
The energy is stored in the capacitor’s electric field due to the voltage applied. The function
of a capacitor is to attempt to maintain a constant voltage.
Ceramic capacitors have excellent high frequency characteristics so will be recommended in
this case.
Ceramic capacitance of 450 μF is recommended made up of 45 10 μF MLC capacitors.
The bulk capacitors help determine the output ripple voltage and its transient response,
selection is dominated by ESR.
Bulk capacitance of 4.48 mF is recommended made up of 8 560 μF Al-Poly capacitors.
4.0.1 Decoupling guidelines for Intel Xeon Processor with 800 MHz bus.
Due to its large number of transistors and high internal clock speeds the Xeon is capable of
generating large average current swings between low and full power states. This may cause
voltages on power planes to sag below minimum values if bulk decoupling is not adequate.
Larger bulk storage (Cbulk) like electrolytic or aluminium-polymer capacitors supply current
during longer lasting changes in current demand by the component, such as coming out of an
idle condition. Similarly they act as a storage well for current when entering an idle condition
from a running condition.
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance
(ESR). A decoupling solution would consist of a combination of low ESR bulk capacitors and
high frequency ceramic capacitors.
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
21
Number of decoupling capacitorss recommended based on updated processor power
requirements in VRM10.1
14 x 560uF Alum-Polymer
45 x 10uF MLCC
For more information on the Intel Xeon Processor with 800MHz bus refer to device datasheet
[4].
4.1 Output Inductance
In switching power supply power stages, the function of inductors is to store energy. The
energy is stored in their magnetic field due to the current flowing.
The function of an inductor is usually to attempt to maintain a constant current or sometimes
to limit the rate of change of current flow.
The inductor value determines the peak to peak ripple current. Allowable ripple current tends
to be up to fifty percent of the maximum DC output current.
A large inductance reduces the ripple current but can result in a very large and impractical
inductor. A smaller inductance will increase the current ripple but it means that a smaller
inductor can be used in the design, there will be a faster current slew rate, and smaller output
capacitance can be used.
Inductor value of 105 nH is chosen.
4.2 Power Switch
The MOSFETs are very important devices in the circuit. This circuit uses N-channel
Enhancement Mode Field Effect Transistors as shown in figure 4.1.
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
22
Figure 4.1 MOSFET

A majority carrier device: fast switching speed

Typical switching frequencies: hundreds of kHz

On-resistance increases rapidly with rated blocking voltage

Easy to drive
Figure 4.2 MOSFET Equivalent Circuit
Shown in figure 5.x is the equivalent circuit of a MOSFET which includes the intrinsic diode
and capacitances due to the semiconductor manufacturing process. These values need to be
considered when choosing switching devices
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418

Cgs is large and essentially constant.

Cgd is small and highly nonlinear.

Cds is intermediate in value and highly nonlinear.
23
The switching time is determined by the rate at which the gate driver charges/discharges Cgs
and Cgd. The Cgs and Cgd are derived from the MOSFET specifications.
The capacitance values Ciss, Coss, and Crss are the standard capacitances that companies will
list in their datasheets. These values are calculated as follows.

Ciss (input) = Cgd + Cgs

Coss (output) = Cgd + Cds

Crss (reverse transfer) = Cgd
4.2.1 Selection Parameters
These are some of the main values looked at when determining the choice of MOSFETs. All
of these parameters are found in the devices data sheets.
On-Resistance, RDS(ON)
This is the resistance between the source and drain terminals when the MOSFET is fully
turned on.
Gate Threshold Voltage, VGS(th)
This is the minimum voltage that is needed between the gate and source terminals to turn the
MOSFET on.
Drain Current, Id
This is the current that the MOSFET can stand passing from drain to source.
Input Capacitance, Ciss
This is the total capacitance between the gate terminal and the source and drain terminals.
Total Gate Charge, QT
This is the charge that must be supplied to the MOSFET
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
24
Other parameters that need to be looked at are turn-on delay time (td(on)), rise time (tr), turn-off
delay time (td(off)), and fall time (tf) which need to be as small as possible for good switching
performance.
4.2.2 Synchronous MOSFET
The synchronous MOSFET conducts when the power switch turns off and provides a path for
the inductor current.
For the low side MOSFET, the on-resistance (RDS(ON)) is the primary parameter for selection.
Because of the small duty cycle of the high side, the on-resistance determines the power
dissipation in the low side MOSFET and therefore significantly affects the efficiency of the
DC-DC converter. For high current applications, it may be necessary to use two MOSFETs in
parallel for each phase. This effectively reduces the RDS(ON) and therefore reduces the
conduction losses.
International Rectifier IRLR3717 was chosen for the synchronous MOSFET.[5]
4.2.3 Main MOSFET
In switching power supply power stages, the function of the main power switch is to control
the flow of energy from the input power source to the output voltage.
With a duty cycle of around 10 percent, the high side MOSFET switching loses will dominate
the conduction losses. Because the high side MOSFET conducts for a small percentage of
time the conduction losses are less significant.
For the high side MOSFET, the gate charge is as important as the on-resistance, especially
with 12V input and higher switching frequencies. This is because the speed of the transition
greatly affects the power dissipation. It may be a good trade off to select a MOSFET with a
higher RDS(ON) if this means a much smaller gate charge is available. For high current
applications, it may be necessary to use two MOSFETs in parallel for each phase.
As switching losses dominate, need a device with low gate charge and input capacitance.
ST Microelectronics STD35NF3LL was chosen for the main MOSFET.[6]
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
25
4.2.4 Heat Sinks
The maximum junction temperature of a MOSFET is found in its data sheet, typically 175 ºC.
but this is strictly a maximum value and should never be reached.
The life expectancy of a semiconductor is very long at room temperature but for every 5
degree increase in temperature the operating life halves, as shown in table 2
Temperature Operating Life
25 ºC
1,000,000 hours (~11 years)
35 ºC
500,000 hours
45 ºC
250,000 hours
55 ºC
125,000 hours
65 ºC
62,500 hours
75 ºC
31,250 hours
85 ºC
15,625 hours
95 ºC
7,812 hours (~ 325 days)
105 ºC
3,906 hours
115 ºC
1,953 hours
125 ºC
976 hours
135 ºC
488 hours
145 ºC
244 hours
155 ºC
122 hours
165 ºC
61 hours
175 ºC
30 hours
Figure 4.3 Temperature of Semiconductor vs. Operating Life
if the MOSFET were to operate at the maximum rating from the data sheet of 175 ºC it would
only last about a day. So the operating temperature would obviously need to be lower than
this.
All semiconductor devices have some electrical resistance. This means that when power
MOSFETs are switching currents, they dissipate power as heat. If the power dissipation is
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
26
high enough, this heat will need to be removed from inside the device to prevent too much of
a temperature rise. The most common method of doing this is by using a heatsink.
T(j-a) = Pd x Rth(j-a)
Where T(j-a) is the temperature rise of the transistor above the ambient temperature, Pd is the
power being dissipated and Rth(j-a) is the total thermal resistance.
Rearranging gives:
Pd = Rth(j-a) / T(j-a)
Usually the Tjmax for silicon devices is 150 ºC so T(j-a) will be 150 – 25 = 125
So from the manufacturers data sheet the maximum power dissipation in
(a) synchronous MOSFET
Rth(j-a) = 110 ºC /W
So Pd = 125 / 110 = 1.14W
(b) main MOSFET
Rth(j-a) = 100 ºC /W
So Pd = 125 / 100 = 1.25W
This is the maximum power dissipation in each MOSFET. If the power dissipation
calculated for the MOSFETs is larger than this, the use of a heatsink will be advisable.
A heatsink works by effectively reducing the Rth( j-a). The total thermal resistance is
made up of two thermal resistances, the thermal resistance inside the device package
between the junction and case, Rth(j-c), and the thermal resistance between the case and
ambient, Rth(c-a).
Rth(j-c) is a fixed value given in the devices data sheet, but Rth(c-a) can be lowered by
using a heatsink with a low thermal resistance.
Sean Kelly - April 2005
27
Chapter 5 Analog Devices ADP3188 & ADP3418
Analog devices are a leading manufacturer of precision high performance integrated circuits
used in analog and digital signal processing applications.
Analog’s multi-phase controller ADP3188 and synchronous rectified MOSFET driver
ADP3418 are suitable for the multi-phase interleaved DC-DC buck converter implementation.
This chapter gives a brief introduction of Analog’s four-phase controller ADP3188 and
synchronous rectified driver ADP3418. A step by step design procedure for a 12V to 1.3V
@120A, 500 kHz using the interleaved approach follows. It includes all the fundamental
formulae to design a multi-phase interleaved DC-DC buck converter.
The ADP3188 controller coupled with some ADP3418 single-channel driver ICs form the
basic building blocks for applications which demand high current and rapid load transient
speed.
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
28
5.0 ADP3188
Figure 5.1 Functional Block Diagram of ADP3188
The ADP3188 is Analog’s third generation of multi-phase power solutions to be used by
Intel. It is a highly efficient synchronous buck switching regulator controller optimized for
converting a 12 V main supply into the core supply voltage required by high performance
Intel processors. It uses an internal 6-bit DAC to read a voltage identification code (VID)
directly from the processor, which is used to set the output voltage between 0.8375 V and 1.6
V. It offers programmable 2- to 4- phase PWM topology, the ADP3188 optimises phase count
to minimize system cost.
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
29
It also provides active current and thermal sharing between output phases, reducing the ratio
between size and power components to prevent thermal imbalance. The ADP3188 includes a
built in PWRGD (Power Good) delay circuit, meeting Intel’s VID on-the-fly specification for
power regulation. Each phase uses an ADP3418 MOSFET driver to complete the interface
between the ADP3188 and the power MOSFETs used to convert the main supply to VID
voltage. For more detailed descriptions of the ADP3188 functionality, refer to the device
datasheet [8].
5.1 ADP3418
Figure 5.2 Functional Block Diagram of ADP3418
The ADP3418 is a dual high voltage MOSFET driver optimized for driving two N-channel
MOSFETs, the two switches in a non isolated, synchronous, buck power converter. Each of
the drivers is capable of driving a 3000pF load with a 30ns transition time. One of the drivers
can be bootstrapped, and is designed to handle the high voltage slew rate associated with
floating high-side gate drivers. The ADP3418 includes overlapping drive protection to
prevent shoot-through current in the external MOSFETs. The OD pin shuts off both the highside and the low side MOSFETs to prevent rapid output capacitor discharge during system
shutdowns. For more detailed descriptions of the ADP3418 functionality, refer to the device
datasheet [9].
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
30
5.2 Initial Design Spec
The design parameters for a typical Intel VRM 10.1 compliant CPU application are:

Input Voltage
=
12 V

VID setting voltage (VVID)
=
1.3 V

Duty Cycle (D)
=
0.108

Nominal output voltage at no load (VONL)
=
1.28 V

Nominal output voltage at 120A load (VOFL)
=
1.13 V

Static output voltage drop based on a 1.25mΩ load line (RO) from no load to full load

VD = VONL - VOFL
=
150 mV

Maximum output Current (IO)
=
120 A

Maximum output current step (d IO)
=
105 A

Number of phases (n)
=
4

Switching frequency per phase (fSW)
=
500 kHz
5.3 Design Procedure
This section summarizes a step-by-step procedure for a 12V-to-1.3V @120A power
supply for high current and high transient speed applications.

Setting clock frequency
RT is an external resistor used to set the clock frequency. This clock frequency
divided by the number of phases determines the switching frequency per phase.
The switching frequency will be used to determine the size of the inductors and
input and output capacitors and switching losses.
RT
=
1
 27k
n  fSW  4.7 pF
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
31
=
1
 27k
4  500k  4.7 pF
=
79.4kΩ
where 4.7 pF and 27 kΩ are internal IC component values.

Soft Start & Current Limit Latch off delay times
Soft start allows the power converter to gradually reach the initial steady state operating
point, this reduces start up stress and surges. The capacitor and resistor combination
establish the soft start time.
CDLY
=

VVID
20A 
2  RDLY

 t SS

 VVID
Where tSS is the desired soft start time of 3ms.
CDLY
=
42nF
Choosing the closest 1 % standard capacitor
CDLY
=
39nF
RDLY
=
1.96  tDELAY
CDLY
=
452kΩ
Choosing the closest 5 % standard resistor
RDLY

=
470kΩ
Inductor Selection
The choice of inductance for the inductor determines the ripple current in the
inductor. The smaller the inductance the bigger the ripple current, which increases the
output voltage ripple and conduction losses in the MOSFETs but the advantages are
using smaller inductors and less total output capacitance.
L
≥
VVID  RO  (1  (n  D))
fSW  VRIPPLE
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
≥
1.3V  1.25m  (1  (4  0.108))
500kHz  18mV
≥
102 nH
32
Choose inductor value
L
=
105 nH
IR
=
VVID  (1  D)
fSW  L
=
22 A
IR 50% of max DC current in inductor
Inductor should not saturate at peak current of 41 A
DCR (DC Resistance)
The DCR is used for measuring the phase currents. A large DCR can cause excessive
power losses, while too small a value can lead to increased measurement error.
DCR should be 1 - 1½ times droop resistance (RO)
Use a DCR of 1.4mΩ

Output Droop Resistance
The design requires that the regulator output voltage measured at the CPU pins drops
when the output current increases. The specified voltage drop corresponds to a dc
output resistance (Ro)
The output current is measured by summing the voltage across each inductor and
passing the signal through a low-pass filter.
RO
=
RPH(X) =
=

RCS
 RL
RPH ( X )
1.4m
 100k
1.25m
112 kΩ
Inductor DCR temperature correction
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
33
The Inductor’s DCR is used as the sense element and copper wire is source of the
DCR, need to compensate for temperature changes of the inductors winding.
Temperature coefficient of copper = 0.39 % / 0C = 0.0039
A
RTH (50 0 C )
RTH ( 25 0 C )
=
B
=
RTH (90 0 C )
RTH ( 25 0 C )
Relative values of RCS for each temperature 500C & 900C
r1=
=
1
1  (TC  (T 1  25))
r2=
0.9112
=
1
1  (TC  (T 2  25))
0.7978
Relative values for RCS1, RCS2 and RTH
rCS2 =
rCS1 =
rTH =
( A  B)  r1  r 2  A  (1  B)  r 2  B  (1  A)  r1
= 0.7195
A  (1  B)  r1  B  (1  A)  r 2  ( A  B)
(1  A)
1
A

1  rCS 2 r1  rCS 2
1
1
1

1  rCS 2 rCS 1
RTH
=
k
=
=
rTH  RCS
= 0.3795
1.075
=
118.28kΩ
=
0.8455
RCS  k  rCS1 R =
35.3kΩ
RTH ( ACTUAL)
RTH (CALCULATED)
Calculate RCS1 and RCS2
RCS1
=
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
RCS2
34
= RCS  ((1  k )  (k  rCS 2))
=
83.9kΩ
Choosing closest 1 % resistor gives:
RCS1 = 35.7 kΩ
RCS2 = 84.5 kΩ

Output Offset
The Intel specification requires that at no load the nominal output voltage of the regulator
be offset to a value lower than the nominal voltage corresponding to the VID code.
Offset set by constant current source from FB pin through RB
RB
VVID  VONL
IFB
=
=
1.3V  1.28V
=
15.5A
Choosing closest 1 % standard resistor gives
RB

1.3 kΩ
=
COUT Selection
Ceramic Capacitance
Use 18 X 10μF 1206 capacitors
Cz
=
180 μF
Bulk Capacitance
Cx(MIN) ≥
L  IO
 CZ
Vrl
n  ( RO 
)  VVID
IO
Sean Kelly - April 2005
1.29kΩ
Chapter 5. Analog Devices ADP3188 & 3418
≥
=
Cx(MAX)≤
Where k =
*
35
105nH 100 A
 180 F
50mV
4  (1.25m 
)  1.3V
100 A
1 mF
L
2
nK RO
-ln (
2

VV
V
nKRO 2
 ( 1  (tV VID 
)  1)  C Z
VVID
VV
L
V ERR
)
VV
=
5.2
The VRM must be capable of accepting voltage level changes of 12.5 mV steps every
5 μs, up to 36 steps (450 mV) in 180 μs
VV = 450 mV,
tV = 180 μs,
VERR = 2.5 mV.
Cx(MAX)≤
105nH  450mV
180s 1.3V  4  5.2 1.25m 2
 ( 1 (
)  1)  180F
2
2
450mV 105nH
4  5.2 1.25m 1.3V
Cx(MAX)≤
27.3mF
Use eight 560 μF Al-Poly capacitors with a typical ESR of 5mΩ each yields Cx = 4.48
mF with an Rx = 0.63mΩ
Lx
≤
CZ  RO  Q 2
≤
180F  1.25m 2  2 ≤
2
Where Q is limited to 2 to ensure a critically damped system.

Power MOSFETS
Guideline is to limit power dissipation to 1 W per MOSFET
Sean Kelly - April 2005
563pF
Chapter 5. Analog Devices ADP3188 & 3418
36
Synchronous MOSFETs
With conduction losses being dominant
The power dissipated in each synchronous MOSFET
PSF
PSF
IO 2 1
n IR 2
)  (
) ]  RDS ( SF )
nSF
12
nSF
=
(1  D)  [(
=
(1  0.108)  [(
=
1.34 W
120 A 2 1
4  22 A 2
)  (
) ]  6.4m
8
12
8
Main MOSFETs
There are two main power dissipation components in main MOSFETs
Switching loss per main MOSFET:
PS(MF)
VCC  I O
n
 RG  MF  C ISS
nMF
n
=
2  f SW 
=
2  500kHz 
=
864 mW
12V 120 A
8
 3   800 pF
8
4
Conduction loss per main MOSFET:
PC(MF) =
D  [(
IO 2 1
n  IR 2
)  (
) ]  RDS ( MF )
nMF
12
nMF
=
0.108  [(
=
584 mW
120 A 2 1
4  22 A 2
)  (
) ]  23m
8
12
8
The power dissipated in each main MOSFET
PMF
=
1.45 W
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
37
Used ST Microelectronics STD35NF3LL as the main MOSFET (eight total nMF = 8) with
a CISS = 800 pF and RDS(MF) = 23 mΩ.
In the datasheet the STD35NF3LL the RDS(ON) is 16mΩ but this is a value at 25 ºC. One
needs to account for the RDS(ON) at a temperature of 120 ºC. From the RDS(ON) vs.
Temperature graph in the data sheet the factor to multiply the RDS(ON) @ 25 ºC is found to
be ~1.45 so the RDS(ON) @ 120 ºC is found to be 23 mΩ.
Used International Rectifier IRLU3717 as the synchronous MOSFET (eight total nSF = 8)
with a CISS = 2830 pF and RDS(SF) = 6.4 mΩ.
Similarly In the datasheet the IRLU3717 the RDS(ON) is 4.6mΩ but this is a value at 25 ºC.
One needs to account for the RDS(ON) at a temperature of 120 ºC. From the RDS(ON) vs.
Temperature graph in the data sheet the factor to multiply the RDS(ON) @ 25 ºC is found to
be ~1.4 so the RDS(ON) @ 120 ºC is found to be 6.4 mΩ.
Power dissipation in the driver per phase
PDRV
=
[
f SW
 (nMF  QGMF  nSF  QGSF )  I CC ]  VCC
2 n
=
[
500kHz
 (8 12.5nC  8  21nC )  6mA] 12V
2 4
=
273 mW
in each driver which is below 400mW dissipation limit

Ramp Resistor Selection
The ramp resistor RR is used for setting the size of the internal PWM ramp. The value of
the resistor is chosen to provide the best combination of thermal balance, stability, and
transient response.
RR
=
AR  L
3  AD  RDS  C R
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
38
=
0.2 105nH
3  5  2.4m  5 pF
=
117 kΩ
where AR is the internal ramp amplifier gain, AD is the current balancing amplifier gain,
RDS is the total low-side MOSFET on resistance, and CR is the internal ramp capacitor
value.
Choosing closest 1 % standard resistor gives
RR
=
117 kΩ
Internal ramp voltage magnitude determined by:
VR

=
AR  (1  D)  VVID
RR  C R  f SW
=
0.2  (1  0.108) 1.3V
117k  5 pF  500kHz
=
0.59
=
590 mV
Comp Pin Ramp
A ramp signal on the COMP pin is due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the following overall ramp
signal at the PWM input:
VRT
=
=
=

VR
2  (1  n  D)
1
n  f SW  C X  RO
590mV
2  (1  4  0.108)
1
4  500kHz  4.48mF 1.25m
657 mV
Current Limit Set Point
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
39
The current limit threshold for the ADP3188 is set with a 3 V source (VLIM) across
RLIM with a gain of 10.4 mV/uA (ALIM)
RLIM
=
ALIM  VLIM
I LIM  RO
=
10.4mV / A  3V
120 A  1.25m
=
208 kΩ
Choosing closest 1 % standard resistor gives
RLIM
=
IPHLIM =
205 kΩ
VCOMP( MAX )  VR  VBIAS
AD  RDS ( MAX )

IR
2
=
3.3V  590mV  1.2V 22 A

5  3m
2
=
112 A
The per phase initial duty cycle is determined by:
DMAX
VCOMP( MAX )  VBIAS
=
D
=
0.108 
=
0.35
VRT
3.3V  1.2V
657mV
Shown in figure 5.3 is the circuit which shows how the four phases of the interleaved buck
converter would be controlled with the controller and MOSFET driver ICs.
Sean Kelly - April 2005
Chapter 5. Analog Devices ADP3188 & 3418
+12V Supply
40
Iin
Lin
Cin
1/4 Iout
DRIVER
Lout
1/4 Iout
DRIVER
Lout
VRM
CONTROLLER
Iout
1/4 Iout
DRIVER
Lout
1/4 Iout
DRIVER
Lout
Figure 5.3 Circuit Diagram
Sean Kelly - April 2005
Cout
41
Chapter 6 Computer Simulation
6.0 Pspice
Pspice is a software package used to simulate power electronic circuits.
The student version is available on the ORCAD website; this was downloaded and used for
simulation of the circuits once design procedure was completed. The pspice manual was also
downloaded from this website and was found to be a valuable resource [10].
With the student version the number of nodes that can be used is limited so the model of a
multi-phase interleaving buck converter can be simplified and analysed as a single-phase buck
converter. The equivalent inductance in the simplified model is 1/n of the inductance in each
phase. The equivalent switching frequency of the simplified model is n times the switching
frequency in each phase. So the multi-phase interleaving buck converter can be analysed in
the same way as a single-phase buck converter.
The buck circuit is constructed with LC values calculated from the formulae. The frequency
and pulse width desired are obtained using pulse voltage sources to simulate the drivers. The
circuit would appear as below in Pspice.
Sean Kelly - April 2005
Chapter 6. Computer Simulation
42
PARAMETERS:
Fs = 2000k
DUTY = 0.108
MF1
0
1
1
2
L1
3
2
80n
NTD40N03R
MF2
0
1
3
2
MF3
0
1
NTD40N03R
V1
12Vdc
1
2
V2
1
2
3
2
C1
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY/Fs}
PER = {1/Fs}
V1 = 0
TR = 1n
V2 = 7
4.48m
MF4
0
1
V3
1
2
3
2
R1
43.33m
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY/Fs}
PER = {1/Fs}
V1 = 7
TR = 1n
V2 = 0
0
Figure 6.1 Buck Circuit
This circuit file uses MOSFET models provided by the manufacturer for users. Most major
companies provide spice models of their discrete products. For a good guide on how to import
these vendor models, see [9].
The MOSFET pspice models, NTD40N03R (upper MOSFET) and NTD110N02R
(synchronous MOSFET), were downloaded from the ONSEMICONDUCTOR website to be
used in the circuit for more accurate testing.
Another useful feature of pspice is the ability to set a part called parameters where variables
can then be set and modified easily, this can be seen in figure 6.1.
The simulation results for the circuit are shown below. In figure 6.2 is the output voltage
waveform. Output voltage is found to be 1V. This deviation from the expected 1.3V is mainly
due to power losses in the MOSFETs, as when more MOSFETs are added to the circuit in
parallel the output voltage tends to 1.3V. There will also be discrepancies due to the fact that
the equivalent series resistance (ESR) and equivalent series inductance (ESL) of the output
capacitance has not been taken into account at this stage.
Sean Kelly - April 2005
V
Chapter 6. Computer Simulation
43
Figure 6.2 Output Voltage Waveform
In figure 6.3 is the output filter current waveforms which shows the inductor, capacitor and
resistor waveforms. From this we can see how the inductor ripple current is filtered out by the
output capacitance and the load sees the DC current. This current is also lower than expected
due to the non-ideal components being used.
Figure 6.3 Output Filter Waveforms
Sean Kelly - April 2005
Chapter 6. Computer Simulation
44
6.1 Modifying Circuit
The circuit was then redesigned to account for effects of non-ideal active and passive
components such as the ESR of the inductor, ESR and ESL of capacitance, and power losses
across the power MOSFETs.
The equivalent series resistance (ESR) and equivalent series inductance (ESL) were found
from the manufacturers’ data sheet. The ESL is calculated from the impedance versus
frequency curve.
The duty cycle is also modified to take account of the fact that the active and passive models
are non-ideal. The modified circuit appears as below in pspice.
PARAMETERS:
Fs = 2000k
DUTY = 0.13
MF1
0
1
1
2
L1
3
R3
2
80n
1.4m
NTD40N03R
MF2
0
1
3
2
C1
4.48m
MF3
0
1
NTD40N03R
V1
12Vdc
1
2
V2
1
2
3
2
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY /Fs}
PER = {1/Fs}
V1 = 0
TR = 1n
V2 = 7
R2
R1
V
MF4
0
1
V3
1
2
3
2
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY /Fs}
PER = {1/Fs}
V1 = 7
TR = 1n
V2 = 0
0
Figure 6.4 Modified Buck Circuit
and the simulation results are presented below. Figure 6.5 has the new output voltage
waveform which is much closer to the desired value.
Sean Kelly - April 2005
.63m
L2
125p
43.33m
Chapter 6. Computer Simulation
45
Figure 6.5 New Output Voltage Waveform
Figure 6.6 shows the new output inductor, capacitor and resistor current waveforms.
Figure 6.6 New Output Filter Waveforms
Sean Kelly - April 2005
Chapter 6. Computer Simulation
46
6.2 Transient Analysis
The Intel VRM 10.1 specification specifies a 930 A/μs current slew rate at the pins of the
microprocessor. Intel’s recommendations for output decoupling was modeled and a transient
analysis was performed on the circuit to simulate a load transient from light to heavy and
heavy to light load respectively. This should translate to a current slew rate of 100 A/μs at the
output of the voltage regulator. The results are presented below.
U16
0
1 1
2
3
L4
L5
80n
10p
R4
L6
R5
0.3m
20p
0.34m
2
I
NTD40N03R
U15
0
1 1
2
C1
3
2
0
1 1
2
V2
12Vdc
C3
370u
80u
U8
NTD40N03R
V1
C2
7840u
3
2
R1
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY/Fs}
PER = {1/Fs}
V1 = 0
TR = 1n
V2 = 7
R2
0.5m
R3
0.27m
1.25m
U7
0
1 1
2
V3
3
2
L1
L2
286p
32p
I1 = 0
I1
I2 = 100
TD = 400us
TR = 0.107us
TF = 0.107us
PW = 50u
PER = 100.414u
L3
150p
NTD110N02R
TD = 0
TF = 1n
PW = {DUTY/Fs}
PER = {1/Fs}
V1 = 7
TR = 1n
V2 = 0
PARAMETERS:
Fs = 2000k
DUTY = 0.108
0
Figure 6.7 Load Transient Analysis Circuit
These results show that when there is a 930 A/μs load transient is seen at the pins, the output
decoupling is sufficient to limit this current slew to a rate of 100 A/μs at the VR output.
While there should be a more steady 100 A/μs at the VR output. The reason this is not the
case is because both the ceramic and electrolytic capacitances can not be modeled in the
circuit.
Sean Kelly - April 2005
I
Chapter 6. Computer Simulation
47
Figure 6.8 Light to Heavy Load Transient
Figure 6.9 Heavy to Light Load Transient
Sean Kelly - April 2005
48
Chapter 7 Hardware Implementation
7.0 Switching Circuit
When simulation of the circuit was completed, the components required for building the
circuit were ordered. The main section of the switching circuit was interfacing the MOSFET
drivers with the MOSFETs. This was done phase by phase with testing of each individual
phase before the four phases were combined to form the multi phase switching circuit which
is shown in figure 7.1.
Figure 7.1 Switching Circuit
Sean Kelly - April 2005
Chapter 6. Computer Simulation
49
When this was done, the complete switching circuit could be tested. It was found that the
MOSFET drivers were overheating rapidly and on evaluation it was found that the MOSFETs
gate charge could be a problem. At this stage it was found that the gate charge of the
MOSFETs is a very important parameter as if it is too high there will be too much power
dissipation in the MOSFET drivers and they will be in danger of blowing. The MOSFETs
were replaced with more suitable devices and the circuit was found to be operating correctly
the switching waveforms for the four phases were taken on the oscilloscope and the data was
graphed using excel, the results are presented below in figure 7.2. The circuit was tested at
100kHz (a period of 10μs), and with a duty of 0.25. The control circuit would then delay each
subsequent phase so they were 90 degrees out of phase with each adjoining phase.
Output of Switching Circuit
15.00
Voltage
10.00
5.00
Phase 1
Phase 2
0.00
Phase 3
-5.00
Phase 4
-10.00
-15.00
Time
Figure 7.2 Output of Switching Circuit
Sean Kelly - April 2005
Chapter 6. Computer Simulation
50
7.1 Output Filter
When the switching circuit was built, tested and operating correctly. The next stage was to
build the output filter. The filter consists of the output capacitance, load resistance and the
inductors (1 per phase), these were designed by Christine Collins, a postgraduate student in
the electronic engineering department in NUIG. By controlling these inductors, with the
switching circuit discussed previously, they can be tested for efficiency and other value for
inductance can also be tested in the same way. Shown in figure 7.3 is the output filter
interfaced with the switching circuit.
Figure 7.3 Switching Circuit and Output Filter
Sean Kelly - April 2005
Chapter 6. Computer Simulation
51
7.2 Control Circuit
The last stage of building the circuit is the control circuit for the switching stage. This needs
to take a PWM square wave and delay this for each phase by the period divided by number of
phases. The square wave was produced using an offset, duty cycle square wave from a signal
generator. This square wave is then delayed for each phase, using an analogue delay circuit as
shown in figure 7.4
Rf
249
249
OUT
C
+
V+
Vin
V-
Rg
Vout
AD8055
47nF
R
106
Figure 7.4 An Analogue Delay Circuit
This circuit provides a controllable analogue delay providing an op-amp with a wide
bandwidth is selected. The circuit has the following transfer function.
Vo 1  RCs

Vi 1  RCs
where the RC time constant equals half the desired delay time.
So when testing at 100kHz this has a period of 10μs so the desired time delay is 2.5μs .
This translates to a resistor value of 100Ω and a capacitor value of 12nF.
Sean Kelly - April 2005
Chapter 6. Computer Simulation
52
Chapter 8 Conclusions
The overall aim of this project was to design and build a voltage regulator module (VRM) so
it could be used to test magnetic components. This goal was realized and switching circuit is
ready for testing of inductors.
A lot of background research was involved during the early stages of the project into such
areas as the buck converter topology and VRM 10.1 Design Guidelines which has proved to
be a very interesting research area.
Once the design procedure for the controller IC and MOSFET driver IC was completed, and
circuit was fully simulated in Pspice, Building of the circuit could begin. This was a very
interesting stage of the project and a lot of invaluable skills were learned such as component
layout and selection which cannot be learned during the design procedure.
A complete switching circuit is now fully completed and working. This can now be used for
testing of different types and sizes of inductors and analyzing their performance.
The future for voltage regulator module (VRM) designers will be very demanding. As the
currents increase and voltages decrease, stricter demands will be placed on the load line and
thermal issues will become extremely important. In the future it is expected that the parasitic
resistance between the regulator and microprocessor will become much more of an issue and
it may be necessary to integrate the voltage regulator onto the microprocessor die but this will
require a big breakthrough in silicon technologies.
This project has been both challenging and enjoyable. I find the area of power electronics
very interesting and would consider pursuing it after college. I feel the skills I have acquired
such as project management, presentation skills and research ability will be very helpful in the
future.
Sean Kelly - April 2005
Chapter 6. Computer Simulation
53
References
[1] Moore’s Law
http://www.intel.com/technology/silicon/mooreslaw/
[2] Professor W. G. Hurley “ EE411 Power Electronics” course notes.
[3] Intel Corporation “Intel VRM 10.1 Specification Design Guidelines”.
http://www.intel.com/design/Xeon/guides/302732.htm
[4] Intel Corporation “Intel Xeon Processor Data Sheet”.
http://www.intel.com/design/xeon/datashts/302355.htm
[5] International Rectifier, synchronous MOSFET, “IRLU3717 Data Sheet”.
http://ec.irf.com/v6/en/US/adirect/ir?cmd=catProductDetail&dummy=1&productID=IRLU3717%
3A
[6] ST Microelectronics, main MOSFET, “STD35NFLL Data Sheet”.
http://www.alldatasheet.com/datasheet-pdf/pdf/STMICROELECTRONICS/STD35NF3LL.html
[7] An introduction to Heatsinks and Cooling
http://www.homepage.which.net/~paul.hills/Heatsinks/...
[8] Analog Devices, controller IC, “Analogs ADP3188 Data Sheet”
http://www.analog.com/en/prod/0,2877,ADP3188,00.html
[9] Analog Devices, MOSFET driver, “Analogs ADP3418 Data Sheet”
http://www.analog.com/en/prod/0,2877,ADP3418,00.html
[10] Pspice manual, psicemanual.pdf can be found on project webpage.
[11] Importing vendor SPICE models into MicroSim Schematics
http://www.orcad.com/community.pspice.faqs.aspx#modeling
Sean Kelly - April 2005
Chapter 6. Computer Simulation
54
[12] An Analogue Delay Circuit.
http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=6348
Sean Kelly - April 2005