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REF200
SBVS020B – SEPTEMBER 2000 – REVISED JULY 2015
REF200 Dual Current Source and Current Sink
1 Features
3 Description
•
The REF200 combines three circuit building-blocks
on a single monolithic chip: two 100-µA current
sources and a current mirror. The sections are
dielectrically isolated, making them completely
independent. Also, because the current sources are
two-terminal devices, they can be used equally well
as current sinks. The performance of each section is
individually measured and laser-trimmed to achieve
high accuracy at low cost.
1
•
•
•
•
Completely Floating: No Power Supply or Ground
Connections
High Accuracy: 100 µA ±0.5%
Low Temperature Coefficient: ±25 ppm/°C
Wide Voltage Compliance: 2.5 V to 40 V
Includes Current Mirror
2 Applications
•
•
•
•
•
•
The sections can be pin-strapped for currents of 50
µA, 100 µA, 200 µA, 300 µA, or 400 µA. External
circuitry can obtain virtually any current. These and
many other circuit techniques are shown in the
Application Information section of this data sheet.
Sensor Excitation
Biasing Circuitry
Offsetting Current Loops
Low Voltage References
Charge-pump Circuitry
Hybrid Microcircuits
The REF200 is available in an SOIC package.
Device Information(1)
PART NUMBER
REF200
PACKAGE
SOIC (8)
BODY SIZE (NOM)
3.91 mm × 4.90 mm
(1) For all available packages, see the package addendum at the
end of the data sheet.
Functional Block Diagram
I1
High
I2
High
Substrate
Mirror
In
8
7
6
5
100µA
100µA
1
2
3
4
I1
Low
I2
Low
Mirror
Common
Mirror
Out
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
REF200
SBVS020B – SEPTEMBER 2000 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
5
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
8
8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
8.3 System Examples ................................................... 12
9 Power Supply Recommendations...................... 25
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2015) to Revision B
•
Changed multiple instances of "mA" in data sheet back to "µA" (typo) ................................................................................. 1
Changes from Original (September 2000) to Revision A
•
2
Page
Page
Added ESD Ratings and Recommended Operating Conditions tables, and Feature Description, Device Functional
Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation
Support, and Mechanical, Packaging, and Orderable Information sections........................................................................... 1
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5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
I1 Low
1
8
I1 High
I2 Low
2
7
I2 High
Mirror Common
3
6
Substrate
Mirror Output
4
5
Mirror Input
Pin Functions
PIN
DESCRIPTION
NAME
NO.
I1 Low
1
Current source 1 low terminal
I2 Low
2
Current source 2 low terminal
Mirror Common
3
Current mirror common terminal
Mirror Output
4
Current mirror output terminal
Mirror Input
5
Current mirror input terminal
Substrate
6
Substrate (Usually connected to most negative potential in the system)
I2 High
7
Current source 2 high terminal
I1 High
8
Current source 1 high terminal
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–6
40
V
Reverse current
–350
µA
Voltage between any two sections
±80
V
Applied voltage
Tstg
(1)
Operating temperature
–40
85
°C
Storage temperature
–40
125
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V(ESD)
(1)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101
(1)
VALUE
UNIT
±750
V
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCOMP
Compliance voltage
2.5
40
V
TA
Specified temperature range
–25
85
°C
TYP
MAX
UNIT
Current accuracy
±0.25%
±1%
Current match
±0.25%
±1%
6.4 Electrical Characteristics
at TA = 25°C, VS = 15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
CURRENT SOURCES
Temperature drift
Output impedance
Noise
Voltage compliance (1%)
Specified temperature range
25
2.5 V to 40 V
20
3.5 V to 30 V
200
BW = 0.1 Hz to 10 Hz
f = 10 kHz
TMIN to TMAX
ppm/°C
100
500
MΩ
1
nAp-p
20
pA/√Hz
See Typical Characteristics
Capacitance
10
pF
CURRENT MIRROR – I = 100 µA unless otherwise noted
Gain
0.995
Temperature drift
Impedance (output)
2 V to 40 V
Nonlinearity
I = 0 µA to 250 µA
Input voltage
4
1.005
ppm/°C
100
MΩ
0.05%
1.4
Output compliance voltage
Frequency response (–3 dB)
40
1
25
V
See Typical Characteristics
Transfer
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6.5 Typical Characteristics
100.1
600
100
500
99.9
400
Quantity (Units)
Current (µA)
at TA = 25°C, VS = 15 V (unless otherwise noted)
99.8
Drift specified by
“box method”
(See text)
99.7
85°C
501
454
Distribution of three
production lots —
1284 Current Sources.
300
200
–50
–25
0
25
50
75
100
0
125
30 15
5
6
0
1
1
10 15 20 25 30 35 40 45 50 55 60 65
Temperature Drift (ppm/°C)
Temperature (°C)
Figure 1. Current Source Typical Drift vs Temperature
Figure 2. Current Source Temperature Drift Distribution
101
100.5
100.8
100.4
100.6
100.3
100.4
100.2
Current (µA)
Current (µA)
66
5
2
0
99.5
117
86
100
99.6
100.2
100
99.8
100.1
25°C
100
99.9
99.6
99.8
99.4
99.7
99.2
99
99.6
–55°C
125°C
99.5
0
5
10
15
20
25
30
35
0
40
1
2
3
4
5
Voltage (V)
Voltage (V)
Figure 4. Current Source Output Current vs Voltage
Figure 3. Current Source Output Current vs Voltage
1000
900
12kW
Reverse Current (µA)
800
7V
Reverse Voltage
Circuit Model
700
600
5kW
500
400
Safe Reverse Current
300
200
Safe Reverse Voltage
100
0
0
–2
–4
–6
–8
–10
–12
Reverse Voltage (V)
Figure 5. Current Source Current Noise (0.1 Hz to 10 Hz)
Figure 6. Current Source Reverse Current vs Reverse
Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = 15 V (unless otherwise noted)
5
0.1
4
VO = 1V
2
Error (%)
Nonlinearity (% of 250µA)
3
1
0
–1
VO = 1.5V
–2
–3
–4
–5
10µA
Data from Three
Representative Units
(Least-square fit)
0.08
VO =
1.25V
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.01
100µA
0
1mA
50
100
150
200
250
Current (µA)
Mirror Current (A)
Figure 8. Mirror Transfer Nonlinearity
Figure 7. Mirror Gain Error vs Current
4
Input Voltage (V)
3
2
Input Voltage
Output
Compliance
Voltage
1
0
1µA
10µA
100µA
1mA
10mA
Current
Figure 9. Mirror Input Voltage and Output Compliance Voltage vs Current
6
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7 Detailed Description
7.1 Overview
The REF200 device combines three circuit building-blocks on a single monolithic chip—two 100-µA current
sources and a current mirror. The sections are dielectrically isolated, making them completely independent. Also,
because the current sources are two terminal devices, they can be used equally well as current sinks. The
performance of each section is individually measured and laser-trimmed to achieve high accuracy at low cost.
7.2 Functional Block Diagram
I1
High
I2
High
Substrate
Mirror
In
8
7
6
5
100µA
100µA
1
2
3
4
I1
Low
I2
Low
Mirror
Common
Mirror
Out
7.3 Feature Description
7.3.1 Temperature Drift
Drift performance is specified by the box method, as illustrated in Figure 1. The upper and lower current
extremes measured over temperature define the top and bottom of the box. The sides are determined by the
specified temperature range of the device. The drift of the unit is the slope of the diagonal, typically 25 ppm/°C
from –25°C to +85°C.
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7.4 Device Functional Modes
The three circuit sections of the REF200 are electrically isolated from one another, using a dielectrically-isolated
fabrication process. A substrate connection is provided (pin 6), which is isolated from all circuitry. This pin should
be connected to a defined circuit potential to assure rated DC performance. The preferred connection is to the
most negative constant potential in the system. In most analog systems, this would be –VS. For best ac
performance, leave pin 6 open and leave unused sections unconnected. Figure 10 shows the simplified circuit
diagram of the REF200.
5
8,7
4
5kΩ
1kΩ
1kΩ
3
Current
Mirror
(Substrate)
Current
Source
(1 of 2)
8X
12kΩ
4kΩ
6
1,2
Figure 10. Simplified Circuit Diagram
8
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Applications for the REF200 are limitless. Application Bulletin AB-165 (SBOA046) shows additional REF200
circuits as well as other related current source techniques. In this section, a collection of circuits are shown to
illustrate some techniques.
If the current sources are subjected to reverse voltage, a protection diode may be required. A reverse voltage
circuit model of the REF200 is shown in Figure 6. If reverse voltage is limited to less than 6 V or reverse current
is limited to less than 350 µA, then no protection circuitry is required. A parallel diode (see (a) in Figure 17)
protects the device by limiting the reverse voltage across the current source to approximately 0.7 V. In some
applications, a series diode may be preferable (see (b) in Figure 17), because it allows no reverse current. This
configuration, however, reduces the compliance voltage range by one diode drop.
8.2 Typical Application
Figure 11 shows the schematic of a circuit that translates RTD resistance to a voltage level convenient for an
ADC input. The REF200 precision current reference provides excitation and an instrumentation amplifier scales
the signal. The design also uses a 3-wire RTD configuration to minimize errors due to wiring resistance.
+5V
REF200
3 Wire
RTD
+5V
RTD
R1 2k
+
R3 78.7
INA326
Vout
R1
R2
±
C2 220p
100µA
R2 698k
100µA
Figure 11. RTD Resistance to Voltage Converter Schematic
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Typical Application (continued)
8.2.1 Design Requirements
The design requirements are as follows:
• Supply Voltage: 5 V
• RTD temperature range: –50°C to +125°C
• RTD resistance range 80.3 Ω to 147.9 Ω
• Output: 0.1 V to 4.9 V
The design goals and performance are summarized in Table 1. Figure 15 depicts the measured transfer function
of the design.
Table 1. Comparison of Design Goals, Calculations, Simulation, and Measured Performance
VOUT
RTD
GOAL
CALCULATED
SIMULATED
MEASURED
VOUT maximum scale
80.3 Ω
0.1 V
0.112 V
0.117 V
0.11 3 V
VOUT minimum scale
142.9 Ω
4.9 V
4.83 V
4.82 V
4.862 V
8.2.2 Detailed Design Procedure
Figure 12 and Figure 13 shows the schematic of the RTD amplifier for minimum and maximum output conditions.
This circuit was designed for a –50°C to 150°C RTD temperature range. At –50°C the RTD resistance is 80.3 Ω
and the voltage across it is 8.03 mV (VRTD = (100 μA) (80.3 Ω), see Figure 2). Notice that R3 develops a voltage
drop that opposes the RTD drop. The drop across R3 is used to shift amplifiers input differential voltage to a
minimum level. The output is the differential input multiplied by the gain (Vout = 698 ∙ 160 μV = 0.111 V). At
150°C, the RTD resistance is 148 Ω and the voltage across it is 14. 8 mV (VRTD = (100 μA × 148 Ω ). This
produces a differential input of 6.93 mV and an output voltage of 4.84 V (VOUT = 698 ∙ 6.93 mV = 4.84 V , see
Figure 13). For more detailed design procedures and results, refer to the reference guide, RTD to Voltage
Reference Design Using Instrumentation Amplifier and Current Reference (TIDU969).
+5V
REF200
+
+
8.03mV
R3 78.7
- 7.87mV +
+
160µ V
-
R1 2k
80.3Ÿ@
-50C
RTD
3 Wire
RTD
+5V
INA326
VOUT
0.111V
R1
R1
-
G = 2(R2/R1)
200µA
C2 220p
100µA
R2 698k
100µA
Figure 12. RTD Amplifier with Minimum Output Condition
10
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+5V
REF200
100µA
+5V
3 Wire
RTD
VOUT
4.84V
R1
R1
-
R2 698k
- 7.87mV +
+
6.93mV
-
R1 2k
+
14.8mV
R3 78.7
RTD
148Ÿ@
150C
INA326
+
G = 2(R2/R1)
200µA
C2 220p
100µA
Figure 13. RTD Amplifier with Maximum Output Condition
8.2.2.1 Lead Resistance Cancelation (3-Wire RTD)
Figure 14 shows the 3-wire RTD configuration can be used to cancel lead resistance. The resistance in each
lead must be equal to cancel the error. Also, the two current sources in the REF200 must be equal. Notice that
the voltage developed on the two top leads of the RTD are equal and opposite polarity so that the amplifiers
input is only from the RTD voltage. In this example, the RTD drop is 14.8 mV and the leads each have 1 mV.
Notice that the 1 mV drops cancel. Finally, notice that the voltage on the 3rd lead (2 mV) creates a small shift in
the common mode voltage. In some applications, a larger resistor is intentionally added to shift the commonmode voltage. However, the INA326 has a rail-to-rail common mode range, so it can accept common-mode
voltages near ground.
+5V
REF200
Large Lead R
100µA
100µA
+5V
300m
R1
VOUT
R1
4.84V
-
- 1mV+
10Ÿ
C2 220p
+
14.8mV
R3 78.7
R2 698k
148Ÿ@
150C
3 Wire
RTD
-1mV+
+
14.8mV
10Ÿ
INA326
+
R1 2k
RTD
10Ÿ
+2mVPCB
Figure 14. 3-Wire RTD Configuration Cancels Lead Resistance
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8.2.3 Application Curves
0.7
5.0
4.5
0.6
4.0
Output Error (%)
Vout (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.4
0.3
0.2
Error (0 Ÿ
0.1
0.5
Error (10 Ÿ
0.0
0.0
80
90
100
110
120
130
140
80
150
RTD Resistance
100
120
140
RTD Resistance (Ÿ)
C001
160
C002
Figure 16. Measured Error vs RTD Resistance
Figure 15. RTD to Vout Transfer Function
8.3 System Examples
NOTE: All diodes = 1N4148.
D1
D3
100µA
Bidirectional
Current Source
D1
Bidirectional
Current Source
100µA
100µA
D4
(a)
D2
D2
(b)
(c)
(d)
Figure 17. Reverse Voltage Protection
+VS
100µA
IOUT
5
In
4
Out
50µA
Mirror
Com
3
100µA
–VS
Figure 18. 50-µA Current Source
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System Examples (continued)
300µA
200µA
100µA
100µA
100µA
5
In
100µA
400µA
100µA
100µA
4
Out
5
In
Mirror
Mirror
Com
3
Com
3
Compliance = 4V
(a)
4
Out
Compliance = 4V
(b)
(c)
Figure 19. 200-µA, 300-µA, and 400-µA Floating Current Sources
Compliance to
Ground
+VS
50 µA
+VS
Compliance to
–VS + 5 V
100 µA
Compliance to
–VS + 5.1 V
27 kΩ
50 µA
5
In
4
Out
5
In
Mirror
Com
3
4
Out
50 µA
5
In
Mirror
Mirror
Com
3
0.01 µF
100 µA
4
Out
Com
3
5.1 V
1N4689
100 kΩ
100 µA
100 µA
–VS
–VS
(a)
–VS
(b)
(c)
Figure 20. 50-µA Current Sinks
SERIES-CONNECTED CURRENT SOURCES
CURRENT vs APPLIED VOLTAGE
+VS
101
High
100µA
100µA
100µA/200µA
5
In
Current (µA)
100µA
100µA
Low
100
4
Out
Mirror
99
Com
3
0
10
20
30
40
50
60
70
80
Applied Voltage (V)
Compliance to –VS + 1.5V
–VS
Provides 2X Higher Compliance Voltage
Figure 21. Improved Low-Voltage Compliance
Figure 22. 100-µA Current Source—80-V Compliance
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System Examples (continued)
+VS
+VS
100µA
0.01µF
L
o
a
d
5.1V
1N4689
100µA
–VS
(a) Compliance approximate
to Gnd. HV compliance
limited by FET breakdown.
(b) Compliance to +VS – 5V.
L
o
a
d
27kΩ
High
L
o
a
d
100µA
+VS
–VS
100µA
33kΩ
1N4148
1N4148
–VS
100µA
40kΩ
0.01µF
40kΩ
100µA
(c)
0.01µF
±
0.01µF
40kΩ
±
0.01µF
100µA
Low
1N4148
(d) Floating 200µA cascoded
current source.
40kΩ
100µA
1N4148
(e) Bidirectional 200µA
cascoded current source.
NOTES: (1) FET cascoded current sources offer improved output impedance and high frequency operation. Circuit in (b)
also provides improved PSRR. (2) For current sinks (Circuits (a) and (b) only), invert circuits and use “N” channel JFETS.
Figure 23. FET Cascode Circuits
14
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System Examples (continued)
®
Using Standard Potentiometer
+VS
Using Bourns Op Amp Trimpot
+VS
VIN
VIN
RA
RB
RA
100µA
RB
100µA
VOUT
VOUT
Op Amp
Op Amp
51Ω
To
Other
Amps
(1)
To
Other
Amps
2kΩ Linear
(1)
100Ω
®
Bourns Trimpot
51Ω
100µA
100µA
VOUT = VIN (–R B /RA )
Offset Adjustment Range = ±5mV
–VS
VOUT = –VIN (R B /RA )
Offset Adjustment Range = ±5mV
–VS
NOTE: (1) For N Op Amps, use Potentiometer Resistance = N • 100Ω.
Figure 24. Operational Amplifier Offset Adjustment Circuits
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System Examples (continued)
R2
+VS
100 µA
NOTE: (1) OPA602 or OPA128
0.01 µF
EXAMPLES
(1)
I OUT = N • 100 µA
R1
(N • R2 )
R1
R2
IOUT
100 Ω
10 kΩ
10 kΩ
10 MΩ
1 MΩ
1 kΩ
1 nA
1 μA
1 mA
Use OPA128
R1
(N • R 2 )
I OUT = N • 100 µA
(1)
0.01 µF
100 µA
R2
–VS
(a)
(b)
FEATURES:
(1) Zero volts shunt compliance.
(2) Adjustable only to values above
reference value.
NOTE:
Current source/sink swing to the
Load Return rail is limited only
by the op amp's input common
mode range and output swing
capability. Voltage drop across R
can be tailored for any amplifier to
allow swing to zero volts from rail.
+VS
100 µA
OPA602
NR
R
NR
0.01 µF
EXAMPLES
R
0.01 µF
IO = (N +1) 100 µA
NR
1 kΩ
1 kΩ
100 kΩ
R
IOUT
OPA602
4 kΩ 500 μA
9 kΩ
1 mA
9.9 kΩ 10 mA
100 µA
Reference
IO = (N +1) 100 µA
–VS
(c)
(d)
IO = (N +1) 100 µA
100 µA
OPA602
IO = 100 μA (N + 1). Compliance » 3.5 V
with 0.1 V across R. Max IO limited by FET.
For IO = 1 A, R = 0.1 Ω, NR = 1 kΩ.
10 pF
0.01 µF
R
NR
(e)
Figure 25. Adjustable Current Sources
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System Examples (continued)
INA110
Instrumentation Amplifier
ROFFSET
Cable Shield
RTD
VOUT = Gain • 200 µA • Δ RTD
200-µA
Reference
Current
200-µA
Compensation
Current
+VS
8
6
7
5
I
A
B
1
2
O
C
3
REF200
4
–VS
Figure 26. RTD Excitation With Three-Wire Lead Resistance Compensation
2 Vp-p
Triangle Output
C
OPA602
Square Output
2 Vp-p
R
10 kΩ
Frequency = 1/4RC (Hz)
Frequency = 25/C (Hz)
(C is in µF and R = 10 kΩ)
1N4148
1N4148
Bidirectional
Current Source
1/2
REF200
1N4148
1N4148
Figure 27. Precision Triangle Waveform Generator
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System Examples (continued)
100 NŸ
VIN
¦10 V ” VIN ”10 V
C
(1)
100 µA + Bridge
1/4
OPA404
1/4
OPA404
1/4
OPA404
12 Vp-p
Duty Cycle Out
(1)
VIN = 10 V: 100% Duty Cycle
VIN = 0 V: 50% Duty Cycle
VIN = ±10 V: 0% Duty Cycle
(1)
100 µA + Bridge
60 k
See Figure 27.
Figure 28. Precision Duty-Cycle Modulator
For current source,
invert circuitry and
use P-Channel FET.
IOUT
Siliconix
J109
0.1 µF
50kΩ
100 µA
–15 V
Figure 29. Low Noise Current Sink
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System Examples (continued)
IOUT
For current source,
invert circuitry and
use P-Channel FET.
50 kΩ
0.1 µF
Siliconix
J109
0.1 µF
50 kΩ
100 µA
100 µA
–15 V
Figure 30. Low Noise Current Sink With Compliance Below Ground
High
300 µA
0.01 µF
20 kΩ
100 µA
High
400 µA
100 µA
2N5116
0.01 µF
20 kΩ
100 µA
2N5116
2N4340
0.01 µF
2N4340
27 kΩ
5
In
4
Out
5
In
100 µA
Mirror
Com
3
4
Out
Mirror
Com
3
300 µA
Low
400 µA
Low
(a) Regulation (15 V to 30 V = 0.00003%/V (10 GW)
(a) Regulation (15 V to 30 V = 0.000025%/V (10 GW)
Figure 31. Floating 300-µA and 400-µA Cascoded Current Sources
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System Examples (continued)
+VS
100 µA
10 kΩ
C
10 kΩ
VI
VO = –VI
OPA602
Diodes: 1N4148
or PWS740-3
Diode Bridge for
reduced VOS .
VO Rate Limit = 100 µA/C
100 µA
–VS
Figure 32. Rate Limiter
High
Compliance
4 V to 30 V
25 mA
100 Ω
100 μA
100 Ω
+VS
100 Ω
–VS
100 Ω
10 kΩ
40.2 Ω
Low
NOTE: Each amplifier 1/4 LM324
Op amp power supplies are derived
within the circuitry, and this quiescent
current is included in the 25 mA.
Figure 33. 25-mA Floating Current Source
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System Examples (continued)
+15 V
VO
100 µA
R
(50 kΩ)
+10
R
(50 kΩ)
VI
+5
1N4148
–10
–5
+5
+10
VI
10 pF
–5
1N4148
For VI > –5 V: VO = 0
For VI < –5 V: VO = –VI – 5 V
(Dead to 100 µA • R)
VO
OPA602
–10
R
(50 kΩ)
R
(50 kΩ)
VO
+10
VI
1N4148
+5
–10
100 µA
–5
+5
+10
VI
10 pF
1N4148
–15 V
OPA602
VO
–5
–10
For VI < 5 V: VO = 0
For VI > 5 V: VO = 5 V – VI
(Dead to –100 µA • R)
Figure 34. Dead-Band Circuit
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System Examples (continued)
+15 V
VO
+10
100 µA
R
(50 kΩ)
R
(50 kΩ)
+5
–10
1N4148
–5
+5
+10
VI
–5
10 pF
10 kΩ
1N4148
OPA602
–10
For VI > 5 V: VO = VI – 5 V
For VI < –5 V: VO = VI + 5 V
(Dead to ±100 µA • R)
10 kΩ
VI
10 kΩ
VO
OPA602
R
(50 kΩ)
R
(50 kΩ)
1N4148
100 µA
10 pF
1N4148
–15 V
OPA602
Figure 35. Double Dead-Band Circuit
+VS
100 µA
VO = 100 µV
1Ω
Figure 36. Low-Voltage Reference
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System Examples (continued)
+VS
100 µA
OPA602
0.01 µF
VO = 1 V
10 kΩ
Figure 37. Voltage Reference
VO
+10
+7.5 V (R = 75 kΩ)
1 kΩ
+5 V (R = 50 kΩ)
+5
100 µF
+2.5 V (R = 25 kΩ)
VO
OPA121
–10
+5
–5
+10
VI
OPA121
VI
(1)
100 µA
with bridge(1)
R
(50 kΩ)
–2.5 V (R = 25 kΩ)
–5
VO = VI (–5 V < VI < 5 V)
VO = 5 V (VI > 5 V)
VO = –5 V (VI < –5 V)
(Bound = 100 µA • R)
+5 V (R = 50 kΩ)
+7.5 V (R = 75 kΩ)
–10
See Figure 17.
Figure 38. Bipolar Limiting Circuit
VO
1 kΩ
+10
+7.5 V (R = 75 kΩ)
100 µF
1N4148
+5 V (R = 50 kΩ)
+5
OPA121
+2.5 V (R = 25 kΩ)
VO
–10
OPA121
–5
+5
+10
VI
VI
100 µA
R
(50 kΩ)
VO = V I (V I < 5 V)
VO = 5 V (VI > 5 V)
(VLIMIT = 100 µA • R)
–5
–10
Figure 39. Limiting Circuit
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System Examples (continued)
+VS
+5V
100µA
VO
1kΩ
The
Window
5V
1/2
LM393
0
–VW
+VW
VI
VCENTER (2)
0.01µF
R(3)
(1)
–VW , +VW = 100µA • R
VCENTER(2)
VO
0.01µF
R(3)
(1)
1/2
LM393
VI
100µA
–VS
NOTES: (1) Capacitors optional to reduce noise and switching time.
(2) Programs center of threshold voltage. (3) Programs window voltage.
Figure 40. Window Comparator
+VS
100µA
100µA
1/2
OPA1013
1/2
OPA1013
PMI
MAT03
+In
–In
–VS
INA105
VO = +In – (–In)
Figure 41. Instrumentation Amplifier With Compliance to –VS
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9 Power Supply Recommendations
The REF200 device has completely floating current sources and current mirror. The REF200 device has a wide
compliance voltage range from 2.5 V to 40 V.
10 Layout
10.1 Layout Guidelines
Figure 42 illustrates an example of a printed-circuit-board (PCB) layout for a data acquisition system using the
REF2030. Some key considerations are:
•
•
•
•
Minimize trace lengths in the current source and current mirror paths to reduce impedance.
Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic errors
(such as the Seebeck effect) from occurring.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when absolutely necessary.
10.2 Layout Example
VSUPPLY
GND
C
REF200
To RTD
R
R
To INA
R
Figure 42. Example Layout of REF200 in a RTD Measurement System
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
•
•
RTD to Voltage Reference Design Using Instrumentation Amplifier and Current Reference, TIDU969
Implementation and Applications of Current Sources and Current Receivers, SBOA046
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
REF200AU
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
REF
200U
REF200AU/2K5
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
REF
200U
REF200AU/2K5E4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
REF
200U
REF200AUE4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
REF
200U
REF200AUG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-25 to 85
REF
200U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
REF200AU/2K5
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
REF200AU/2K5
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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