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2012 IC Design Contest
Analog Circuit Category
Switched-Capacitor Voltage Doubler
I. General Descriptions:
In this contest, the design is a “switched-capacitor voltage doubler (SCVD)”, which
accomplishes energy transfer and voltage conversion using capacitors. The switchedcapacitor voltage converters include the voltage inverter and the voltage doubler circuit.
In the voltage inverter, the charge pump capacitor, CD, is charged to the input voltage
during the first half of the switching cycle. During the second half of the switching cycle,
its voltage is inverted and applied to capacitor CO and the load RL. The switching
frequency impacts the size of the external capacitors required, and higher switching
frequencies allow the use of smaller capacitors. The duty cycle, defined as the ratio of
charging time for CD to the entire switching cycle time, is usually 50% for yielding the
optimal charge transfer efficiency. The detail circuits are shown in Fig-1 to Fig-5
respectively.
External
Device
Vx
Vin
CD Vy
Charge Pump
Vn1
Vp1
Vn2
Vp2
Vout
CO
RL
Vn1
Vp1
Voltage
Translator
CLK1
CLK
Voltage
Translator
External
Devices
CLK2
Non-Overlapping
Clock Generator
Vn2
Vp2
Fig-1: Switched-capacitor voltage doubler
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Vin
Vn2
Vx
Vp1
CD
Vy
Vn1
Vp2
Vout
CO
RL
External
Devices
Fig-2: Charge pump circuit
Vout
Fig-3: Driver circuit
VDD
CKOp
CKOn
CKin
Fig-4: Voltage translator circuit
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CLK
CLK1
CLK2
Fig-5: Non-overlap clock generator
II. Design Specifications:
1. Please use CIC 0.18um 1.8V 1P6M CMOS virtual process to design the whole circuit. The
final results should include the netlist, layout and all the verification files (DRC and LVS
reports).
2. Please be noted: Use 3.3-V devices for all designs. Anyone who violates this requirement
will be disqualified during the grading.
3. Supply voltage (VDD) is 1.8V and no negative bias source is allowed in your design.
4. Input clock signal is 50KHz with 50% duty cycle and 1.8V peak voltage (please refer to the
test bench).
5. Charge pump capacitor CD is 1.0uF, output capacitor CO is 2.2uF and loading RL is 200Ω.
6. Beside the above requirements, the post-layout simulation (for speeding up the simulation
time, only do the C+CC extraction) results of this SCVD circuit should also meet the
following acceptance specifications under the typical transistor parameters (TT corner):
 Stable output voltage: larger than 3.0V after 500us
 Area: smaller than 60,000um2 (including ALL transistors. CD, CO and RL are external
components)
 Efficiency (defined in the testbench): larger than 85%
III. Scoring:
1. Acceptance criteria: Finish layout without any DRC/LVS error and the post-layout
simulation results of your design meet all specifications described in section II item 6.
2. Ranking method: Satisfying the acceptance criteria is the basic requirement. The ranking
is based on the efficiency. Higher efficiency means the better ranking.
3. Please be noted: If any of the acceptance criteria is not satisfied, the ranking will be
affected even if his/her efficiency is higher than other teams who satisfy all the
specifications but with lower efficiency.
4. The principle of scoring is based on the complete design in the contest. However, even
though your design cannot be finished in time, CIC allows the designers to upload their
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results before the deadline of the contest. If the number of teams with “complete design”
is less than the number of awards, the incomplete designs might be granted.
IV. The following rules should be followed
EDA Tools:
1. Simulation: HSPICE 2010.12-SP2
2. Layout: Virtuoso IC5141 or Laker L3
3. Verification: Calibre 2010.4_26.16 for DRC, LVS and PEX.
Others:
1. CIC will provide the unified test bench to consist the scoring criteria.
2. Netlist file naming: the subckt name of the netlist file should be “scdb.spi”, the top cell
should be named as “scdb”, and output node is Vout. Vin is a 1.8-Volt DC input. Supply
power is “Vdd” and ground is “Vss”. Please be noted that the total seven nodes of “scdb”
should be the same as the following naming sequence. It is important to follow the port order
in your design files; otherwise it may affect your ranking.
.subckt scdb Vdd Vss Vin CLK Vx Vy Vout
MM1 net1 net2 Vdd Vdd P_33 L=x W=y
…..
…..
.ends
3. GDSII file is named as “scdb.gds” and the top cell name is scdb
4. It’s not necessary to do the antenna check when doing the DRC but other items should be
clean expect the metal density error
5. Calibre LVS result is named as scdb.lvs.report
6. Please tar the “scdb.spi” and “scdb.gds”, name this tar file as “grad_analog.tar” and put it to
the specific directory which will be listed in the other document.
V. Testbench
*2012 IC contest--charge pump
*Testbench file
.LIB 'cic018.l' TT
.INC 'scdb.spi'
**************************************************
*CORE
**************************************************
Xscdb Vdd Vss Vin CLK Vx Vy Vout scdb
**************************************************
*EXTERNAL CAPACITOR & LOAD
**************************************************
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CD
Vx
Vy 1U
CO
Vout Vss 2.2U
RL
Vout Vss 200
**************************************************
*BIAS & INPUT
**************************************************
VDD
Vdd Vss V_SUPPLY
VSS
Vss GND V_GROUND
VIN
Vin Vss V_INPUT
VCLK CLK Vss PUL(0 1.8 0 1U 1U 10U 20U)
**************************************************
*PARAMETER
**************************************************
.PARAM V_SUPPLY = 1.8V
.PARAM V_GROUND = 0.0V
.PARAM V_INPUT = 1.8V
**************************************************
*ANALYSIS
**************************************************
.MEASURE TRAN VDD_AVG AVG V(Vdd) FROM=500u TO=1m
.MEASURE TRAN IDD_AVG AVG I(Vdd) FROM=500u TO=1m
.MEASURE TRAN VIN_AVG AVG V(Vin) FROM=500u TO=1m
.MEASURE TRAN IIN_AVG AVG I(Vin) FROM=500u TO=1m
.MEASURE TRAN VOUT_AVG AVG V(Vout) FROM=500u TO=1m
.MEASURE TRAN IO_AVG
AVG I(RL)
FROM=500u TO=1m
.MEASURE AVGVDDP PARAM='ABS(VDD_AVG*IDD_AVG)'
.MEASURE AVGVINP PARAM='ABS(VIN_AVG*IIN_AVG)'
.MEASURE AVGVOUTP PARAM='ABS(VOUT_AVG*IO_AVG)'
.MEASURE EFF
PARAM='AVGVOUTP/(AVGVDDP+AVGVINP)'
.OP
.OPTION POST
.OPTION PROBE
.TRAN 0.1U 1M
.PROBE TRAN V(Vout) I(RL)
.END
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軟體環境
使用者登入後自動會設定好以下軟體環境：
Vendor
Cadence
Synopsys
Mentor
Spring Soft
Utility
Tool
Executable
Virtuoso
icfb
Composer
icfb
NC-Verilog
ncverilog
SOC Encounter
encounter
design vision
dv, dc_shell
VCS
vcs
IC compiler
icc_shell -gui
Hspice
hspice
Cosmos Scope
scope
Spice explorer
sx –w , wv
Calibre
calibre
ModelSim
vsim
Laker
laker
Verdi
verdi, nWave, nLint
vi
vi, vim, gvim
gedit
gedit
nedit
nedit
pdf reader
acroread
calculate
gnome-calculator, bc -l
gcc
gcc
EDA 軟體所須使用的 license 皆已設定完成，不須額外設定，且每隊限定每個軟體
只能使用一套 license。
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Full Custom Related Files
Files location: /usr/cad/icc2012/VP/
Process
Process
Process
c shell
CIC-CIS- 2005-TR01_VP1.pdf
CIC-CIS- 2005-TR01_VP2.pdf
CIC-CIS- 2005-TR01_VP3.pdf
cpall.csh
calibre/
.cdsinit
Calibre_DRC/
rule.drc
Calibre_LVS/
Rule.lvs
Calibre_PEX/
Rule.rce
Rule_08KA.rc
Rule_20KA.rc
model/
cic018.l
laker/
laker.tf
virtuoso/
cic18.tf
display.drf
PNP/
PNP_V50X50.gds
PND_V100X100.gds
Layout Rule
Electrical Design Rule
Device Formation
copy all files to home
virtuoso initial file for calibre
Calibre DRC rule file
Calibre LVS rule file
Calibre LPE rule file
Calibre LPE rule file
Calibre LPE rule file
SPICE model
Laker technology file
Virtuoso technology file
Virtuoso display file
BJT Example layout
BJT Example layout
若需在 virtuoso 中呼叫 calibre，請將 calibre/.cdsinit 複製到自己的 home directory。
若不知道如何複製檔案，可執行 /usr/cad/icc2012/VP/cpall.csh，這個 csh 檔會將所
有製程資料複製到您的 home 目錄。
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