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Voltage Buffer Compensation using Flipped Voltage Follower in a Two-Stage CMOS Op-amp Sri Harsh Pakala, Mahender Manda, Punith R. Surkanti, Annajirao Garimella and Paul M. Furth VLSI Laboratory, Klipsch School of Electrical and Computer Engineering New Mexico State University, Las Cruces, NM 88003, USA. Email: [email protected] Abstract—In Miller and current buffer compensation techniques, the compensation capacitor often loads the output node. If a voltage buffer is used in feedback, the compensation capacitor obviates the loading on the output node. In this paper, we introduce an implementation of a voltage buffer compensation using a Flipped Voltage Follower (FVF) for stabilizing a two-stage CMOS op-amp. The op-amps are implemented in a 180-nm CMOS process with a power supply of 1.8V while operating with a quiescent current of 110µA. Results indicate that the proposed voltage buffer compensation using FVF improves the Unity Gain Frequency from 5.5MHz to 12.2MHz compared to Miller compensation. Also, the proposed technique enhances the transient response while lowering the compensation capacitance by 47% and 17.7% compared to Miller and common-drain compensation topologies. Utilization of FVF or its variants as a voltage buffer in a feedback compensation network has wide potential applications in the analog design space. Index Terms—Flipped voltage follower, frequency compensation, CMOS op-amps, voltage buffers, current buffers. I. INTRODUCTION Miller [1], cascode [2], nested Miller (NM) and reversenested Miller (RNM) compensation schemes are the most widely used techniques to stabilize multi-stage amplifiers [3][21]. These compensation techniques are generally robust and offer advantages such as: (i) pole splitting, (ii) Left-Half-Plane (LHP) zero creation and its accurate placement through a nulling resistor and (iii), in the case of cascode compensation, eliminating the feed-forward path due to the presence of a current buffer, which is usually implemented with a commongate transistor [5]-[14]. These techniques typically exhibit one inherent disadvantage, in which the compensation capacitor loads the output node. For example, Miller compensation between input node X and output node Y of the gain stage shown in Fig. 1(a) loads the output with the compensation capacitor, as node X is approximately an AC ground compared to node Y. For stabilizing an op-amp designed specifically for high-speed applications, it is immensely important to reduce the loading effect on the output in order to achieve a fast and stable transient response. Buffers introduced in the compensation path do not affect the gain, but assist in reducing the loading effect on the output node. These buffers in compensation path eliminate the feed-forward path and generate LHP zeros. A current buffer (CB) when introduced in feedback compensation network as shown in Fig. 1(b) can be very effective due to its low input impedance, represented by ri_CB. While the utilization of the low-impedance node as a compen- Fig. 1. Figure illustrating the loading of compensating capacitance on output node Y in case of (a) Miller compensation with nulling resistor and (b) current buffer. In case of (c) voltage buffer, compensating capacitance doesn’t load the output node Y. -sating node in compensation schemes using CBs helps in reducing the size of compensating capacitor CCB that is required to ensure a stable system, the output node Y is still loaded by CCB. Fig. 1(c) shows a voltage buffer (VB) introduced in the feedback compensation path between node Y and X in series with capacitance CVB. The elimination of a direct connection of CVB to the output improves the transient response. The low impedance node at the output of the VB provides an additional advantage of establishing effective feedback [11], [22]-[23]. Thus a VB with very low output impedance r0_VB is preferred. Practical VBs can be implemented using a common-drain (CD) transistor. This paper introduces a VB compensation using a variant of the flipped voltage follower (FVF). In many applications, FVFs exhibit enhanced performance compared to a regular CD topology because of their very low output impedance [24]. In Section II, VB circuit topologies are analyzed and compared. Section III outlines the implementation details of the proposed compensation technique. Section IV presents the simulation results of Miller, CD and the proposed FVF compensation schemes. Section V illustrates the benefits of the FVF configuration over Miller and CD compensation schemes. Conclusions are presented in Section VI. II. VOLTAGE BUFFERS This section describes the implementation of different types of VBs suitable for compensation networks. A. Common-Drain Topology: The PMOS version of CD amplifier is shown in Fig. 2(a). Input VIN is applied to the PMOS CD transistor MCD, while the VDD VDD I CD VDD M2 VOUT VIN MCD gmCD 2IFVF VOUT VIN MFVF gmFVF VIN M FFVF gmFFVF VOUT M2 I FVF VSS (a) VSS (b) IFVF VSS (c) Fig. 2. Voltage buffer topologies (a) common-drain, (b) fllipped voltage follower and (c) folded flipped voltage follower stages. output VOUT is taken at its source terminal. Since the bias current ICD is always constant, the sourcee-to-gate voltage VSG,CD of MCD is also fixed. Therefore, aany small-signal change in the input will be directly followed by the output in order to keep VSG,CD constant. Since the output is always one VSG higheer than the input, the range of the input is {VSS, VDD – VSAT,ICDD – VSG,CD}. The input impedance looking into gate of CD is vvery high and the output impedance is 1/gmCD. The CD VB hhas high current sinking capability, whereas its sourcing capaability is limited by bias current ICD. B. Flipped Voltage Follower: The schematic of a PMOS version of FVF [24] is shown in Fig. 2(b). FVF consists of PMOS input transistor MFVF, transistor M2 with shunt feedback and bias ccurrent IFVF. FVF has high current sourcing but limited current sinking capability. The internal feedback loop helps in reducing the output impedance 1/gmFVF of the control transsistor by the loop gain gm2r0FVF. Therefore, the FVF output impeedance is 1 (1) . ROUT = (g m 2 r0 FVF ) g mFVF Although FVF exhibits ultra-low output impeedance, it suffers from limited operating voltage range. The inpput voltage range is limited by feedback transistor M2 and is given by VDD − VSG , M 2 + VSD , MFVF − VSG , MFVF ≤ VIN , FVF ≤ VDD − VSD , M 2 − VSG , MFVF . (2) Because of its low input range less than |VTHHP|, FVF may not be suitable for VB compensation. C. Folded Flipped Voltage Follower: The folded flipped voltage follower (F FFVF) [24] has ultra-low output impedance and doesn’t sufffer from limited operating voltage range. The PMOS version of FFVF, shown in Fig. 2(c), consists of PMOS input transsistor MFFVF and NMOS feedback transistor M2. In order tto eliminate the voltage clamping issue as in FVF, the feedbback transistor is folded. This doubles the bias current requirred to 2IFVF, but helps in obtaining a voltage range similar to a CD stage. The input range of FFVF is given by VSS + VGS , M 2 + VSD , MFFVF − VSG , MFFVF ≤ VIN , FFVF ≤ VDD − VSAT , 2 IFVF − VSG , MFFVF . (3) From Fig. 3, we note that the FFVF has sim milar input-output ranges compared to CD. On the other hhand, the output resistance of the FFVF is approximately 25x loower than that of CD, as seen in Fig. 4. Hence, the FFVF is an ideal candidate to implement in VB compensation. Fig. 3. Input-output characteristic of CD and d FFVF topologies. Fig. 4. Output impedance characteristic of CD and FFVF topologies. III. PROPOSED VOLTAGE BUFFER COMPENSATION USING FOLDED FLIPPED VOLTA AGE FOLLOWER Fig. 5 depicts the schematic off a two-stage op-amp with Miller, CD and FFVF compensation n techniques. The first stage is a PMOS differential pair with an NMOS current mirror load (M1- M5), while the second stage is a common-source amplifier (M6- M7). The output stage is sized K times larger in width than the unit sized tail PMOS transistor in the first stage and hence biased with K IBIAS. p-amp is given by The DC gain of the two-stage op (4) Av = g m1 R1 g m 2 ROUT , O where gm1 and gm2 are the effectivee transconductances of the first and second stages, respectively. R1 and ROUT are defined as the lumped resistances at the outp put of the first stage V1 and op-amp output VOUT, respectively. Three T variants of two-stage op-amps are implemented using the following feedback compensation networks: (i) Miller (ii) CD (iii) FFVF. Miller compensation network, formed fo by capacitor CM and nulling resistor RM, is placed betweeen nodes V1 and VOUT. CD compensation network is implemen nted through an additional branch biased with current ICD forrmed by transistors M8-M9, compensation capacitor CCD and d resistor RCD connected between node V1 and source of CD transistor M9 at node VX,CD. The proposed FFVF compensation n network is implemented through the addition of a FFVF brranch M10-M13, with a bias current of 2IFVF. Compensation caapacitor CFFVF and resistor RFFVF are connected between nodes V1 and VX,FFVF. Resistors RCD and RFFVF can be optionally used to move LHP zero formed by the VBs to desired domin nant frequencies [21], [25]. Both CD and FFVF compen nsation schemes require a nominal Miller capacitor CM and nu ulling resistor RM connected to node V1 in parallel, in order to sttabilize the op-amps over a wide range of load resistor RL and capacitor CL. Though an VDD VBIAS M5 M11 M8 IBIAS ICD V X,FFVF M1 Vin- gm1 M2 C CD R CD M10 M9 RL gm10 IFVF M4 M13 Mil ler Compensation Input Stage CL CM R M V1 V SS VOUT VX,CD gmCD M3 K IBIAS g mFFVF M12 C FFVF R FFVF Vin+ 2IFVF M6 CD Compensation FFVF Compensation gm2 M7 Outtput Stage Fig. 5. Figure illustrating Millerr, CD and proposed FFVF compensation schemes in a CMOS two-stage op-amp. o additional Miller compensation network is reqquired in parallel with FFVF compensation, the compensatioon path created through low impedance node of transistor M12 allows the use of a very low-valued Miller capacitor CM. Bothh CD and FFVF compensation schemes require an extra biass current in their respective buffers when compared to Miller. Careful placement of LHP zeros help m maintain adequate phase margin over varying load condition. The LHP zeros generated by CD and FFVF compensation schhemes are: 1 (5) ω Z ,CD = ⎛ 1 ⎞ ⎜ + RCD ⎟ CCD ⎜ g m,CD ⎟ ⎝ ⎠ ω Z , FFVF = 1 ⎛ 1 ⎜ ⎜ (g ⎝ m10 r0 , FFVF g mFFVF ) + R FFVF ⎞ ⎟ C FFVF ⎟ ⎠ (6) where, gmCD, gmFFVF and gm10 are the transconductances of CD and FFVF input transistors and FFVF feeddback transistor, respectively. r0,FFVF is the output resistance of FFVF input transistor M12. FFVF technique needs lower qquiescent current than CD compensation, such that 2IFVF << ICDD. This is because of the ultra-low output impedance of the FFVF F. IV. Fig. 6 Frequency response of 2-stage op-aamp with Miller, CD and FFVF compensation at RL=20kΩ and CL=25pF. Fig. 7 Frequency response of 2-stage op-aamp with FFVF compensation at different load conditions. SIMULATION RESULTSS The three variants of two-stage op-amps aare designed and simulated in a 180-nm CMOS process. Each op-amp operates with a supply voltage of 1.8V and a quieescent current of 110μA. AC and transient simulations were performed for a load range of RL=20kΩ to 10MΩ and CL=1pF to 100pF. A. AC Analysis: AC analysis was performed on all three vaariants of the opamps. Miller, CD and FFVF compensationn schemes were implemented such that a minimum of 60° phaase margin (PM) and 10dB gain margin (GM) is achieved across all load conditions. Fig. 6 shows the magnitude and phase respponses of Miller, CD and FFVF compensation schemes. The proposed compensation scheme clearly outperforms Miller and achieves similar performance to the CD compensation technique, while utilizing a lower valued compensation capaccitor. Unity gain frequency (UGF) is enhanced from 5.5MHzz in Miller, and 11.7MHz in CD, to 12.2MHz with FFVF technnique. Fig. 7 Fig. 8. Transient responses of Miller, CD an nd FFVF compensated op-amps in inverting configuration. illustrates the stability of the FFV VF-compensated op-amp at three different load conditions. B. Transient Analysis: Transient analysis is performed on op-amps in inverting configuration with unity gain and a rail-to-rail pulse input of frequency 50kHz. Fig. 8 presents th he transient responses of the three op-amps at RL =20kΩ and CL =25pF. CD- and FFVF- compensated op-amps exhibited higher slew-rates than Millercompensated op-amp. V. Table I summarizes the simulated results of the three designed op-amps at a typical load of 25pF||20kΩ. Particular compensation capacitance and buffer quiescent current values allowed for a minimum of 60° phase margin (PM) and 10dB gain margin (GM) across all load conditions, RL =20kΩ to 10MΩ and CL=1pF to 100pF. From Table I, we see that the required compensation capacitance for FFVF is reduced by 47% and 17.7% compared to Miller and CD compensation techniques, respectively. UGF is extended from 5.5MHz in the case of Miller compensation to 11.7MHz and 12.2MHz for CD and FFVF, respectively. Moreover, the current overhead of 2.4µA for the CD scheme is reduced by 50% to 1.2µA in the FFVF technique. VI. CONCLUSION TABLE I SUMMARY RESULTS OF OP-AMP OF FIG. 5 AT RL= 20 KΩ AND CL = 25 PF. Parameter/Design Miller CD FFVF Total IQ (µA) Power Supply (V) Compensation Resistances and Capacitances 110 110 + 2.4 1.8 RM =11kΩ, CM = 0.5pF, RCD =0Ω, CCD =3.1pF 110 + 1.2 RM =8.3kΩ, CM =0.6pF, RFFVF =20.5k, CFFVF =2.4pF 7.5kΩ, 5.6pF 11kΩ, 3.6pF 28.8 kΩ, 3pF 54 94.9° 5.5 1.7/3.3 54 62.9° 11.7 2.1/6.8 54 71.2° 12.2 2.1/7.2 RM =7.5kΩ, CM =5.6pF [7] [8] [9] [10] [11] [12] Voltage buffer compensation using a folded flipped voltage follower is introduced and implemented in a two-stage CMOS op-amp. Three op-amps were implemented such that the proposed scheme can be compared to Miller and commondrain compensation networks. By isolating the compensation node through a voltage buffer implemented by a flipped voltage follower, several advantages can be gained such as: lower compensation capacitor, higher UGF and improved transient response. Utilization of flipped voltage follower or its variants in a feedback compensation network has wide potential applications in the analog design space. Total Compensation Resistance and Capacitance AV (dB) Phase Margin UGF (MHz) SR+/SR- (V/µs) [6] DISCUSSION [13] [14] [15] [16] [17] [18] [19] [20] REFERENCES [1] [2] [3] [4] [5] J. M. Miller, “Dependence of the input impedance of a three-electrode vacuum tube upon the load in the plate circuit,” Scientific Papers of the Bureau of Standards, vol. 15, pp. 367-385, 1920. B. K. Ahuja, “An improved frequency compensation technique for CMOS operational amplifiers,” IEEE J. of Solid-State Circuits, vol.18, no.6, pp.629-633, Dec. 1983. M. Yavari, et al., “Hybrid Cascode Compensation for two-stage CMOS operational amplifiers,” IEEE International Symposium on Circuits and Systems, ISCAS 2005, vol. 2, pp.1565,1568, 23-26 May 2005. A. D. Grasso, G. Palumbo, S. Pennisi, “Advances in Reversed Nested Miller Compensation,” IEEE Tran. on Circuits and Systems I: Regular Papers, vol.54, no.7,pp.1459-1470, July 2007. F. You, S. H. K. Embabi, E. Sanchez-Sinencio, “A multistage amplifier topology with nested Gm-C compensation for low-voltage application,” [21] [22] [23] [24] [25] 43rd ISSCC IEEE International Solid-State Circuits Conference, 1997, pp.348-349, Feb. 1997. K. N. Leung and P. K. T. Mok, “Nested Miller compensation in lowpower CMOS design,” IEEE Trans. on Circuits and Systems II, vol.48, no.4, pp.388-394, Apr 2001. K. N. Leung and P.K.T. Mok, “Analysis of multistage amplifierfrequency compensation,” IEEE Trans. on Circuits and Systems I:, , vol.48, no.9, pp.1041-1056, Sep 2001. X. Peng, W. Sansen, “AC boosting compensation scheme for low-power multistage amplifiers,” IEEE J. of Solid-State Circuits, vol.39, no.11, pp.2074-2079, Nov. 2004. X. Peng, W.Sansen, “Transconductance with capacitances feedback compensation for multistage amplifiers,” IEEE J. of Solid-State Circuits, vol.40, no.7, pp.1514-1520, July 2005. R. Mita, G. Palumbo, S. Pennisi, “Design guidelines for reversed nested Miller compensation in three-stage amplifiers,” IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing, vol.50, no.5, pp.227-233, May 2003. D. Marano, G. Palumbo, S. Pennisi, “A new advanced RNMC technique with dual-active current and voltage buffers for low-power high-load three-stage amplifiers,” ISCAS 2009., pp.25-28, 24-27 May 2009. P. R. Gray, R. G. Meyer, “MOS operational amplifier design-a tutorial overview,” IEEE Journal of Solid-State Circuits, vol.17, no.6, pp.969982, Dec. 1982. P. J. Hurst, et al. “Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol.51, no.2, pp.275-285, Feb. 2004. G. Rincon-Mora, “Active capacitor multiplier in Miller-compensated circuits,” IEEE J. of Solid-State Circuits, vol.35, no.1, pp.26-32, Jan. 2000. P. M. Furth, S. H. Pakala, A. Garimella, C. Mohan, “A 22dB PSRR enhancement in a two-stage CMOS opamp using tail compensation,” Custom Integrated Circuits Conference, CICC, 2012 IEEE , pp.1-4, 9-12 Sept. 2012. A. Garimella, P. Surkanti, P. M. Furth, “Pole-Zero Analysis of LowDropout (LDO) Regulators: A Tutorial Overview,” 25th International Conference on VLSI Design, VLSID, 2012, pp.31-32, 7-11 Jan. 2012. A. Garimella, P. M. Furth, “Frequency compensation techniques for opamps and LDOs: A tutorial overview,” 2011 IEEE 54th International Midwest Symposium on Circuits and Systems, MWSCAS, pp.1,4, 7-10 Aug. 2011. P. R. Surkanti, A. Garimella, P. M. Furth, “Pole-zero analysis of multistage amplifiers: A tutorial overview,” 2011 IEEE 54th International Midwest Symposium on Circuits and Systems, MWSCAS, pp.1,4, 7-10 Aug. 2011. A. Garimella, M. W. Rashid, P. M. Furth, “Nested Miller compensation using current buffers for multi-stage amplifiers,” 2011 IEEE 54th International Midwest Symposium on Circuits and Systems, MWSCAS, pp. 1-4, 7-10 Aug. 2011. A. Garimella, M. W. Rashid, P. M. Furth, “Single Miller compensation using inverting current buffer for multi-stage amplifiers,” 2010 IEEE International Symposium on Circuits and Systems, ISCAS, pp.15791582, May 30 2010-June 2 2010. A. Garimella, M. W. Rashid, P. M. Furth, “Reverse Nested Miller Compensation Using Current Buffers in a Three-Stage LDO,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.4, pp.250-254, April 2010. G. A. Rincon-Mora, “Analog IC Design with Low-Dropout Regulators (LDOs)”, McGraw Hill Professional, Mar 2009. R. J. Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition. R. G. Carvajal, et al., “The flipped voltage follower: a useful cell for low-voltage low-power circuit design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.52, no.7, pp.1276-1291, July 2005. A. Garimella and P. M. Furth, Eds, “High Performance Analog and Power Management Circuit Design Techniques for Modern SoCs,” Springer AG, manuscript in preparation.