Download Voltage Line Conditioner

Federal University of Santa Catarina - UFSC
Post-graduation in Electrical Engineering - PPGEEL
Power Electronics Institute - INEP
Master Thesis Presentation:
Study and Design of a Voltage Line Conditioner
with Serial Compensation and Fed by Load Side
Eng. MSc Thiago Batista Soeiro
July, 2007
Presentation Contents
• Introduction
• Voltage Line Conditioner: Power Stage
• Voltage Line Conditioner: Control Stage
• Experimental Results
• Conclusions
Motivations
1- The increase of voltage-sensitive equipments results in greater
demand for high-quality voltage sources;
2- The existence of standards limiting the harmonic pollution in
electric power system;
3- To aid the national industries in the development of high-quality
voltage sources.
Main Objectives
1- To study concepts and topologies of voltage line conditioners;
2- To establish general voltage compensation methods to be applied
in voltage line conditioners;
3- To evaluate the performance of the topology proposed under
unbalanced and distorted system voltages;
4- To study and formulate control techniques to provide the
conditioning of the load voltage
5- To develop and test a voltage line conditioner prototype to
validate the analysis.
Important Concepts
io
The Studied Topology was based on two

concepts:
• The Principle of Serial Voltage
Compensation, applied in Stabilizers in
1950 by Patchett
ZL
d
 vri 
vi
vo  vi , io , d 


vr
Lo
Rectifier
S1
S2
S3

• Indirect ac-ac Converter with
Direct link presented by BongHwan Kwon in 2002

vri
vri

S5
S7
a
S4
S6
b
S8
Inverter
 vds
vdp
Co

Important Concepts
The Voltage Line Conditioner Operation Principle:
vi


vds

vds  vdsF  vdsH
vo

io  iF  iH
ZS
vi  vF  vH
vo
vi
 vri 
Voltage Line Conditioner:
Power Stage

vds
LS  Lds

T1
io

vi
Lo

S5
iLo
S7
+
S3
S1
b vr
a
S6
S8
-
Co
S4
vo
S2


Inverter
Rectifier
Modulation Strategy
v0 (t )
PWM Inverter (S5 - S8)
S1,4 (t )
vSrr
v Srr
S 2,3 (t )
v ref
vr (t)
0
Tr
2
Tr
Bidirectional Rectifier (S1 - S4)
t
S
5,6
S
7,8
vab
0
Tr
2
Tr
t
Main Waveforms
Adding voltage
vi
vo
3 Level PWM Modulation
Subtracting voltage
Rectifier input voltage
Rectifier input voltage
vg1,4
vg 2,3
vr
Rectifier
vc
vab
Inverter
0
vds
d
Ts
2
Ts
2
vo
vi
t
0

2
t
0

2
Main Analytical Expression
N
g t  
N  d (t )
1
N   d t 

I Leq 
VCo 
Converter’s Static Gain
Transformation ratio
V0  d  t   1  d  t  
2  N  f s  Leq
I Leq   N  d  t  
16  N  f S  Co

Current ripple
I o 2  d  t   1  d  t  
4  f S  Co  I Leq   N  d  t     N  1
Voltage ripple
Voltage Line Conditioner:
Control Stage
RS
LS
LdP

S5
S7
S6
D7
S3
D 3 S1
D6
S8
C0
D8
S4
D4
S2
S1 S2 S3 S4
S5 S6 S7 S8
Modulador
Cv (s)
Modulador
D2
v0(t)

Sensor
de
Tensão
Comando
vSrr
vSrr

D1
a
b
vi ()
t

D5
Carga
Rede de Energia
T
vo _ ref


Compensador de Tensão
Mathematical Model
• Small signals model:
• G(s), Transfer Function of output voltage vs. duty cycle;
• F(s), Transfer Function of output voltage vs. input voltage .
v0  s   F  s   vi  s   G  s   d  s 
 s  Leq  N 2  Vo
G s 
F s 
vo

d
vo
vi
ZL   N  D
s 2  Leq  Co  N 2 

 Vo   N  D 
s  Leq  N 2
ZL
N   N  D
s 2  Leq  Co  N 2 
s  Leq  N 2
ZL
  N  D
  N  D
2
2
Conditioner Analytical Study
• Load Influence over circuit’s dynamic response:
Conditioner Analytical Study
There are some strategies to damp the voltage oscillation or compensate the
absence of load:
• To damp voltage oscillation with virtual resistance control strategy;
• To insert a control loop to compensate abrupt voltage drop;
• To insert input filter topologies;