Download Dr. Pawan Kumar Singh, Asst. Prof, SRM

Investigation into Enhancing the Gate Electric Field of Transistor
Seema Dahiya, PhD Scholar, SRM University, Delhi-NCR
Dr. Pawan Kumar Singh, Asst. Prof, SRM University, Delhi-NCR
Abstract The use of electronic devices is increasing day by
day in form of static as well as dynamic devices and
simultaneously the energy consumption of these devices is
increasing because of requirement of information processed is
increasing. There is a social need to reduce the power
consumption of these devices. Over four decades the efforts of
minimizing the transistor size for new and minimized products
has introduced new challenges in designing the transistors. As
per the technology roadmap for semiconductors, the reduction in
power consumption of the MOSFETs used in today's electronic
circuits is reaching the fundamental limit and these days new
type of device structures are being investigated as possible
replacements for traditional metal-oxide-semiconductor field
effect transistors (MOSFETs).
Keywords - MOSFET, TFET, FinFET, HTFET, SE-HTFET,
SOI and SCE
I.
INTRODUCTION
The motive behind switching the BJT (Bipolar Junction
Transistor) technology to MOSFET (Metal oxide
Semiconductor Field Effect Transistor) to reduce the power
consumption of each transistor and make the integration as
small as possible. MOSFET technology was a big success for
the electronic industry since last 40 years and it helps a lot for
the reduced area, low power, greater speed, and low cost per
chip. In addition different applications of these electronics
devices, which demand ultra-low power consumption and
prolonged battery lifetime for example radio frequency
identification, portable electronics, implantable biomedical
devices and micro sensors. With the improvements in
packaging and chip area (number of transistors per unit area)
the problems related to power dissipation, cooling techniques,
leakage current, heat removal, and reliability have become a
trade off and therefore the requirements of energy constrained
designed has increased. A number of power reduction
techniques have been adopted by researchers such as supply
voltage scaling, computer aided design techniques for device
sizing and interconnect, switching activity reduction, logic
optimization, architectural techniques of pipelining and
parallelism etc. out of these techniques, the most prominence
approach, which significantly reduces both active and static
components of power, is scaling the supply voltage. One of
the approaches of scaling the device parameters is operating
the transistor in subthreshold region which contributes towards
energy efficiency is implemented as follows.

The conventional transistors were used to operate
between two states either in the strong-inversion (ON
condition) or subthreshold (OFF condition) but the subthreshold transistors operate either in an OFF condition or

a weak-OFF condition (still in sub-threshold regime but
with weak inversion).
Transistors operate on a supply voltage that is less than
the threshold of the transistors which is far below the
conventional operating voltage levels and consequently
the transistors work on subthreshold current.
Minimum energy per operation can be achieved by
operating the transistor in the subthreshold region. A transistor
operating in subthreshold region is good for ultra low power
requirement application like RFID, wireless micro sensors,
biomedical implants.
Following are the probable reasons behind these
optimization requirements. If we do not adopt low power
design then battery size will increase upto 30% to 40% over
next five years
1) Portability - Portable electronic instruments are the main
motivation behind the low power design because they
depend on the battery backup.
2) Lack of efficient battery technology - Battery capacity
has only improved with a factor of 2 to 4 over last 25
years .It is expected battery power time will increase only
90-110watt/kilogram over next five year.
3) Cost of packaging and cooling - Extensive Packaging
and cooling strategies are required as the power
consumption increases. So there are financial advantages
to reduce the power dissipation.
4) Implantable medical electronics
 Pacemaker
 Muscle stimulators
5) Reliability issues
 Electro migration: - It is flow of metal ions under the
influence of high electric current densities
 Every 10 degree rise in temp results double the failure
rate of components
 Power dissipation is increasing twice for every 6.5
years.
II.
APPROACHES BEING USED FOR
IMPROVEMENTS IN PLANER TECHNOLOGY
A. High K Dielectric Approach
The continuous process of scaling down the MOS
transistor has also scaled down the gate oxide, resulting in
development of gate leakage current. The thickness of electric
oxide layer (EOT) has to be reduced to suppress the short
channel effects. To achieve a small EOT a material with high
dielectric constant can be used in comparison to dielectric
constant of SiO2. Fully depleted silicon on insulator has
improved short channel control and subsequently reduces the
requirements for oxide thickness scaling. The interface
between high-K dielectric materials and poly-silicon gate has
following limitations.
a) Direct shoot up in threshold voltage value
b) Photon scattering which degrades the carrier mobility
c) Thermal instability
Fig. 1. MOS Structure with High-K Dielectric
To suppress these limitations, the gate fabricated with
metal is used with the high-K gate insulator. The most
important consideration for the gate electrode is work function
of the material and it must possess the following properties.
a) High thermal requirements
b) Opportunity to choose the work function of gate
c) Redesign the device to get the best combination of work
function and channel doping.
The work function value for gate electrode of depleted
FETs lies near the conduction and valence band. The short
channel effects are controlled by the device geometry but the
threshold voltage is mainly estimated by the gate work
function so selection of gate electrode becomes important.
B. Strained Approach
Fig. 2. Crystal Structure of Strained Technology
In Strain technique mobility of the carriers in MOS
channels is increased for increasing the drive current (i.e. drain
current). The atoms of silicon layer in strained technique are
stretched beyond their normal inter atomic distance. The
thicker gate oxide with lower supply voltage under same drain
current condition reduces the trade-off among short channel
effects, power consumption and current drive. There are
different ways in which the strain can be introduced in a MOS
transistor channel i.e. locally or globally.
 Biaxial Tensile Strain or Global Strain
It is designed by growing thin layer of epitaxial silicon on
material with larger lattice constant, which is responsible for
strain production in silicon lattice. This approach has
following salient features.
a) This technique was helpful in increasing the electron
mobility by 70% even at high electric fields at which the
surface roughness scattering was expected to drive the
mobility.
b) The speed improvement of transistor around 30%.
c) The self-heating due to the lower thermal conductivity of
the thick layer is an issue in this approach, which can be
improved by reducing the layer thickness in the MOS
structure
d) Dislocation defects are controlled in epitaxial layer.
 The Local or Uni-axial Strain
It is developed during the fabrication process of transistor
using tensile capping layer. This layer increases the mobility
of both type of carriers (i.e. Electron as well as Hole), it gives
importance to thermally grown advanced gate oxides on pure
Si as compare to SiGe and standard CMOS process is
promoted with slight modification and low cost.
C. SOI Technology
The SOI structure is created by developing a buried layer
which is formed by the implantation of oxygen ions. For
fabricating the advanced CMOS ICs the silicon on insulator
technology is becoming popular in comparison to silicon
technology because SOI possesses the low supply voltage and
minimum power consumption features.
Fig. 3. SOI MOS Structure
The buried oxide layer provides the dielectric isolation
between active silicon layer and the substrate. A high
resistivity substrate contain reduced parasitic and leakage
current in substrate is used in comparison to previous
substrate. Following are the salient features of SOI
technology.
a) High reliability and high speed is achieved by eliminating
the vertical as well as sidewall capacitances
b) Excellent device isolated structure
c) High drive current
d) Low subthreshold leakage
e) Suffers from self heating effect when the transistor is in
conduction mode
D. MULTIGATE TRANSISTORS
The most advanced inline approach for improving the
energy efficiency and better scalability of MOS ICs is by
introduction of a second gate at the other side of the body of
each transistor called double-gate or tri gate transistor. Which
is a more promising approach for enhancing the performance
and scaling properties of MOS circuits and it is used to
suppress the short channel effects such as threshold voltage
roll off, DIBL and to get the precise control over channel
current. Multigate transistor technique consist two different
approaches
namely
DGMOSFET
and
Tri-Gate
MOSFET/FinFET.
1.
DGMOSFET
Double Gate MOSFET possesses the good control of the
short channel effects and it is getting popularity for transistors
with channel length below 50-nm. A thin silicon channel
sandwiched between two gates provides excellent gate control
over the channel. It provides the high drain current and low
subthreshold leakage for below 50 nm channel length devices.
DG MOSFET with independent gates is in development and it
useful for low power and mixed signal applications.
DGMOSFETs are also explored for subthreshold operations
and are envisaged as suitable due to their near ideal
subthreshold slope and negligible junction capacitance. It
provides the possibilities for new circuit designs with low
power and high performance. The undoped channel body
provides negligible junction capacitance, which largely
enhances the circuit performance. The fabrication process of
DG-MOSFET is more challenging than their bulk MOSFET
transistors. DGMOSFETs have the following advantages over
bulk CMOS transistors:
d) Reduced Random dopant fluctuations (RDF) due to
undoped or lightly doped body and reduced carrier
mobility degradation.
e) Smaller junction capacitances.
f) Better immunity to SCEs, although negligible for
subthreshold operation.
g) Higher ION/IOFF ratio.
2.
FinFET/Tri-Gate FET
As the transistor scaling approaching below 20nanometers (nm), it is becoming difficult to get similar down
scaling for other transistor parameters, for example the supply
voltage, which is factor in determining dynamic power and
optimizing for one variable such as performance comes at a
cost of compromises in other areas like power.
FinFET or Tri-Gate FETs are further enhancement to
multi gate transistors and becoming popular due to its easy
fabrication process than previous one and it can be build on
both bulk as well as SOI. It is a non planar structure where a
thin channel is developed called fin where gate covers the
sidewalls and top of channel. In bulk process of Fin
fabrication all fins share a common substrate but in SOI Fins
are isolated by very shallow trench isolation. Double Gate
structure has the potential to provide the lowest gate leakage
current so by rotating the DG structure, FinFET transistor can
be manufactured easily using standard lithography techniques.
In this technique the layout is similar as planar FET and the
gate electrodes are self-aligned (Figure 5).
FinFET possesses the capability of design optimization
alternative as compared to planar MOS transistors for equal
performance at low power requirements or better performance
at same power.
Fig. 5. FinFET Architecture
Fig. 4. DG MOSFET Architecture
a) Nearly ideal subthreshold slope.
b) Design flexibility at circuit level by symmetric/asymmetric
with tied and independent gate options.
c) Small intrinsic gate capacitance.
When Gordon Moore presented his law in 1965, he
envisaged a design of about 50 components. The IC being
manufactured today’s consisting of billions of transistors and
further improving for “better, sooner, cheaper” products. The
high leakage current due to short-channel effects and varying
dopant levels have become obstacles for further downscaling.
Important points of FinFET technology are as follows.
a) FinFET technology was found in 1990s, when R&D was
going on for a possible successor to the planar transistor.
b) The team suggested that a thin-body MOSFET structure
would control short-channel effects and suppress leakage
c)
d)
e)
f)
g)
h)
i)
by keeping the gate capacitance in closer proximity to the
whole of the channel
FinFET is a three dimensional device that rise above the
planar substrate, it gives more area to individual transistor
for same coverage area on the chip.
The gate which covers the channel from three directions
provide excellent control of the channel and very small
current is allowed to leak through the body when the
device is in the off state.
This allows the use of lower threshold voltages, which
results in optimal switching speeds and power
Processing cost of FinFET is 2% to 5% higher than that of
planar wafer fabrication
FinFETs are up to 37% faster while using less than half the
dynamic power or cut static leakage current by as much as
90%
Designers can run the transistors faster and use the same
amount of power, compared to the planar equivalent, or
run them at the same performance using less power.
Design teams can balance performance throughput, and
power to obtain the requirements of each application.
1. Vertical Device Architecture
Vertical device Architecture is having following salient
features.
a) 50% reduction in plain view density
b) Vertical orientation may enable new circuit concept
c) Lithography ( may double the number of FE critical
Layers)
d) Interlayer contacts(diffusion-diffusion, gate-gate contacts)
e) Thermal processing(top layer may need to be processed
over existing bottom layer)
f) Strain engineering(more challenges than single layer)
Fig. 7. Vertical Device Architecture
III.
NEW OPTIONS FOR FURTHER
IMPROVEMENT
The short channel effects (SCE) are becoming serious
problems as the metal oxide semiconductor field effect
transistor (MOSFET) scales down to the deep sub-micron
dimension. A silicon tunneling transistor called TFET was
proposed as the candidate of MOSFET. This transistor realizes
the gate-controlled tunneling at room temperature. As a novel
device, there are still many unknowns and challenges in the
physics, fabrication, and application of TFETs.
2. Tunnel Field Effect Transistor (TFET)
TFET operate by tunneling through the source/drain barrier
rather than diffusion over the barrier and it possesses the
following salient features.
a) We can further reduce the channel length because of high
resistivity.
b) Suitable for low power application because of low leakage
current.
c) Sub threshold swing of TFET’s is better than MOSFET’s.
d) Operating speed of TFET’s greater than MOSFET’s.
e) Small drain current as compare to MOSFET’s because of
intrinsic channel.
Fig. 6. Alternative to Planer Technology
The transistor which is in production is having a channel
length of 22nm and this have been achieved using modified
structure of conventional MOSFET and it is called FinFET.
To further increase the density of a chip, we have two ways,
either vertical manufacturing of existing transistors or design a
novel transistor named as Tunnel FET or TFET. Vertical
Technology is having its own manufacturing difficulties.
Currently researchers are focusing on TFET’s as a
replacement of MOSFET Technology
Fig 8. TFET Architecture
f)
g)
h)
i)
j)
For boosting tunnel probability require :Steep doping as compare to MOSFET.
High mobility of electrons through channel.
Energy band alignment.
Sealing of SiO2 (oxide) layer.
Fig. 9. Energy Band Diagram of Homo vs. Hetro TFET
 Type of TFET (Homo & Hetro Junction)
a) Hetero-junction TFET provide higher drive current
resulted due to the reduction in effective tunneling barrier
at source without reducing the band-gap of the channel
material
b) HTFET simultaneous enables lower IOFF.
the design of low-power electronic circuits that can operate at
lower voltages as follows.
However, because of the use of the tunnelling effect, the
tunnel FET has the disadvantage that the current passing
through it is smaller than that through the MOSFET. To obtain
a higher current efficiency, it is important to apply a stronger
electric field to the tunnel junction. A high gate voltage is
required to apply a strong electric field, while the tunnel FET
needs to operate at a lower gate voltage to reduce power
consumption. Tunnel FET having small threshold swing less
than 60mV which mitigate the problem of leakage current at
low voltage.
The article [1] presents the design of hetero junction tunnel
FET based low logic gate for static & dynamic logic topology.
Comparison is done with 20nm Si-finFET technology with
supply voltage scaling. Points depicting HTFET perform
better than FinFET are given below.
Fig. 10. Drain Current for Hetro vs. Homo TFET
c) Het JTEFT exhibit higher drive current with comparable
Ion/off ratio to Hom JTFETs. More than 3 order of
magnitude improvement in Ion/off ratio achieved in Het
JTFET is due to the reduction in defect assisted conduction
with InAs termination.

TFET vs. MOSFET
Fig. 12. Sub-Threshold Swing of HTFET vs. FinFET
a) Due to the steep slope characteristics, HTFET have better
configuration than Si-FinFET .
b) Energy efficiency of HTFET is 66% more than Si-FinFET
static logic gate.
c) HTFET dynamic logic gate has 56% less energy
consumption than FinFET dynamic NAND gate at
Vdd=0.2V.
d) 20nm gate length HTFET shows 7x on current
improvement at Vcc=0.3V.
 Further improvements in TFET
Fig. 11. TFET vs. MOSFET Sub-threshold Swing
When a gate voltage is applied to the gate electrode of a
tunnel FET, the width of the barrier between the source and
the channel decreases owing to the effect of the electric field.
As a result, the electrons pass through the barrier because of
the tunnelling effect and current flows through the transistor.
Based on this principle, the tunnel FET can switch the current
on and off at a lower voltage than that of conventional
MOSFETs. The very fast switching of the tunnel FET enables
Fig. 13. TFET vs. SE-TFET
Conventional TFET has disadvantage that the current
passing through is smaller than that through the MOSFET. To
obtain higher current efficiently it is important to apply a
stronger electric field to the tunnel junction. A high gate
voltage is required to apply a strong electric field , while the
tunnel FET need to operate at lower gate voltage to reduce
power consumption.
Fig 13(b) is schematic of tunnel FET with new
architecture. After a very thin non-doped channel layer is
epitaxially grown on a source with a high concentration of
impurities, a three dimensional transistor is formed by placing
a gate electrode around the double layered channel.
New architecture, the vertical and horizontal electric field
are superimposed at the interface on the three dimensional
structured channel side-walls between the high concentration
source and non doped channel layer, making to apply strong
electric field than in conventional architectures. This is known
as synthetic electric field tunnel FET. The drain current is 10100 times higher in SE-MOSFET than conventional TFET.
Fig 14. Synthetic-TFET vs. Conventional TFET
IV.
CONCLUSION
There are different levels of improvement in a digital
circuit. The channel current of a TFET can be increased using
different methods as follows
a) Increasing the gate voltage (But it is not a feasible solution
for low voltage circuits )
b) Increasing the electric field at the gate terminal by using
the improved gate structure as demonstrated above (SETFET).
c) Use different materials and doping concentration in source
and drain diffusion and as demonstrated in Hetro Junction
Tunnel FET (HTFET)
Device process is lowest level of improvement and this
paper proposing the improvement in SS and drain current by
applying a synthetic electric field to Hetro junction Tunnel
FET.
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