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JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN
ELECTRICAL ENGINEERING
POWER QUALITY PROBLEMS STUDY ON IEEE 14
BUS SYSTEMS AND THEIR MITIGATION USING
UPQC WITH DIFFERENT CONTROL SCHEMES
1
MR. H. M. KARKAR, 2 DR. S. N. PANDYA
1M.E.
[Power System] Student, Department Of Electrical Engineering, L.D. College Of
Engineering, Ahmedabad
2Associate Professor, Department Of Electrical Engineering, L.D. College Of
Engineering, Ahmedabad
[email protected], [email protected]
ABSTRACT: In little more than ten years, electricity power quality has grown from obscurity to a major issue.
Power quality is among the main things that is emphasized and is taken into consideration by utilities in order
to meet the demands of their customer. At each passing day this issue has becoming more serious and at the
same time the user’s demand on power quality also gets more critical.Thus it is essential to establish a power
quality monitoring system to detect power quality disturbance. Several research studies regarding the power
quality have been done before and their aims frequently concentrated on the collection of raw data for a further
analysis, so the impacts of various disturbances can be investigated. This thesis deals with the implementation
of fact device UPQC on IEEE 14 BUS system. Different control schemes have been suggested for UPQC. Also a
methodology is shown for determining the most sensitive bus and the most sensitive load. UPQC is installed
between the sensitive bus and the load with three different control schemes and results are shown for different
types of fault at different-different locations. Also a comparison is shown between all the control schemes.
Keywords— UPQC, Voltage Sag, Voltage Swell, Power Quality. Hysteresis control,Unit vector template
generation technique,PWM technique
I: INTRODUCTION
Due to the extensive use of power electronic based
equipments/loads almost in all areas, the point of
common coupling (PCC) could be highly distorted
[1]-[3]. The switching ON/OFF of high rated load
connected to PCC may result into voltage sags or
swells on the PCC. There are several sensitive loads,
such as computer or microprocessor based AC/DC
drive controller, with good voltage profile
requirement; can function improperly or sometime
can lose valuable data or in certain cases get damaged
due to these voltage sag and swell conditions. One of
the effective approaches is to use a unified power
quality conditioner (UPQC) at PCC to protect the
sensitive loads. A UPQC is a combination of shunt
and series APFs, sharing a common dc link [1-3], [610]. It is a versatile device that can compensate
almost all power quality problems such as voltage
harmonics, voltage unbalance, voltage flickers,
voltage sags & swells, current harmonics, current
unbalance, reactive current, etc. The Unified Power
Quality Conditioner (UPQC) has evolved to be one
of the most comprehensive custom power solutions
for power quality issues relating to non-linear
harmonic producing loads and the effect of utility
voltage disturbance on sensitive industrial loads. To
investigate the performance of the proposed control
schemes for the UPQC, simulations are carried out
and validated with experimental results.
II: SYSTEM CONFIGURATION
The system configuration for UPQC is shown in the
Fig.1.The voltage at PCC may be or may not be
distorted depending on the other non-linear loads
connected at PCC. Also, these loads may impose the
voltage sag or swell condition during their switching
ON and/or OFF operation. The UPQC is installed in
order to protect a sensitive load from all disturbances.
The UPQC consists of two voltage source inverters
connected back to back, sharing a common dc link.
Each inverter is realized by using six IGBT switches.
One inverter is connected parallel with the load, acts
as shunt APF, helps in compensating load harmonic
current, reactive current and maintain the dc link
voltage at constant level. The second inverter is
Fig.1 Block Diagram of UPQC
connected in series with the line using series
transformers, acts as a controlled voltage source
maintaining the load voltage sinusoidal and at desired.
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ELECTRICAL ENGINEERING
III: STEADY STATE POWER FLOW ANALYSIS
The UPQC is controlled in such a way that the
voltage at load bus is always sinusoidal and at desired
magnitude.In the following analysis the load voltage
is assumed to be in phase with terminal voltage even
during voltage sag and swell condition. In this
particular condition, the series APF could not handle
reactive power and the load reactive power is
supplied by shunt APF alone [5].
Fig.2 Equivalent Circuit of a UPQC
The source voltage, terminal voltage at PCC and load
voltage are denoted by Vs, Vt and VL respectively.
The source and load currents are denoted by is and iL
respectively. The voltage injected by series APF is
denoted by VSr, whereas the current injected by shunt
APF is denoted by iSh. Taking the load voltage, VL, as
a reference phasor and suppose the lagging power
factor of the load is Cos L then we can write;[5]
VL=VL00
(1)
IL=IL-L
(2)
Vt=VL(1+k) 00 (3)
Where factor k represents the fluctuation of source
voltage, defined as,
k=
(4)
The voltage injected by series APF must be equal to,
VSr=VL−Vt=−kVL∠00
(5)
The UPQC is assumed to be lossless and therefore,
the active power demanded by the load is equal to the
active power input at PCC. The UPQC provides a
nearly unity power factor source current, therefore,
for a given load condition the input active power at
PCC can be expressed by the following equations,
Pt=PL
(6)
Vt.iS=VL.iL.cosφL
(7)
VL(1+k).iS=VL.iL.cosφL (8)
iS =iL/(1+k)*cosφL
(9)
The above equation suggests that the source current i S
depends on the factor k, since φLand iL are load
characteristics and are constant for a particular type
of load. The complex power absorbed by the series
APF can be expressed as,
S Sr =VSr .iS *
(10)
PSr =VSr .iS . cosφs =-k .VL .iS .cosφs
(11)
QSr=VSr .iS .sinφS
(12)
φS = 0 , since UPQC is maintaining unity power
factor
PSr =VSr .iS=−k .VL .iS
(13)
QSr ≅0
(14)
The complex power absorbed by the shunt APF can
be expressed as,
S Sh =VL .iSh *
(15)
The current provided by the shunt APF, is the
difference between the input source current and the
load current, which includes the load harmonics
current and the reactive current. Therefore, we can
write;
iSh =iS −iL
(16)
iSh =iS ∠00 −iL ∠ φL
(17)
iSh =iS −( iL .cosφL –j iL .sinφL )
(18)
iSh =(iS −iL .cosφL ) + j iL .sinφL
(19)
PSh =VL .iSh .cosφsh =VL .(iS −iL .cosφL)
(20)
QSh=VL .iSh .sinφsh V L .iL .sinφL
(21)
When a sag is detected such that |Vs2| <|Vs1| (rated),
then for UPQC-Q , Vinj is calculated from as.[21]
Vinj2 = (Vs12 – Vs22)
Now from PWM method √2Vinj = MI (Vdc/2),
where MI is the desired modulation index (MI).
Therefore,
MI = (2√2 .Vinj)/Vdc
If x is the p. u. sag to be mitigated, minimum dc link
voltage would be Vdc= 2√(2 )* √(x(2-x)) * Vs1, for
maximum value of MI =1 (taking the injection
transformer turns ratio to be 1:1).
IV: CONTROL SCHEMES FOR UPQC
The control strategy is basically the way to generate
reference signals for both shunt and series APF. The
effectiveness of the UPQC depends on its ability to
follow the reference signals with a minimum error to
compensate the voltage sag and swell or any other
undesirable condition. The series APF acts as a
controlled voltage source. The shunt APF acts as a
control source for maintaining the DC link voltage.
The shunt APF also provides required var to the load
such that the power factor at PCC is unity and only
fundamental active power is supplied by the source.
The voltage injected by series APF can be varied
from 0o to360o .The series injected voltage has to be
in phase (out of phase) with PCC voltage to
compensate voltage sag swell.
4.1 Different Control Schemes for UPQC
1. Control for Series and Shunt APF
2. Unit Vector Template Generation(UVTG)
Technique for Series and Shunt APF
3. Sinusoidal Pulse Width Modulation(SPWM)
Technique for Series and Shunt APF
V: IEEE 14 BUS TEST SYSTEMS
The IEEE 14 Bus Test Case represents a portion of
the American Electric Power System (in the
Midwestern US) as of February, 1962. A muchXeroxed paper version of the data was kindly
provided by Iraj Dabbagchi of AEP and entered in
IEEE Common Data Format by Rich Christie at the
University of Washington in August 1993.
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ELECTRICAL ENGINEERING
Fig.3 IEEE 14 Bus System
5.1 SYSTEM VARIFICATION FROM LOAD
FLOW AND SIMULATION
Table No.1
Bus
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Actual
Value
(p.u)
1.06
1.0450
1.01
1.016
1.018
1.0700
1.06
1.0901
1.05334
1.0489
1.0559
1.0558
1.050
1.0339
Bus Voltage
From Load
Flow(p.u)
1.06
1.0448
1.0097
1.0162
1.01194
1.0698
1.05947
1.08931
1.0524
1.0481
1.05487
1.05422
1.05494
1.03308
Bus Voltages
from
Simulation (p.u)
1.06
1.0449
1.0099
0.9967
0.999
1.069
1.0208
1.0900
1.0193
1.0243
1.0438
1.0614
1.05705
1.02889
Table No.2
Bus
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
IEEE Bus
Voltages (kv)
69
69
69
69
69
13.8
13.8
18
13.8
13.8
13.8
13.8
13.8
13.8
Simulation Results
(kv)
69.00
69.00
69.00
67.18
67.42
13.81
13.45
18.07
13.28
13.25
13.43
13.67
13.60
13.24
VI: METHODOLOGY FOR DECIDING THE
LOCATION OF UPQC
As our test system is the IEEE 14 BUS system which
has 22 lines and 14 buses. Bus 1 is Slack Bus and
Buses 2,3,6,8 are the generator buses. All the buses
except bus 1 contains loads also. So it is important to
decide that which bus is the most critical bus.
For deciding the location of UPQC a fault based
technique is suggested. The bus which is always
affected by the faults, no matter where the fault is
taking place in the system, is called as most critical
bus and the load connected to that bus is called as the
most critical load.
The location of UPQC is decided in two steps :
6.1 STEP 1
1. At first we created the 3 phase fault at the
mid-point of each line for a short period, as
the 3 phase fault is the most severe one.
2. Then we measured the voltages of all the
buses except the generator and slack bus.
3. Then we selected the 2 most critical lines.
They are called critical because when we
created the fault on these lines, the effect of
3 phase fault was most severe and they are
affecting the most number of buses in the
system.
4. After preparing the table for these results we
selected the line 7-9 and line 9-10 as the
most critical lines.
6.2 STEP 2
1. After selecting the bus 9-10 & 7-9 as most
critical line, we created the different types of
faults at 5-5 % distance on these lines.
2. We plotted the graph between the distance
and the voltage magnitude.
3. After analyzing all the graphs and tables, we
prepared the table for all conditions which
shows that during all types of faults which
buses are mostly affected.
VII: ANALYSIS FROM ABOVE RESULTS
Sr.
No
1
2
3
7.1
Fault
Type
3Phase
fault
PhaseA
fault
PhaseA-B
fault
Table No.3
Buses
Line
with
7-9
sag
Most
Critical
4,7,9,10
7,9,10
,11,14
7,9,10,
7,9,10
11,14
7,9,10
7,9,10
11,14
Line
9-10
Most
Critical
9,10
9,10
9,10
Conclusion from above Results
1. Above table shows that bus 9 and bus 10 are
the most critical buses because they are
always suffering from sag created by
different types of faults at different –
different locations.
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2.
But we chose bus 9 as the most critical bus
as larger load is connected at that bus.
VIII: SIMULATION RESULTS WITH
DIFFERENT CONTROL SCHEMES
8.1 Load and Bus Voltages during Fault Condition
Fig. 6 Waveforms at Load Side with Hysteresis Controller
8.3 SPWM Based Series and Shunt Controller
Fig. 4 Source and Load side wave forms during fault
condition
8.2 Hystersis Based Series and Shunt Controller
Fig. 7 SPWM based Controller
Fig. 5 Hysteresis Control
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Fig. 10 Load Side Waveforms with UVTG
Technique
Fig. 8 Load side waveforms with SPWM Technique
8.4 Unit Vector Template Generation Technique
IX: CONCLUSION
 If the sags are more frequent and for a very
short duration then it is better to use
Hysteresis Controller.since it is faster and
in-sensitive to system parameters with
inherent peak current limiting capability.
Also it is easy to implement and in closed
loop, offers current protection with excellent
dynamic response. It ensures the elimination
of higher order harmonics of the load
without the need of any additional filter
circuits.
 SPWM technique takes more simulation
time and it takes more time to maintain dc
link voltage.
 If the duration of sag is more but not
occurring frequently then it is better to use
SPWM technique
 If the sags are more frequent and for a very
short duration and the load is most sensitive
then it is better to use Hysteresis controller
 Unit vector template generation technique
is more accurate and precise as we are
generating a pu. Reference signal and then
locking the phase other wise results are
similar to hysteresis control.
Fig. 9 UVTG Technique
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ELECTRICAL ENGINEERING
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