Download SYNCHRONOUS PROGRAMMABLE 4

HCF40161B
SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY
COUNTER WITH ASYNCHRONOUS CLEAR
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■
INTERNAL LOOK-AHEAD FOR FAST
COUNTING
CARRY OUTPUT FOR CASCADING
SYNCHRONOUSLY PROGRAMMABLE
LOW-POWER TTL COMPATIBILITY
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIF. UP TO 20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
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DESCRIPTION
HCF40161B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40161B is a 4-bit synchronous programmable
counter. The CLEAR function is asynchronous. A
low level at the CLEAR input sets all four outputs
low regardless of the state of the CLOCK, LOAD
and ENABLE inputs. A low level at the LOAD
inputs disables the counter and causes the output
to agree with the set-up data after the following
CLOCK pulse regardless of the conditions of the
DIP
SOP
ORDER CODES
PACKAGE
TUBE
T&R
DIP
SOP
HCF40161BEY
HCF40161BM1
HCF40161M013TR
ENABLE inputs. The carry look-ahead circuitry
provides for cascading counter for n-bit
synchronous application without additional gating.
Counting is enabled when both the PE and TE
inputs are high. The TE input is fed forward to
enable COUT. This enable output produces a
positive
output
pulse
with
a
duration
approximately equal to the positive portion of the
Q1 output. This positive overflow carry pulse can
be used to enable successive cascaded stages.
Logic transitions at the PE and TE inputs may
occur when the clock is either high or low.
PIN CONNECTION
September 2002
1/14
HCF40161B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
NAME AND FUNCTION
1
CLEAR
2
CLOCK
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
P1 to P4
PE
TE
LOAD
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-triggered)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Q1 to Q4
Flip Flop Outputs
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8
16
LOGIC DIAGRAM
2/14
CARRY OUT Terminal Count Output
VSS
Negative Supply Voltage
VDD
Positive Supply Voltage
HCF40161B
TRUTH TABLE
CLOCK
X
CLR
LOAD
PE
TE
OPERATION
H
L
X
X
PRESET
H
H
L
X
NC
H
H
X
L
NC
H
H
H
H
COUNT
L
X
X
X
RESET
(X) : Don’t Care
NC : No Change
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TIMING DIAGRAM
3/14
HCF40161B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
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RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
4/14
Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
HCF40161B
DC SPECIFICATIONS
Test Condition
Symbol
IL
VOH
Parameter
Quiescent Current
High Level Output
Voltage
VI
(V)
VO
(V)
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
Value
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
150
300
600
3000
4.95
9.95
14.95
Unit
Max.
150
300
600
3000
4.95
9.95
14.95
µA
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VOL
VIH
VIL
IOH
IOL
II
CI
Low Level Output
Voltage
High Level Input
Voltage
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0/18
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
Any Input
Any Input
18
0.05
0.05
0.05
0.05
0.05
0.05
3.5
7
11
3.5
7
11
1.5
3
4
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
-3.2
-1
-2.6
-6.8
1
2.6
6.8
3.5
7
11
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
±0.1
5
7.5
0.05
0.05
0.05
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±1
V
V
V
V
mA
mA
±1
µA
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
5/14
HCF40161B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)
tPLH tPHL Propagation Delay Time
Clock to Q
tPLH tPHL Propagation Delay Time
Clock to COUT
tPLH tPHL Propagation Delay Time
TE to COUT
tsetup
Setup Time
Data to Clock
tsetup
Setup Time
Load to Clock
tsetup
Setup Time
PE or TE to Clock
Hold Time
thold
c
u
d
Clock Input Pulse Width
ete
l
o
s
tr tf
t
e
l
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tPHL
s
b
O
Proagation Delay Time
Clear to Q
Clear Input Pulse Width
Low Level
(s)
Min.
P
e
let
o
s
b
-O
e
t
le
so
b
O
-
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
6/14
240
90
60
240
90
60
340
140
100
0
0
0
Typ.
Max.
200
80
60
225
95
70
125
55
40
120
45
30
120
45
30
170
70
50
400
160
120
450
190
140
250
110
80
c
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P
170
70
50
2
5.5
8
170
70
50
Unit
ns
ns
(s)
t
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t
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P
e
Clock Input Rise or Fall
Time
b
O
tW
o
r
P
Maximum Clock Input
Frequency
fCL
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
)
s
(
t
tTHL tTLH Transition Time
tW
Value (*)
ns
ns
)
s
t(
ns
ns
ns
100
50
40
85
35
25
3
8.5
12
250
110
80
85
35
25
200
100
80
ns
ns
MHz
200
70
15
500
220
160
ns
ns
ns
HCF40161B
TEST CIRCUIT
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CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK MINIMUM PULSE WIDTH (f=1MHz; 50%
duty cycle)
7/14
HCF40161B
WAVEFORM 2 : PROPAGATION DELAY TIMES, CLEAR MINIMUM PULSE WIDTH (CLEAR MODE)
(f=1MHz; 50% duty cycle)
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WAVEFORM 3 : SETUP AND HOLD TIMES (PRESET MODE) (f=1MHz; 50% duty cycle)
8/14
HCF40161B
WAVEFORM 4 : SETUP AND HOLD TIMES (COUNTENABLE MODE) (f=1MHz; 50% duty cycle)
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WAVEFORM 5 : PROPAGATION DELAY TIMES (CASCADE MODE) (f=1MHz; 50% duty cycle)
9/14
HCF40161B
TYPICAL APPLICATION: DETAIL OF FLIP-FLOPS (Asynchronous Clear)
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TYPICAL APPLICATION: CASCADING COUNTER PACKAGES IN THE PARALLEL-CLOCKED MODE
10/14
HCF40161B
TYPICAL APPLICATION: CASCADING COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE
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11/14
HCF40161B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
b
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.5
0.030
0.065
0.020
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b1
0.25
D
0.010
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
12/14
HCF40161B
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
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C
0.5
0.019
c1
45˚ (typ.)
D
9.8
E
5.8
10
0.385
6.2
0.228
0.393
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8 ˚ (max.)
PO13H
13/14
HCF40161B
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2002 STMicroelectronics - Printed in Italy - All Rights Reserved
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14/14