Download 8-STAGE STATIC SHIFT REGISTERS

HCF4014B
SYNCHRONOUS PARALLEL OR SERIAL IN/SERIAL OUT
8 - STAGE STATIC SHIFT REGISTER
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MEDIUM SPEED OPERATION :
12 MHz (Typ.) At VDD = 10V
FULLY STATIC OPERATION
8 MASTER-SLAVE FLIP-FLOPS PLUS
OUTPUT BUFFERING AND CONTROL
GATING
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4014B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is an 8-stage parallel or serial input/
serial output register having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a single
SERIAL data input, and individual parallel "JAM"
inputs to each register stage. Each register stage
is a D-type, master-slave flip-flop in addition to an
output from stage 8, "Q" outputs are also available
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DIP
SOP
PACKAGE
TUBE
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DIP
SOP
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ORDER CODES
HCF4014BEY
HCF4014BM1
T&R
HCF4014M013TR
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from stages 6 and 7. Parallel as well as serial
entry is made into the register synchronously with
the positive clock line transition. In this device,
entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL
CONTROL input is low, data is serially shifted into
the 8-stage register synchronously with the
positive transition of he clock line. When the
PARALLEL/SERIAL CONTROL input is high, data
is jammed into the 8-stage register via the parallel
input lines and synchronous with the positive
transition of the clock line.
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PIN CONNECTION
October 2002
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HCF4014B
IINPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
7, 6, 5, 4, 13,
14, 15, 1
11
PI1 to PI8
NAME AND FUNCTION
8
SERIAL IN
PARALLEL/
SERIAL
CONTROL
CLOCK
Q6, Q7, Q8
VSS
16
VDD
9
10
2, 3, 12
Parallel Input
Serial Input
Parallel/Serial Input Control
Clock Input
Buffered Outputs
Negative Supply Voltage
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TRUTH TABLE
CLOCK
SERIAL INPUT
PARALLEL/
SERIAL
CONTROL
PI - 1
X
1
0
X
1
X
1
X
1
0
0
1
ct
0
du
X
LOGIC DIAGRAM
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Q1
(INTERNAL)
Qn
0
0
0
1
0
1
0
1
1
1
1
1
X
X
0
Qn - 1
X
X
1
Qn - 1
X
X
Q1
Qn
PI - n
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1
0
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Positive Supply Voltage
0
HCF4014B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Value
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
PD
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
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RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
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Parameter
Supply Voltage
VI
Input Voltage
Top
Operating Temperature
tr, tf
Input Rise and Fall Time (PI-1 ... PI-8)
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VDD = 5V
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Value
Unit
3 to 20
V
0 to VDD
V
-55 to 125
°C
0 to 1000
µs
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HCF4014B
DC SPECIFICATIONS
Test Condition
Symbol
IL
Parameter
Quiescent Current
VOH
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Output
Voltage
VOL
Low Level Output
Voltage
VIH
High Level Input
Voltage
VIL
Low Level Input
Voltage
IOH
Output Drive
Current
IOL
Output Sink
Current
II
CI
Input Leakage
Current
Input Capacitance
0/5
0/5
0/10
0/15
0/5
0/10
0/15
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
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|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
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VO
(V)
VI
(V)
Value
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-55 to 125°C
Min.
Min.
4.95
9.95
14.95
3.5
7
11
1.5
3
4
-3.2
-1
-2.6
-6.8
1
2.6
6.8
3.5
7
11
4.95
9.95
14.95
±10-5
±0.1
5
7.5
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±1
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V
V
V
1.5
3
4
The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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0.05
0.05
0.05
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
µA
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Pr
Unit
Max.
150
300
600
3000
0.05
0.05
0.05
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-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
150
300
600
3000
0.05
0.05
0.05
-O
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Typ.
-40 to 85°C
V
mA
mA
±1
µA
pF
HCF4014B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, C L = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Value (*)
Unit
Parameter
VDD (V)
Min.
Typ.
Max.
320
160
120
200
100
80
3
6
8.5
180
80
50
160
80
60
100
50
40
6
12
17
90
40
25
CLOCKED OPERATION
tPLH tPHL Propagation Delay Time
tTHL tTLH Transition Time
fCL (1)
tW
Maximum Clock Input
Frequency
Clock Pulse Width
tr , tf
tsetup
tsetup
tsetup
thold
Clock Input Rise or Fall
Time
Setup Time, serial Input
(ref to CL)
Setup Time, Parallel Inputs
(ref to CL)
Setup Time, Parallel/Serial
Control (ref to CL)
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120
80
60
80
50
40
180
80
60
0
0
0
ns
ns
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Hold Time, serial in,
parallel in, parallel /serial
control
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
60
40
30
40
25
20
90
40
30
MHz
ns
15
15
15
µs
ns
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay
of the output of the driving stage of the estimated capacitive load.
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HCF4014B
TEST CIRCUIT
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CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
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WAVEFORM 1 : PROPAGATION DELAY TIMES, CLOCK PULSE WIDTH (f=1MHz; 50% duty cycle)
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HCF4014B
WAVEFORM 2 : SETUP AND HOLD TIMES (SI TO CLOCK) (f=1MHz; 50% duty cycle)
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WAVEFORM 3 : SETUP AND HOLD TIME (PI TO P/S) (f=1MHz; 50% duty cycle)
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HCF4014B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
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20
E
8.5
e
2.54
e3
17.78
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0.335
7.1
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5.1
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1.27
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3.3
Z
Pr
0.100
F
L
0.787
0.700
0.280
0.201
0.130
0.050
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P001C
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HCF4014B
SO-16 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
a1
1.75
MAX.
0.1
0.068
0.2
a2
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
c1
45˚ (typ.)
D
9.8
E
5.8
)
s
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0.019
e
1.27
e3
8.89
10
0.385
6.2
0.228
4.0
G
4.6
L
0.5
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5.3
1.27
)
(s
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3.8
S
Pr
0.393
0.244
0.050
F
M
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0.62
0.350
0.149
0.157
0.181
0.208
0.019
0.050
0.024
8 ˚ (max.)
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PO13H
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HCF4014B
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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