Download PRESETTABLE DIVIDE-BY

Survey
yes no Was this document useful for you?
   Thank you for your participation!

* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project

Document related concepts

TRIAC wikipedia , lookup

UniPro protocol stack wikipedia , lookup

Multimeter wikipedia , lookup

Oscilloscope history wikipedia , lookup

Amplifier wikipedia , lookup

Ohm's law wikipedia , lookup

Phase-locked loop wikipedia , lookup

Surge protector wikipedia , lookup

Resistive opto-isolator wikipedia , lookup

CMOS wikipedia , lookup

Power electronics wikipedia , lookup

Power MOSFET wikipedia , lookup

Integrating ADC wikipedia , lookup

Wilson current mirror wikipedia , lookup

Analog-to-digital converter wikipedia , lookup

Valve RF amplifier wikipedia , lookup

Transistor–transistor logic wikipedia , lookup

Voltage regulator wikipedia , lookup

Time-to-digital converter wikipedia , lookup

Flip-flop (electronics) wikipedia , lookup

Current mirror wikipedia , lookup

Switched-mode power supply wikipedia , lookup

Operational amplifier wikipedia , lookup

Schmitt trigger wikipedia , lookup

Immunity-aware programming wikipedia , lookup

Opto-isolator wikipedia , lookup

Rectiverter wikipedia , lookup

Transcript
HCF4018B
PRESETTABLE DIVIDE-BY-N COUNTER
■
■
■
■
■
■
■
■
MEDIUM SPEED OPERATION 10 MHz (Typ.)
at VDD - VSS= 10V
FULLY STATIC OPERATION
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4018B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4018B consist of 5 Johnson counter
stages, buffered Q outputs from each stage, and
counter preset control gating. CLOCK, RESET,
DATA, PRESET ENABLE, and 5 individual JAM
inputs are provided. Divide by 10, 8, 6, 4 or 2
counter configuration can be implemented by
feeding the Q5, Q4, Q3, Q2, Q1 signals,
respectively, back to the data input.
Divide-by-9, 7, 5, or 3 counter configurations can
be implemented by the use of a HCF4011B gate
)
s
(
ct
u
d
o
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF4018BEY
HCF4018BM1
)
s
t(
T&R
c
u
d
HCF4018M013TR
o
r
P
package to properly gate the feedback connection
to the DATA input. Divide-by-functions greater
than 10 can be achieved by use of multiple
HCF4018B units. The counter is advanced one
count at the positive clock signalstransition.
Schmitt trigger action on the clock line permits
unlimited clock rise and fall times. A high RESET
signal clears the counter to an all-zero condition. A
high
PRESENT-ENABLE
signal
allows
information on the JAM inputs to preset the
counter.
Anti-lock gating is provided to assure the proper
counting sequence.
e
t
le
o
s
b
O
-
r
P
e
t
e
l
o
PIN CONNECTION
s
b
O
September 2001
1/11
HCF4018B
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
2, 3, 7, 9, 12
1
4, 5, 6, 11,
13
15
14
SYMBOL
JAM1 to
JAM5
DATA
NAME AND FUNCTION
Jam Inputs
Data Input
Q1 to Q5
Buffered Outputs
Reset Input
Clock Input
8
RESET
CLOCK
PRESET
ENABLE
VSS
16
VDD
10
Preset Enable Input
Negative Supply Voltage
Positive Supply Voltage
FUNCTIONAL DIAGRAM
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
2/11
o
s
b
O
-
o
r
P
)
s
t(
HCF4018B
LOGIC DIAGRAM
c
u
d
TIMING CHART
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
3/11
HCF4018B
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Supply Voltage
VI
DC Input Voltage
II
DC Input Current
PD
Value
Unit
-0.5 to +22
V
-0.5 to VDD + 0.5
± 10
V
mA
200
100
mW
mW
Top
Power Dissipation per Package
Power Dissipation per Output Transistor
Operating Temperature
-55 to +125
°C
Tstg
Storage Temperature
-65 to +150
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
Value
Supply Voltage
3 to 20
VI
Input Voltage
Top
Operating Temperature
0 to VDD
c
u
d
-55 to 125
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
4/11
o
s
b
O
-
o
r
P
Unit
)
s
t(
V
V
°C
HCF4018B
DC SPECIFICATIONS
Test Condition
Symbol
IL
Parameter
Quiescent Current
0/5
0/10
0/15
0/20
0/5
0/10
0/15
5/0
10/0
15/0
High Level Output
Voltage
VOH
Low Level Output
Voltage
VOL
High Level Input
Voltage
VIH
Low Level Input
Voltage
VIL
Output Drive
Current
IOH
0/5
0/5
0/10
0/15
0/5
0/10
0/15
Output Sink
Current
IOL
Input Leakage
Current
Input Capacitance
II
CI
VO
(V)
VI
(V)
0.5/4.5
1/9
1.5/13.5
4.5/0.5
9/1
13.5/1.5
2.5
4.6
9.5
13.5
0.4
0.5
1.5
|IO| VDD
(µA) (V)
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
<1
)
s
(
ct
0/18
Value
Any Input
Any Input
5
10
15
20
5
10
15
5
10
15
5
10
15
5
10
15
5
5
10
15
5
10
15
TA = 25°C
Min.
Typ.
Max.
0.04
0.04
0.04
0.08
5
10
20
100
4.95
9.95
14.95
-55 to 125°C
Min.
Min.
150
300
600
3000
0.05
0.05
0.05
r
P
e
t
le
-3.2
-1
-2.6
-6.8
1
2.6
6.8
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±10-5
±0.1
5
7.5
µA
4.95
9.95
14.95
3.5
7
11
1.5
3
4
V
0.05
0.05
0.05
3.5
7
11
1.5
3
4
Unit
Max.
150
300
600
3000
0.05
0.05
0.05
3.5
7
11
-1.36
-0.44
-1.1
-3.0
0.44
1.1
3.0
Max.
4.95
9.95
14.95
o
s
b
O
18
-40 to 85°C
uc
od
)
s
t(
1.5
3
4
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
±1
V
V
V
mA
mA
±1
µA
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
u
d
o
r
P
e
t
e
l
o
s
b
O
5/11
HCF4018B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)
tPLH tPHL Propagation Delay Time
tTHL tTLH Transition Time
Maximum Clock Input
Frequency
fCL
Minimum Clock Pulse
Width
tW
Clock Input Rise or Fall
Time
tr , tf
tsetup
Data Setup Time Minimum
Clock Inhibit
Data Input Hold-Time
tH
PRESET(1) or RESET OPERATION
tPLH, tPHL Propagation Delay Time
(reset or reset to Q)
Preset or Reset Pulse
Width
tW
tREM
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
(s)
od
o
s
b
O
-
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) At PRESET ENABLE or JAM inputs
t
e
l
o
s
b
O
6/11
Typ.
Max.
400
180
130
200
100
80
3
7
8.5
160
70
50
200
90
65
100
50
40
6
14
17
80
35
25
c
u
d
e
t
le
Unit
Min.
unlimited
t
c
u
Preset or Reset Removal
Time
r
P
e
Value (*)
40
12
6
140
80
60
20
6
3
70
40
30
160
70
50
80
30
20
275
125
90
80
35
25
40
15
10
o
r
P
ns
ns
MHz
ns
)
s
t(
µs
ns
ns
550
250
180
ns
ns
ns
HCF4018B
TYPICAL APPLICATION
External connections for divide by 10, 9, 8, 7, 6, 5, 4, 3, 2 operation
DIVIDE BY 10 Q5
DIVIDE BY 8 Q4
DIVIDE BY 6 Q3
DIVIDE BY 4 Q2
DIVIDE BY 2 Q1
CONNECTED BACK TO "DATA"
NO EXTERNAL COMPONENTS
REQUIRED
NO CONNECTED
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
7/11
HCF4018B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
8/11
o
s
b
O
-
o
r
P
)
s
t(
HCF4018B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
I
5.1
L
c
u
d
e
t
le
3.3
Z
1.27
)
s
(
ct
o
s
b
O
-
o
r
P
)
s
t(
0.280
0.201
0.130
0.050
u
d
o
r
P
e
t
e
l
o
s
b
O
P001C
9/11
HCF4018B
SO-16 MECHANICAL DATA
mm.
DIM.
MIN.
TYP
A
inch
MAX.
MIN.
TYP.
a1
1.75
0.1
0.068
0.2
a2
MAX.
0.003
0.007
1.65
0.064
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
)
s
t(
0.244
e
1.27
0.050
e3
8.89
0.350
F
3.8
4.0
0.149
G
4.6
5.3
0.181
L
0.5
1.27
0.019
M
e
t
le
0.62
S
8° (max.)
)
s
(
ct
o
r
P
c
u
d
0.157
0.208
0.050
0.024
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
PO13H
10/11
HCF4018B
c
u
d
e
t
le
)
s
(
ct
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
11/11