Download Effects of Device Variations on the EMI Potential of High

Effects of Device Variations on the EM1 Potential of
High Speed Digital Integrated Circuits
James L. Knighten
Joseph T. (Ted) DiBene II
NCR Corporation
17095Via de1Campo
San Diego, CA 92127
Abstract: Radiated emissions from printed circuit boards can be
influenced by component variations. This is particularly true for
high speed digital circuitry. Changes in resistors, capacitors, inductors, transmission lines, and integrated cirduit chips may have a
significant effect on the radiation characteristics of a real system.
Variations in component characteristics significantly affect digital
signal waveforms (risetimes, falltimes, envelope structure). These
component variations are routinely accounted for in signal integrity
analysis to ensure the purest signal waveshapes. Waveshapes directly influence radiated emission characteristics.
Conventional
EMC modeling techniques and algorithms do not directly predict
the behavior of these devices under temperature, voltage, time, and
other variables which affect the operation of the component in question.
This paper takes an approach to examining a specific type of component (a CMOS ASIC) and its potential effect on a printed circuit
board emissions by analyzing its behavior under certain conditions
(e.g. temperature, process variation, and voltage source variation).
A high pin count 560 pin Tape Ball Grid Array (TGBA) package is
examined. The effects on the IC are bounded and quantified.
I.
INTRODUCTION
It is well known that passive and active circuit components exhibit
variable characteristics, due to parasitics, part-to-part variabilities,
and other environmental variabilities (such as temperature) that
influence circuit behavior. For example, resistors exhibit parasitic
self and mutual inductive and capacitive characteristics. The first is
due to leads and internal construction and the latter is due to placement on a printed circuit board. These variable traits often become
more significant as frequency increases. Similarly, real capacitors
and inductors also exhibit parasitics and other variable traits. These
variable characteristics represent analog behavior of circuit elements
that may be functions of mechanical configuration, manufacturing
process, temperature, installation in a circuit, or other factors.
NCR Corporation
17095Via de1Campo
San Diego, CA 92127
These part-to-part and environmental variabilities can create significant circuit operational differences (data signal). At very high
speeds, digital circuits actually operate as analog circuits striving to
function within certain bounds of signal strength, duration and
waveshape that allow digital operation. In very high speed digital
circuitry, both parasitics, part-to-part variabilities and environmental
response variabilities can have a significant influence on the waveshape of the signal current. This variation in signal current represents a variation in the source of EMI.
In many cases of EMI radiation, common mode current generation
on the printed circuit board is the dominant source of EMI radiated
energy [2], [3]. A source of wmmon mode currents on a printed
circuit board is the differential mode current in the circuit [4], [5].
[6]. That is to say that the source of EMI radiation is the same
source as the normal operating currents (data signal, clock), i.e., the
semiconductor active devices in the circuit. Therefore, differences
in differential mode signal spectra and amplitude directly influence
common mode current spectra and amplitude and potential for EMI.
This paper examines a specific active component and its behavior
under differing conditions. A modern 560 pin Tape Ball Grid Array
(TBGA) CMOS ASIC is studied, focusing on the 3.3V TTL data
input/output (I/O). The signals switch at a 50 MHz rate and the
rise/fall times range from 500 ps to 1 ns, depending upon the process variations, temperature, voltage, etc. (These switching speeds
are much faster than previous generation technologies that switch
with rise/fall times between 1 and 3 ns.) The differences in signal
waveshape and amplitude are analyzed using signal integrity modeling methods in SPICE. Significant differences in waveshape (and
hence spectral content) are shown in otherwise identical parts.
II.
DATA WAVEFORM HARMONIC?CHARACTERISTICS
A common practice in the EMC community is to approximate clock
or digital data waveforms as being trapezoidal in shape to simplify
signal analysis and emissions prediction [l].
Trapezoidal waveforms with symmetric rise and fall times exhibit half-wave symmetry (50% duty cycle) and hence yield spectra that contain odd harmonics only. Many modern semiconductor devices exhibit asymmetries in rise and fall times that yield spectra that contain both odd
and even harmonics. This is important when dealing with modern,
fast edge rate devices, such as the CMOS ASIC that is examined in
this paper.
The modeling of high speed systems for emissions potential requires
that attention be paid to the spectral characteristics of the data signal
[I]. With current data rates near 1 Gb/sec, this admonition is even
more important. What may not be as well appreciated in the EMC
community is that active circuit elements exhibit operational variabilities that can have significant effects on the normal operational
signals (i.e., data signal) of high speed digital circuits. These parasitics/variabilities may include package parasitic capacitances, re’&stances- ahd rhaucrances,‘~ remperamre, marfmticmring process, * wn-exsmlpre”o+‘- me-pr’outiarun”w’r -obmaven--ahu’&h -narmomcS is
shown for a HP HDMP-1536 Fibre Channel transceiver TTL
placement on a circuit board, etc.
(parallel side I/O), operating at 53 MHz. This example is chosen
0-7803-4140-6/97/$10.00
208
because the TI’L I/O driver closely resembles the more complex
CMOS ASIC being analyzed” . Figure 1 shows the measured waveform of the TTL I/O data signal with an HP 54720D Digitizing, Real
Time Oscilloscope and an HP 54701A 2.5 GHz Active Probe. Figure 2 shows the spectrum of this waveform as calculated directly by
the digitizing oscilloscope. Clearly, both odd and even harmonics
are present. These are displayed as peaks at 53 MHz, 106 MHz,
159 MHz, etc.
This device has been modeled by its manufacturer in HSPICE with a
complex model that characterizes device level construction of the
chip. Hence, the model has been developed to acknowledge the
effects of manufacturing process variability, operating temperature,
operating voltage (i.e., Vuu - Vss), etc.
Figure 3 shows a schematic representation of the buffer circuit modeled. The PMOS and NMOS transistors are shown cascaded for
Channel 1
Driver Circuits
Single TTL Driver
Output of ASIC
input Buffer
.----------------------------------------------;
Figure 3: Schematic representation of driver circuit modeled.
Figure 1: Measured waveform of a 53 MHz data signal of a
Fibre Channel TTL parallel I./O, showing
asymmetrical rise and fall times
Selup
print
Figure 2: Instrument determined Fourier Transform of
Measured waveform in Figure 1
II.
CMOS ASIC MODEL
A more complex device, a 560 pin TBGA package CMOS ASIC is
examined analytically. This 3.3 V device is TTL compatible with
virtually the same I/O as the Fibre Channel ITL I/O discussed
above. The signals switch at 50 MHz where the rise/fall times
range from 500 ps to 1 ns, depending upon process variations, temperature, voltage, etc.
a This I/O signal was taken from a test board due to lack of availability of the
C M O S ASK. While the I/O drivers are similar, the circuit interconnections and
terminations are not, reflecting the different waveshapes between measured and
simulated data in this paper.
209
source current generation and for modeling purposes. Package parasitics are located in the device at the power, ground, and signal connections (each box represents a combination of R, L, and C’s). The
transmission line is a 12” 65 ohm series/source terminated element.
The drive circuit (dashed line) and receiver buffer was modeled by
the manufacturer using an HSPICE compatible BSIM Level 13
MOSFET transistor model [7]. Three distinct low level models
were used for each of three process variances for both the NMOS
and PMOS enhancement mode transistors which make up the driver
circuit. Between each process variance there are parameters within
each NMOS and PMOS transistor which have been altered depending upon the external environmental conditions (temperature, voltage, etc.) and the process itself. As an example, parameters like the
flatband voltage VFBO, drain mobilities XMUS/XMUZ, and gate-todrain/source parasitic capacitances CGDOM and CGSOM all vary
from one process variance to the other. These parameters (and others) effect the behavior of the device under certain process and operating conditions. For modeling purposes these parameter changes
(for three different variations of process) are defined by the manufacturer as strong, nominul, or weak. As an example, XMUZIXMUS
is smaller for a strong process. At manufacturing these variances
appear as changes in the doping levels, polysilicon thicknesses,
metalization layers, and other factors. During manufacturing, process changes can alter these parameters and thus, the circuits behavior. Voltage thresholds can be altered by doping levels during wafer
fabrication as can the other parameters from other manufacturing
process variances [8][9]. An external effect such as temperature can
change mobility altering the circuit operation as well. These phenomena can be observed at the output of the circuit and are modeled
very accurately with detailed SPICE models such as the one used for
the driver circuit of the ASIC section represented in Figure 3.
While many of these differences in operating conditions of a real
device can be intentionally selected, some are determined by process
lot, placement on a printed circuit board, and other means which
may be out of the control of the circuit designer and EMC engineer.
IIt. RESULTS
Table I shows the parameter values used in the worst case, the
nominal case, and the best case models (these definitions were chosen for signal integrity reasons)
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Figure 4 shows a nominal 50 MHz data waveform produced by this
chip, based on the HSPICE model. A Fourier spectrum of this signal is shown in Figure 5. (This transform was performed using an
FFT with a rectangular windowing function, i.e., simple truncation.)
From Figure 5, both even and odd harmonics are present, reflecting
the asymmetric rise and fall times in the waveform.
The parameters of this device model can be adjusted to reflect
changes in many device parameters. In order to dramatize the vari-
1
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Figure 4: Waveform of the 50 MHz data of a 560 pin TBGA
CMOS ASIC under nominal conditions
Figure 5: Spectrum of the nominal 50 MHz data
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Figure 6: Worst casemodel waveform of the 50 MHz data signal
Figure 7: Worst casespectrum of the 50 MHz data
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Figure 8: Best casewaveform of the 50 MHz data signal
Figure 9: Best case spectrum of the 50 MHz data signal
210
amined analytically. In particular, we examine effects of voltage
level, temperature, and process. In Figure 10, each of these parameters is separately set to its best case value, with the remaining
device parameters at worst case values and the data signal is calculated with the HSPICE model. These parameters values are given in
Table III. In Figure 10, for each harmonic peak in the spectrum, the
Table I: TBGA ASIC model arameters used
Cl
ature
Voltage
I
1 3.515 V
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1 3.3 v
1 3.085 v
ability of the spectral content that is possible, some of these device
variables are altered to their extremes. Figure 6 and 7 illustrate the
time waveform and spectrum obtained when all of these parameters
are set to their worst case extreme conditions of process variability,
temperature, voltage, etc.
Figures 8 and 9 illustrate the waveform and spectrum of this same
data I/G signal when the device parameters are set to their best case
conditions of process variation, temperature, voltage, etc. It is apparent by visual examination that the waveforms exhibit differences
in DC excursions, ringing, and rise and fall times. The spectral
differences reflect this, especially in the higher order harmonics.
Each parameter change alters the output waveforms differently.
Voltage effects can cause spectral deviations by modifying the output amplitudes, which may influence slew and cause spectral
changes at the source. Temperature excursions cause electron mobility and slew rates to change. As a consequence, this alters the
output impedance of the drivers during transition and on/off states.
Process effects which modify electron mobility, also influence voltage thresholds, output impedance, and other output signal characteristics.
A summary of these spectral differences between extremes of total
worst and best cases of the data signal of this CMOS ASIC are
shown in Table II.
The effect of individual model parameter variations can also be ex-
Table II: Summary of Data Spectral Differences due to
Variations of CMOS ASIC Processand Operating Conditions
Best Case
Worst Case
Worst Case
Freq./
Magnitude
/Best Case
Magnitude,
Harmonic
Ratio in dB
i/Hz
V/Hz ’
No.
..I
50 MHz; lx
2x
3x
4x
5x
6x 1
7x
8x
9x
10x
11x
12x 1
13x (
3555.94
2.60
979.39
185.36
684.52
148.24 1
318.85
143.96
315.56
111.19
315.56
115.31 I
139.13 1
19x )
38.16 1
lr ~~
II
211
4962.5 1
4.24
1386.74
87.45
1012.95
72.54 1
480.90
68.95
589.81
42.18
589.81
42.80 1
777m I
Table III: Model Parameter Values Used to Obtain Results
spectral value is compared to the spectral value of the worst case.
The dominant device parameter is the manufacturing process, i.e.,
weak process versus strong. Even at lower harmonic frequencies,
process may produce between 3 and 7 dB variation between one
ASIC device and another in data signal harmonic amplitude. At the
higher harmonics, this variation may be as high as 18 dB. The second most dominant device parameter is junction temperature. Voltage has the least effect, except at a single high harmonic frequency.
IV. CONCLUSION
Variations in process, temperature, voltage, and other conditions can
cause significant variations in the spectral content of signals from
modern, fast edge rate semiconductor devices. This variation has
been shown from analytical SPICE device models to be as great as
18 dB at the higher order harmonic frequencies of the specific 560
pin TBGA CMOS ASIC examined.
It is demonstrated that the spectral content cannot be bounded by
modeling signals as symmetric trapezoidal waveforms, because such
simple models do not predict the even harmonic frequency content
that is present in the typical ‘ITL data waveform. The asymmetry
that produces even harmonics is inherent in TTL I/O device physics,
i.e., the positive and negative transition times may be different.
2.89
4.23
3.02
Often, EhJI engineering focuses on the electromagnetic aspects of
-6.52
interference mitigation and compliance,.i.e., coupling, shielding, etc.
3.40
Less attention is given to the environment of the active IC devices in
-6.21 11 the circuitry. Since the source of radiated emission energy from
high speed digital circuitry is usually the active semiconductor de3.57
vices driving the circuitry, then variability in seemingly identical
-6.39
components may cause unforeseen variability in radiated emissions.
5.43
This is a variation in the potential for EM1 that may he important,
-8.42
especially in systems with low margin.
5.43
-8.61
Lack of understanding of some of the potential for variabilities in
R 66
seemingly identical components may lead to compliance testing with
components that behave significantly differently from components
that are placed in the field.
Indeed, these variations may cause
unforeseen inconsistencies from unit to unit.
2.
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14x
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11x
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C.R. Paul, “A Comparison of the Contributions of CommonMode Currents and Differential-Mode Currents in Radiated
Emissions,” IEEE Transactions on Electromagnetic Compatibility, Vol. 31, No. 2, pp. 189-193, May 1989.
C. R. Paul, introduction to Electromagnetic Compatibility,
John Wiley & Sons, Inc., New York, 1992.
James L. Drewniak., T. Hubing, T. Van Doren, “Investigation
of Fundamental Mechanisms of Common-Mode Radiation from
Printed Circuit Boards with Attached Cables,” IEEE International Symposium on Electromagnetic Computibility, 1994, p.
110-115.
D. M. Hockanson, C. W. Lam, J. L. Drewniak, T. H. Hubing,
T. P. Van Doren, “Experimental and Numerical Investigations
of Fundamental Radiation Mechanisms in PCB Designs with
Attached Cables,” IEEE International Symposium on Elrctromagnetic Compatibility, 1996, pp. 305-310.
D. M. Hockanson, J. L. Drewniak, T. H. Hubing, T. P. Van
Doren, F. Sha, A. Testa, “Investigation of Fundamental EMI
Source Mechanisms Driving Common-Mode Radiation from
Printed Circuit Boards with Attached Cables,” IEEE Transactions on Electromagnetic Compatibility, vol. 38, No. 4, pp.
557-566, November 1996.
HSPICE Users Manual, Vol. II: Elements und Device Models,
Ver. 96.1, META-SOFTWARE, Inc., Campbell, CA, Feb. 1996
Jacob Millman, Arvin Grabel, Microelectronics, McGraw-Hill,
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N. Ballay and B. Baylac, “Analytical modeling of depletionmode MOSFET with short- and narrow- channel effects,” Proceedings of the IEEE, Vol. 128 Part. I, No.6, pp. 225-238, December 1981
lx
Figure 10: A comparison in dB at each harmonic frequency
showing the maximum effect of individual device model
parameters relative to the worst case results.
Future work is intended to experimentally examine the specific 560
pin TBGA CMOS ASIC discussed here to verify some aspects of
variabilities. In addition, consideration will be given to their direct
effects on radiated emissions, along with variabilities due to part
location on a circuit board and software program dependencies.
ACKNOWLEDGMENTS
We would like to acknowledge LSI Logic Corporation for use of
their SPICE models, as well as their generous assistance in understanding the behavior of the MOSFET device itself. In addition, we
would like to acknowledge the support and assistance of our colleagues and associates.
REFERENCES
1.
Robert Crawhall, “EMI Potential of Non-Periodic Signals”,
IEEE International Symposium on Electromagnetic Compatibility, 1992, pp. 334-339.
212