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A New VLSI Implementation of a CMOS Frequency Synthesizer for SRD Applications Radu Gabriel Bozomitu, Vlad Cehan, and Constantin Barabaşa Telecommunications Department, Faculty of Electronics, Telecommunications and Information Technology, “Gh. Asachi” Technical University, Carol I No.11 Av., 700506, Iaşi, Romania [email protected], [email protected], [email protected] Abstract: In this paper, a new VLSI implementation of a CMOS frequency synthesizer for short range devices (SRD) applications is presented. The proposed circuit is based on PLL architecture which has a frequency divider circuit in the loop. The frequency synthesizer circuit uses a fast-acquisition PLL, which determines the improvement of the pull-in range and of the acquisition time of the circuit, providing a frequency synthesis in the range of (850 – 950)MHz. The CMOS frequency synthesizer proposed in the paper uses a 1MHz comparison frequency, providing the same frequency resolution. The simulations performed in a 0.13m CMOS technology confirm the theoretical results. 1. INTRODUCTION The frequency synthesis consists in the generation of one or more frequencies from one or a few reference sources. The fine frequency resolution, low spurious signals, accuracy and stability are the most important for these devices [1] – [7]. The frequency synthesizers are an essential part of any modern communication system. The paper describes the design of an indirect analog synthesizer circuit in the range of (850 – 950)MHz with 1MHz frequency resolution for SRD applications, implemented in a 0.13m CMOS technology. 2. PRINCIPLE OF FREQUENCY SYNTHESIS In Fig. 1 is presented the block diagram of the proposed frequency synthesizer circuit. The circuit is based on the PLL architecture which has a frequency divider (with a division rate between 0 – 999) in the loop. In order to increase the frequency operation range, the frequency synthesizer circuit uses a fastacquisition PLL. This technique uses two first order low-pass filters on the loop, commanded by a lock indicator circuit (LIC), designed so that their poles are f p 2 . When the circuit fulfilling the condition, f p1 is powered on, the LPF1 is used, having a higher cutoff frequency and determines a fast acquisition of the PLL and increases the capture range of the circuit. When the PLL is locked, the lock indicator circuit induces the change of the LPF1 with LPF2. Since the LPF2 has a smaller cut-off frequency, this technique increases the spectral purity of the signal generated by the voltage controlled oscillator (VCO). The frequency resolution of the CMOS frequency synthesizer is equal to the reference frequency of 1MHz applied at the circuit input. The loop bandwidth (provided by the LPF2) has to be significantly lower than the reference frequency, which results in a relatively slow switching. The fast acquisition technique used in the proposed circuit diminishes the trade-off between the frequency resolution of the PLL and the switching speed. The proposed frequency synthesizer (Fig. 1), based on PLL architecture is composed by a phase comparator, implemented with a Gilbert cell, two first order low-pass filters, a voltage controlled oscillator having ring architecture and a frequency divider circuit. The LPF used in the frequency synthesizer architecture shown in Fig. 1 provide the following transfer function: F ( s) p s p (1) Vcom In equation (7), ωn is the natural frequency of the loop, given by: LIC LPF2 Vin Vctrl Vcom V0 Vout n N VCO ÷N 1 2 N p K PD KVCO 1 2 (8) N K p 1 2 n p where ωp represents the dominant pole of the LPF. According to Fig. 1 the transfer function of the proposed frequency synthesizer can be written: (2) In equation (2), the open loop transfer function is written as the product of forward transfer function G(s) and feedback B(s). The forward transfer function is: K (3) G( s ) F ( s ) s where K is the total gain of the loop. The total gain of the loop can be expressed as: (9) (10) Illustrated in Fig. 2 for several values of ζ and a constant ωn, the step response exhibits severe ringing for 0.5 . In view of process and temperature variation of the loop parameters, ζ is usual chosen to be greater than 2 2 or even 1 to avoid excessive ringing. The choice of ζ entails some trade-offs. From (9) results that as ωp is reduced to minimize the ripple on the control voltage, the stability degrades. The equation (9) shows that the ζ is inversely proportional to K PD KVCO . For the second order system, 0.5 ; a typical (4) K K PD KVCO F (0) [s ] where KPD[V/rad] is the gain of the phase comparator, KVCO[(rad/s)/V] is the VCO sensitivity and F(0) is the d.c. gain of the LPF. For the proposed circuit, F (0) 1 . -1 value for this factor is 2 2 , which determine an optimal plat frequency response (Fig. 2). For this reason, the parameters K and ωp cannot be chosen independently. So, for 2 2 , we obtain: Considering N 1 in Fig. 1, the feedback transfer function can be written: B( s) 1 N K N p Thus, from (8) and (9) we obtain: Fig. 1. Frequency synthesizer circuit based on PLL architecture G( s) 1 G ( s ) B( s ) and ζ is the damping ratio, given by: LPF1 H ( s) p K PD KVCO ζ = 0.2 (5) ζ = 0.5 Using (3) – (5) in equation (2), the transfer function of the proposed frequency synthesizer can be written: H ( s) KF ( s ) s KF ( s ) / N (6) N n2 s 2 2n s n2 2 2 t Using (1) in equation (6) we obtain: H ( s) (7) Fig. 2. Underdamped response of a second-order system for various values of ζ p 2K K ; n 2 N N (11) We conclude that the type I PLL suffers from trade-offs between the settling speed, the ripple on the control voltage (i.e., the quality of the output signal), the phase error, and the stability. Note that from equation (7), H ( s ) N as s 0 . We observe that phase or frequency changes at the input result in an N-fold change in the corresponding output quantity. From the denominator of equation (7), we observe that frequency division in the loop manifests itself as division of KVCO by N. As far as the poles of the closed-loop system are concerned, we can assume the oscillator and the divider from a VCO with an equivalent gain of KVCO N . For the VCO/divider cascade, the input comparison frequency can be written: KVCOVctrl 0 KVCO (12) in 0 V N N N ctrl where ω0 is the free running frequency of the VCO. From equation (12), the VCO output frequency can be written: (13) out 0 KVCOVctrl Thus, from equation (13), the deviation frequency provided by VCO is: (14) KVCOVctrl When the PLL is locked, in order to obtain a higher spectral purity of the VCO output signal, the term given by (14) has to be minimized, which involves: (15) Vctrl 0 Since the comparison frequency is 1MHz, the ripple of the LPF output signal has a frequency equal to 2MHz and its peak-to-peak value, Vctrl(pp), has to be minimized. The ripple of the control voltage determines a frequency modulation of the signal provided by the VCO. The frequency modulation index can be written: (16) m where ωm is the frequency of the control voltage ripple. In order to obtain a higher spectral purity of the signal provided by the VCO, the frequency modulation index has to be 0.5 . Thus, for a better spectral purity of the output signal, the values of KVCO and Vctrl(pp) parameters must be chosen to accomplish the following relation: KVCO Vctrl ( pp ) 0.5 m (18) 3. VLSI IMPLEMENTATION OF THE PROPOSED FREQUENCY SYNTHESIZER CIRCUIT 3.1. The phase comparator and low-pass filter The phase comparator (PC) circuit shown in Fig. 3 is implemented on the base of Gilbert cell. The phase comparator is represented by transistors M1 – M6 and the LPF are simple RC filters implemented with R1, R2 resistors ( R1 R2 R ) and C1, C2 capacitors. In fast acquisition, the C1 capacitor is used, and the dominant pole of the LPF1 is given by: 1 (19) f p1 2 (2 RC1 ) When the PLL is locked, the C2 capacitor is added, and the dominant pole of the LPF2 is given by: 1 (20) f p2 2 2 R C1 C2 Vdd R2 C1 SW C2 M12 Vcom M13 VINP1 M1 Gnd M2 M3 M4 Gnd VOP VINN1 VON VINP2 M5 M6 Gnd VINN2 Rlin Ibias M7 Using (14) in (16) we obtain: KVCOVctrl ( pp ) m LPF R1 M8 M9 M10 M11 Gnd (17) Fig. 3. The phase comparator and the LPF implemented on the base of Gilbert cell In order to provide an output signal with a common mode suitable for the next stage (represented by the VCO) a buffer stage implemented with M10 – M13 transistors is used. Using this buffer stage, the output common mode voltage provided by the PC and LPF is about 2.1V. The bias current of this stage is Ibias = 400A. 3.2. Voltage controlled oscillator Trade-offs among speed, jitter, and power dissipation have to be considered in VCO design. The VCO is configured as a ring oscillator with an even number of stages so that provides a performing frequency operation. Since a four-stage oscillator does not achieve the required speed in our technology, we utilize only two stages (Fig. 4). In Fig. 5 the electric scheme of the Gm used in the ring oscillator in Fig. 4 is shown. The bias current of the VCO stage is 300A. Ib1 Ib2 VOP2 U1 Ibias + - + VON VcP VcN - Ibias VOP VOP1 VON VcP VcN VON1 Gm VCN Fig. 4. VCO as a ring oscillator Vdd R3 R2 R1 Gnd M2 R4 VOP VON M7 VINP M1 M5 Gnd M8 M6 Gnd Gnd X VINN VctrP M3 Gnd M4 VctrN Ibias M9 M10 The operation of the proposed circuit in Fig. 1 can be explained by using the following simulations results made in 0.13µm CMOS process. The circuit uses a reference frequency f in 1MHz , the free In Fig. 6, the PC characteristic of the proposed frequency synthesizer circuit for 900MHz operation frequency is presented (KPC = 107mV/rad). VON2 VCP 4. SIMULATIONS RESULTS running frequency of the VCO is f0 900MHz , and the frequency division rate is between (850 – 950) in order to generate the frequencies in the range of (850 – 950)MHz with a resolution of 1MHz. U2 VOP Gm The Gm circuit shown in Fig. 5 provides relatively low equivalent impedance from X to ground, allowing the positive feedback around M5 – M6 to contribute significant gain (even at low bias currents) and phase shift. The cross-coupled transistor pair (M5 – M6) exhibits a negative resistance of -2/gm, a value that can be controlled by the bias current. A negative resistance placed in parallel with a positive resistance increases the output impedance of the stage and, thus, the delay. Thus, the VCO output frequency can be varied over a wide range with little degradation in amplitude. The buffer output stage implemented with M7 – M8 transistors in Fig. 5 provides two differential output signals, having 3.1V common mode voltage. M11 Gnd Fig. 5. Electric scheme of the Gm from ring oscillator The VCO characteristic is shown in Fig. 7. According to Fig. 7, the VCO gain (the slope of the VCO characteristic) is about 3.5GHz/V, fulfilling the condition given by (18) From this VCO characteristic it is obvious that in the interest dynamic range ((850 – 950)MHz), the operation of the proposed VCO is linear. The PC characteristic has an offset due to parasitic capacitances, which are not neglected at higher frequency. In the following the operation of the proposed frequency synthesizer circuit is analyzed by simulation for three frequencies in the range: 850MHz, 900MHz and 950MHz. The output frequency provided by the circuit is given by the frequency division rate (N) of the frequency divider circuit, implemented at the system level, using an AHDL model. Vctrl [mV] 200 150 LPF1 100 LPF2 50 0 0 50° 100° 150° 200° [Δφ] -50 -100 -150 Fig. 8. Error voltage provided by the two LPF of the frequency synthesizer circuit (fout = 900MHz) -200 Fig. 6. Phase comparator characteristics (KPD=107mV/rad) freq ( Hz ) Fig. 9. Magnitude spectrum of the signal provided by the VCO (fout = 900MHz) Fig. 7. VCO characteristic (KVCO = 3.5GHz/V) In order to obtain the output frequencies in the (850 – 950)MHz range, the frequency division rate is varied between 850 to 950, respectively, with a resolution of 1MHz. The proposed circuit uses two low-pass filters, the first – to increase the pull-in range of the PLL, and the second – to ensure a higher spectral purity of the signals provided by the VCO. The commutation between these two filters is realized after 50μs (by the LIC), time interval which assures the lock of the loop. In the following the calculation of the two lowpass filters dominant poles is exemplified. According to the first equation (11) and for the calculated values of the PC and VCO gains, the value of the dominant pole which assures a fast acquisition of the loop is: f p1 132.5kHz . In order to assure a higher spectral purity of the signal provided by the VCO, the second dominant pole of the LPF is f p 2 5kHz . In Fig. 8, 10 and 12 are presented the differential error voltages provided by the two differential lowpass filters placed on the analog multiplier circuit (implemented with a Gilbert cell) for the following division rates: N 900 , N 850 and N 950 . From these figures, we observe a fast acquisition of the loop (in 50μs) and after that, the commutation between the two low-pass filters assure a higher spectral purity of the generated signal. In Fig. 9, 11 and 13 are presented the magnitude spectrums of the signals provided by the VCO for different frequencies operation of the proposed circuit: in the middle and at the extremities of the capture range. LPF1 LPF1 LPF2 LPF2 Fig. 10. Error voltage provided by the two LPF of the frequency synthesizer circuit (fout = 850MHz) Fig. 12. Error voltage provided by the two LPF of the frequency synthesizer circuit (fout = 950MHz) freq ( Hz ) Fig. 11. Magnitude spectrum of the signal provided by the VCO (fout = 850MHz) freq ( Hz ) Fig. 13. Magnitude spectrum of the signal provided by the VCO (fout = 950MHz) 5. CONCLUSIONS REFERENCES In this paper, a new VLSI implementation of a CMOS frequency synthesizer circuit for short range devices (SRD) applications has been presented. The frequency synthesizer circuit uses a fastacquisition PLL, which determines the improvement of the pull-in range and of the acquisition time of the circuit, providing a frequency synthesis in the range of (850 – 950)MHz with higher spectral purity. The trade-off between the frequency resolution, the switching speed and the capture range has to be considered in any frequency synthesizer circuit design. The CMOS frequency synthesizer proposed in the paper uses a 1MHz comparison frequency, providing the same frequency resolution. The simulations performed in a 0.13m CMOS technology confirm the theoretical results. [1] Floyd M. Gardner, “Phaselock Techniques”, John Wiley & Sons, Inc., 2005; [2] W. F. Egan, “Frequency Synthesis by Phase Lock”, 2nd ed. New York: Wiley, 1999; [3] John Rogers, Calvin Plett, Foster Dai, “Integrated Circuit Design for High-Speed Frequency Synthesis”, Artech House, Inc., 2006; [4] V. Manassewitsch, “Frequency Synthesizers“, 3rd ed. New York, 1987; [5] Věnceslav F. Kroupa, “Direct Digital Frequency Synthesizers”, IEEE Press, Piscataway, NJ 08855-1331 U.S.A., 1999; [6] J. R. Smith, “Modern communications circuits”, 2nd ed., New York: McGraw-Hill, 1998; [7] B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications”, in Proc. 1997 IEEE Custom Integrated Circuit Conference (CICC), pp. 395 – 402.