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Resistance In CMOS circuits, resistances can either be passive or active. Active resistances are usually the resistance of the transistors when they are biased to operate in linear or saturation region. The passive resistors are designed and implemented with different materials on the chip. We have two types of resistors in a VLSI circuit; useful and parasitic. RESISTANCE DESIGN Resistance R * L L * A W *t What are the parameters that we have control over as a designer? W, L and (some control on selection of ). Different resistivity, , is achieved by using diffusion, metal, poly, N-Well and P-Well materials. for a given material is constant and is t commonly called the sheet resistance Rs of a material. L R Rs * W Since thickness is process dependent then Now, if L=W, as with the case of a square shape, then R= Rs . In the above diagram both squares have the same resistance. R is then measured as / Page 1 of 15 Examples of evaluating resistance with the help of square shapes are: For irregular width, R_corner = Rs (0.46+0.1a) where a = W1/W2 Other factors:- Variation in resistivity across the resistor depth, Temperature, Voltage and process variations may affect the total resistance. For example: Resistor values are a function of temperature R(T ) Ro [1 TC1 * dT TC 2 * dT 2 ] , dT = T – Tnominal at 25* Celcius Constants taken from the process manual The resistance is layout dependent and is calculated from sheet resistance L , w is the width and w is the process variation factor. R( L) RS * ( w w) The resistance values are a function of the voltage R(V ) RO [1 VC * dV VC 2 dV 2 ] dV is change in voltage Constants taken from the process manual Page 2 of 15 STRUCTURAL OVERVIEW OF A RESISTANCE AND ITS ASSOCIATE PARASITIC RESISTANCES For each metal, Rc is the contact resistance, and is measured as Rc/Area. Typical resistance values. For 0.5u process: Values are per square N+ diffusion : 70 P+ diffusion : 140 Polysilicon : 12 Polycide:2-3 / / / / M1: 0.06 / M2: 0.06 / M3: 0.03 / P-well: 2.5K / N-well: 1K / Page 3 of 15 Active resistors These resistors are made with transistors. The resistors are made up from two components: The channel resistance and the drain and source resistance plus the contact resistance. Conductance in Linear & Saturation Regions: In the linear region, 2 I d V Bn (V gs Vt ), neglecting ds Vds 2 Resistance of channel, Rchannel = 1 Bn (V gs Vt ) Vds V gs Vt as Vds 2 is very small Similarly for the saturation region I d 0 (neglecting channel modulation effect) Vds If the channel length modulation is not neglected, then Conductance = n 2 [Vgs Vt ]2 Resistance = 2 n [Vgs Vt ]2 Conclusion: In saturation region, resistance between Drain and Source is usually a high value. Page 4 of 15 1) Drain/ Sources Resistance: RD(S) = Rsh * number of squares + contact resistance. The value of the drain and source resistances should be added to the channel resistance,. A more accurate resistance, Rchannel, is given below taking channel length modulation and V2 into account RCH = -------------------------------1 --------------------------------- ' W K' ----- VGS – VT –V DS L 2) Channel Resistance: This depends on the region of operation: RC H = -------------------------2 --------------------------2W K' ----V – VT L GS Contact resistance: The contact resistance Rc is defined as Rc= c/A where c is the specific contact resistance and A is the contact area. Smaller contacts of higher impurities will increase the resistance. Rc assumes that the current through the contact flows uniformly. However, there is a current crowding phenomena around the corners and leading edges of the contact. Typical Contact resistance values for 0.5µ process: Contact resistance: PolyI to MetalI Via resistance: Metal I to Metal II Via resistance: Metal II to metal III 50 1.5 1. Page 5 of 15 CAPACITIVE LOADS IN A CMOS INVERTER Assume that we have an inverter driving another equivalent inverter. The second inverter can be considered as a capacitive load as shown below. The first order model capacitances include the drain capacitances of the driver and the gate capacitances of the driven stage. Cw is the wiring capacitance. Note: We usually neglect Cgsp and Cgsn while doing hand analysis of such circuits. C L Cdp Cdn C gp C gn Cw Page 6 of 15 TRANSIENT ANALYSIS OF CAPACITIVE CIRCUITS Of importance is the transient behavior of the inverter and the speed at which we are able to drive such an inverter. We assume a step is applied to the input of the inverter. As shown below the pmos is off and the nmos initially starts in saturation. At this moment the Vdsn is high and the nMOS is in Saturation. As the load capacitor discharges then Vout decreases until Vds =Vgs-Vt when the nMOS enters the linear region. Therefore there are two stages in calculating the fall time of this inverter. Definitions In response to a step input, the rise and fall times at the output are defined as: Time taken for any signal to rise from 10% to 90% of Vdd is called Rise Time or tr. Time taken for the signal to fall from 90% to 10% of Vdd is called Fall Time or tf. Now assume that a step input is applied to an inverter Page 7 of 15 The propagation delay td is obtained by the 50% line as shown in the figure above. And the propagation delay td can be calculated using the following equation: td t phl t plh 2 Page 8 of 15 The fall time, tf We will analyze the fall time in two steps, ie when the nmos is in saturation and then when it is in linear region. Initially when the step input is applied, the nMOS is on and in saturation as VGS -Vtn < VDS, now ignoring channel modulation, we have ID Vi = 5 N n Vin Vi = 4 n Vi = 3 n VDDVT (VDSAT) I DN n VD D V o [Vgs Vtn ]2 2 also, C.dVds I CAP dt Page 9 of 15 Merging the two equations, n 2 t2 [V gs Vtn ]2 dt t1 CdVds dt 0.9VDD 2C.dVds [Vgs Vtn ]2 VDDVtn n tf1 2C L (Vtn 0.1Vdd ) n (Vdd Vtn ) 2 Similarly, for tf2, we have the transistor in the linear region, t2 VDDVtn t1 0.1VDD tf2 = dt Fall time then is given by C.dVds n [Vgs Vtn ]Vds V 2 ds tf = tf1 + tf2 RISE AND FALL TIME EQUATIONS In order to get tfall (tf) we add tf2 and tf1. Following many manipulations we get: tf 2C L V ( n 0.1) [ 0.5 ln( 19 20n )] , n tn nVdd (1 n ) (1 n ) Vdd Grouping all the constants into K, the fall time is given as: CL tf K , where K is a constant between 3 and 4 depending on the process nVdd If the same analysis are done for the trise (tr) we have tr K CL pVdd trise and tfall, are dependent on W/L, CL and Vdd. We can only change CL and W/L through design. VDD depends on the process. In order to equalize trise and tfall, make W p rWn where r n p Page 10 of 15 Design Guidelines: Keep the rise and fall times equal and smaller than the propagation delay of the inverter. This will have an impact on speed and the power consumption of the circuit. Propagation Delay The following factors influence the delay of the inverter: • • • • • Load Capacitance Supply Voltage Transistor Sizes Junction Temperature Input Transition Time For any given process, we can express the delay (td) for an inverter as: tphl = Cload p(VDD Vt, p ) [ tplh = Cload n(VDD Vt, n ) [ 2 Vt , p 4(VDD Vt, p ) + ln ( VDD Vt , p 2 Vt, n + ln ( VDD Vt, n 1) ] 1) ] VDD 4(VDD Vt , n ) VDD Since N, P are design parameters and VDD is technology dependent while n and p are constants for a given process then the delay can be expressed as: tphl An CL n tplh Ap , CL p The coefficients ‘An’ or ‘Ap’ is obtained for a given process from analytical calculations or better through SPICE Simulation. That is, for a known CL and n, we usually determine td(spice) for either tphl or tplh and then determine An or Ap. Once An and Apare obtained, it can be used repeatedly for the same process. ie: An t d spice n CL Summarizing then, tphl = Cload p(VDD Vt, p ) [ tplh = Cload n(VDD Vt, n ) [ 2 Vt , p VDD Vt , p 2 Vt, n VDD Vt, n + ln ( + ln ( 4(VDD Vt, p ) VDD 4(VDD Vt , n ) VDD 1) ] 1) ] Page 11 of 15 tPHL = CL A' P n VDD tPLH = CL A' n p VDD CL ( – 2) ( 1 + p ) tr = -------------------------------------- ---------------------------- + ln (19 + 20p ) K PVDD ( 1 + p ) (1 + p ) 4C L A'P tr = --------------------KP VDD Assume normalized voltages vin= Vin/ VDD vo= Vo/ VDD n = VTN/ VDD p = VTP/ VDD tPHL and tf decrease with the increase of W/L of the NMOS tPLH and tr decrease with the increase of W/L of the PMOS The delay of the inverter increases with the increase of the input transition times tr and tf Page 12 of 15 Effect of the input Slope All the previous equations involve the use of a step unit signal as input. However real-life signals are often ramps. In that case we will use the following equation to incorporate the effect of the slope of tr and tf: First Order Model t t phl t 2 phlstep ( r )2 2 t plh t 2 plhstep ( td tf 2 )2 1 (t phl t plh ) 2 Alternative Delay Model (for the rise time) t V tdr tdrstep f (1 2 p) , p t Vdd 6 ALTERNATIVE DELAY (tp) FORMULA For the short channel transistor the following delay equation is also used: C 1 tp L ( ) 2 P N Also in the short channel model the source resistance becomes important and it has to be taken into account, since it affects both the current and the voltage threshold. Yet another model tp = CLVDD A(VDD VT ) Where A is a constant and α is another constant between 1.4 and 2 depending upon the technology us Page 13 of 15 PLEASE NOTE: All models presented here are approximate; we only use them as guidelines when implementing circuits. Accurate delays are obtained only through SIMULATION Assignment #4 VLSI Design, COEN 451 A CMOS inverter (INV1), with a physical layout shown in Fig.1, drives a similar inverter, and operates at a supply voltage of 3.3V. a. Determine the delay of the inverter INV1. b. What will be the maximum speed of operation of INV1 if it drives ten similar inverters c. One of the methods to speed up the operation is to increase the size of the driver. Determine the W/Ls of the PMOS and the NMOS transistors of INV1 so that the speed in part (b) is doubled, assuming that the supply voltage has been reduced by 10%. (Hint: Use twice the diffusion capacitance of Fig.1). d. Determine the dynamic power dissipation of the inverter (INV1) for part c. Use CMC technology parameters CMOSIS5B Page 14 of 15 M1 VDD 3.0 µ Vin 4.0µ 2.0µ Vout 2.5µ M1 6.5 µ 2.5 µ 3.0 µ Gnd 0.5 µ Fig. 1 Inverter for design Page 15 of 15