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Design and Evaluation of Cascode GaN FET for Switching Power Conversion Systems Dong Yun Jung, Youngrak Park, Hyun Soo Lee, Chi Hoon Jun, Hyun Gyu Jang, Junbo Park, Minki Kim, Sang Choon Ko, and Eun Soo Nam In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normallyoff operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metaloxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normallyon D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of 250 μA, and an on-resistance of 331 mΩ. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications. Keywords: Normally-on GaN FET, Cascode GaN FET, Boost converter. Manuscript received Mar. 17, 2016; revised Nov. 7, 2016; accepted Nov. 29, 2016. This work was supported by the R&D program of MSIP/COMPA (Next Generation High Efficiency 3-Dimensional Convergence Power Conversion Module). Dong Yun Jung (corresponding author, [email protected]), Youngrak Park (raferer @etri.re.kr), Hyun Soo Lee ([email protected]), Chi Hoon Jun ([email protected]), Hyun Gyu Jang ([email protected]), Junbo Park ([email protected]), Minki Kim ([email protected]), Sang Choon Ko ([email protected]), and Eun Soo Nam ([email protected]) are with ICT Materials & Components Laboratory, ETRI, Daejeon, Rep. of Korea. This is an Open Access article distributed under the term of Korea Open Government License (KOGL) Type 4: Source Indiction + Commercial Use Prohibition + Change Prohibition (http://www.kogl.or.kr/news/dataFileDown.do?dataIdx=71&dataFileIdx=2). 62 Dong Yun Jung et al. I. Introduction Recently, as consumers have demanded highly efficient and smaller handheld devices, and as communications and consumer electronics advance in technology, a high-efficiency power conversion system with a higher operating frequency than that of the current systems has become a significant research focus. To satisfy these requirements, many research groups have studied the GaN power semiconductor as a promising device with a high switching frequency, low on-resistance, low switching loss, and high power density [1]–[10]. However, a GaN-based lateral field-effect transistor (FET) is a normally-on device with a gate threshold voltage (Vth) under 0 V [1]–[2]. For safety and reliability, a number of techniques (including gate recess, p-type III-nitride gate, fluorine plasma ion implantation, gate-controlled tunnel junction, and clamp circuit integration) have been proposed and reported to realize normally-off operation [4]–[10]. Despite having a negative Vth, depletion-mode (D-mode) FETs usually have a lower on-resistance, a smaller junction capacitance, and a higher power density than enhancementmode (E-mode) FETs. To take advantage of D-mode FETs and still operate the circuit in a normally-off mode, researchers devised a cascode structure with an integrated E-mode Si metal-oxide-semiconductor FET (MOSFET) and D-mode GaN FET [11]–[16]. In this paper, Section II presents the design and fabrication of a D-mode GaN FET device, and Section III presents an analysis of a normally-off cascode GaN FET circuit. Finally, Section IV presents the design and verification results of a boost converter to further evaluate the performance of the cascode GaN FET. II. D-Mode GaN FET Device © 2017 For mass production, it is necessary to fabricate large-area ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 2 μm 3 μm Au plating Source 20 μm Gate SiN Al2O3 (30 nm) D-mode GaN FET E-mode Si MOSFET Drain D S D G Al0.25Ga0.75N barrier (20 nm) G GaN buffer (4 μm) S Silicon substrate Fig. 2. Basic schematic of cascode GaN FET for normally-off operation. (a) 0.10 Drain 0.09 Gate 0.08 0.07 IDS (A) 0.06 Source 0.05 (b) 0.04 Fig. 1. (a) Cross-sectional view and (b) fabricated device of Dmode GaN FET. 0.03 GaN power devices on Si substrates. Figure 1(a) shows the cross-sectional structure of the proposed D-mode GaN FET on a Si (111) substrate. The epitaxial structure consists of a 4-μmthick GaN buffer layer grown on highly resistive Si, on which a 20-nm-thick Al0.25Ga0.75N barrier layer is grown. In order to reduce the reverse gate leakage current and obtain a higher forward oxide breakdown, 30-nm aluminum oxide is grown using atomic layer deposition. An ohmic metal stack of Ti/Al/Ni/Au is optimized to reduce the ohmic contact resistance at an annealing temperature of 900 ºC. To suppress current collapse and protect the device from an unreliable plating process [17], the device was passivated with an 800-nm Si3N4 layer deposited by plasmaenhanced chemical vapor deposition at a high frequency power of 50 W and temperature of 230 ºC using SiH4 and NH3 as source gases. The Au plating of 3 μm on the source and drain electrodes is implemented to drive a high current. The gate-drain spacing (LGD), gate-source spacing (LGS), and gate length (LG) of the device is 20 μm, 2 μm, and 3 μm, respectively. The device has a total gate width of 50 mm. Figure 1(b) shows the finished D-mode GaN FET with lateral dimensions of 3.2 mm × 1.8 mm. III. Normally-off Cascode GaN FET Figure 2 shows the cascode configuration of the integrated D-mode GaN FET in series with a low-voltage E-mode Si MOSFET. Although the threshold voltage (Vth) of the D-mode ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 Vth shift D-mode GaN FET Cascode GaN FET 0.02 0.01 –5.5 V 4.5 V 0.00 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 VGS (V) Fig. 3. Measured Vth comparison between D-mode and cascode GaN FET. GaN FET is negative, the overall Vth of the cascode FET shifts to a positive value. The measured Vth of the D-mode GaN FET and cascode GaN FET at an IDS of 50 mA are –5.5 V and +4.5 V, respectively, as shown in Fig. 3. Figure 4 shows the operation point for switching of the fabricated D-mode GaN FET and cascode FET. In the on-state, the gate-source voltage of the cascode FET (VGS,cascode) is typically 10 V, and the gatesource voltage of the D-mode GaN FET (VGS,D-mode) is ideally 0 V. The cascode FET operates on the linear portion of the FETs. On the other hand, in the off-state, VGS,cascode is 0 V, and VGS,D-mode becomes lower than Vth,D-mode. The drain-source voltage of the cascode FET (VDS,cascode) is located in the cutoff area of the FET. To design a cascode GaN FET, we must choose the right specification of the E-mode Si MOSFET. If the drain-source voltage of the E-mode Si MOSFET (VDS,Si) is higher than the breakdown voltage (BV) of the E-mode Si MOSFET (BVSi) during the off-state, the Si MOSFET will fail. Even if VDS,Si is lower than BVSi, if VDS,Si is higher than the absolute value of the minimum gate-source voltage of the D-mode GaN FET (VGS,mim,D-mode GaN), the D-mode GaN FET will fail. In addition, in the off-state, because VGS,D-mode GaN is lower than Vth of the DDong Yun Jung et al. 63 7.0E-03 7 ON 5 6.0E-03 VGS,D-mode = 0 V VGS,cascode = 10 V 5.0E-03 4 4.0E-03 3 3.0E-03 2 1 0 2.0E-03 VGS,D-mode < Vth,D-mode VGS,cascode = 0 V OFF 0 100 200 300 VDS (V) 400 500 Leakage current (A) Forward cuurent (A) 6 Drain 1.0E-03 Source 0.0E+00 600 Gate Fig. 7. TO-254 packaged cascode GaN FET. Fig. 4. Operating point of fabricated D-mode and cascode GaN FET for switching. I-V curve 7 IDS (A) IDS = 6.04 A (@VGS = 10 V, VDS = 2 V) 6 5 VGS = 0 V–10 V (1 V step) IDS (A) 4 VDS_Si VGS,max,GaN VGS,min,GaN Vth,GaN 3 2 Rds,on = 0.331 (IDS = 6.04 A, @VDS = 2 V) 1 VGS_GaN (V) 0 1 0 1 2 3 4 5 VDS (V) (a) Fig. 5. Operation range of VGS of D-mode GaN FET and VDS of E-mode Si MOSFET for cascode GaN FET. Leakage current & breakdown voltage 1.0E 03 BV = 520 V (@VGS = 0 V, IDS = 250 μA) 8.0E 04 IDS (A) IDSS,Si (µA) @VGS,Si = 0 V 6.0E 04 4.0E 04 2.0E 04 VDS,Si (V) Fig. 6. VDS,Si shift at turn-off state when IDSS,GaN > IDSS, Si. mode GaN FET (Vth,D-mode GaN), VDS,Si must be higher than the absolute value of Vth,D-mode GaN. In other words, BVSi must be higher than the absolute value of Vth of the D-mode GaN FET (Vth,D-mode GaN), and lower than the absolute value of the minimum VGS of the D-mode GaN FET (VGS,min,D-mode GaN), as follows: │Vth,D-mode GaN│ < BVSi < │VGS,min,D-mode GaN│. Figure 5 describes the operating range of VDS,Si mentioned above. In terms of the leakage current in the off-state, if the leakage current of the D-mode GaN FET (IDSS,GaN) is higher than that of the E-mode Si MOSFET (IDSS,Si), VDS,Si increases until the same leakage current flows, as shown in Fig. 6. Thus, IDSS,GaN is one of the most important parameters in developing a D-mode 64 Dong Yun Jung et al. 0.0E+0 0 100 200 300 VDS (V) (b) 400 500 600 Fig. 8. Static performance of cascode GaN FET: (a) forward I-V curve and (b) reverse leakage current and breakdown voltage. GaN FET. In addition, IDSS,Si becomes one of the key factors in selecting an E-mode Si MOSFET for a cascode GaN FET. Because VGS,min, Vth, and IDSS of the fabricated D-mode GaN FET are –35 V, –5.5 V, and approximately 1 μA at room temperature, respectively, we used a Si MOSFET with a BV of 30 V and IDSS of 100 μA at 125 ºC. Figure 7 shows the threepin TO-254 packaged cascode GaN FET with two parallel Dmode GaN FETs and an E-mode Si MOSFET. Au80Sn20 perform with a thickness of 25 μm at 300 ºC was used for die bonding, and multiple wires and ribbons were used for the ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 Table 1. Performance summary of cascode GaN FET. RL Casecode GaN FET VCC Gate pulse Gate driver Parameter ID C VDD Static R D ZD Fig. 9. Simplified resistive load test circuit for dynamic characteristics. Turn-on (@50 V, 2 A) 12 50 VDS 8 VGS 30 6 20 4 10 2 0 0 –10 0.0E+00 5.0E-07 –2 1.5E-06 1.0E-06 Time (s) (a) Turn-off (@50 V, 2 A) 12 50 10 40 8 30 6 20 4 VDS VGS (V) VDS (V) 60 10 2 VGS 0 0 –10 0.0E+00 5.0E-07 –2 1.5E-06 1.0E-06 Time (s) (b) 10 5 8 4 VDS (V) R ds,on = 0.474 Ω 2 4 0.974 V 2 1 IDS 0 0 –1 0.0E+00 BV (V) 520 Rds,on (Ω) 0.331 td,on (ns) 39.81 tr (ns) 48.36 Dynamic td,off (ns) 57.67 tf (ns) 17.05 Rds,on (Ω) 0.474 VDS = 50 V, IDS = 2 A 1.0E-04 2.0E-04 Time (s) (c) package frame in order to achieve a high power density and low parasitic inductance. Figure 8 shows the static performances of the packaged cascode GaN FET. The drain-source current of the cascode GaN FET (IDS) is 6.04 A at a drain-source voltage (VDS) of 2 V and a gate-source voltage (VGS) of 10 V. Its static drain-source on-resistance (Rds,on) is 331 mΩ. The BV is approximately 520 V at a VGS of 0 V and leakage current of 250 μA. Figure 9 depicts a simplified resistive load test circuit used to extract the dynamic characteristics of the TO-packaged GaN FET. A variable load power resister (RL) is controlled to achieve the desired load current, while the supply voltage (VDD) is adjusted to emulate widely varying application conditions. In the test setup, a commercial gate driver was used to control the E-mode Si MOSFET. A pulse-wise gate-source voltage swing from 0 V to 8 V is supplied by a pulse generator through an external gate resistor (RG) of 1.0 Ω. Figure 10 shows the measured turn-on, turn-off transition and dynamic Rds,on at a VDS of 50 V and IDS of 2 A. The dynamic Rds,on is measured through a sensing network to obtain a precise VDS in the on-state. The sensing network consists of a resistor, a diode, and a Zener diode to clamp high voltage when the GaN FET is turned off [18]. Table 1 summarizes the measured static and dynamic performances. 6 (@0.974 V/2.05 A) IGS (V) VDS 3 6.04 Condition VGS = 10 V, IDS = 2 A VGS = 0 V, IDS = 250 µA IDS = 6.04 A, VDS = 2 V 10 VGS (V) VDS (V) 40 IDS (A) RG Sensing network 60 Specification 3.0E-04 –2 4.0E-04 Fig. 10. Dynamic performance of cascode GaN FET: (a) turn-on transition, (b) turn-off transition, and (c) dynamic onresistance. ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 IV. Boost Converter Using Cascode GaN FET A boost converter evaluation board was designed to test the performance of the device in a field application. Figure 11(a) shows a simplified circuit diagram. It consists of an input capacitor (Cin), inductor (L), cascode GaN FET, Schottky barrier diode (SBD), snubber circuit to reduce ringing and protect the GaN FET under high-switching-frequency conditions, output capacitor (Cout), input/output voltage sensing network, controller, and gate driver. It also has an option to Dong Yun Jung et al. 65 IN (DC) Cin Input sensing SBD Cascode GaN FET Cout Snubber OUT (DC) Output sensing 95 +12 V 90 85 80 D = 0.3 D = 0.4 D = 0.5 D = 0.6 75 Gate driver Controller Converter efficiency (@100 kHz, Load 50 ) 100 Efficiency (%) L 70 0 10 20 Function generator 30 40 Output power (W) (a) 50 60 Converter efficiency (@Load 50 , Duty = 0.5) (a) 100 Pow e r sem ic ondu Efficiency (%) 95 c to r s 90 85 f = 100 kHz f = 300 kHz f = 500 kHz f = 700 kHz f = 1MHz 80 75 70 (b) Fig. 11. (a) Simplified circuit diagram and (b) fabricated photograph of boost converter evaluation board. Low-voltage power supply Oscilloscope Electronic load Power analyzer High-voltage power supply Converter Function generator Fig. 12. Converter measurement setup. control the duty cycle and switching frequency through an external function generator instead of an automatic control. This uses a closed loop consisting of the input/output voltage sensing network, the controller, and the gate driver. Figure 11 (b) shows a photograph of the boost converter evaluation board. It was designed and fabricated to selectively test various devices with different pin configurations on the same board. The size of the boost converter evaluation board with several additional options is 20 cm × 14 cm. The converter measurement setup consists of a low-voltage power supply for the gate driver and controller, a high-voltage power supply for the converter input, an electronic load for the 66 Dong Yun Jung et al. 0 10 20 30 40 Output power (W) (b) 50 60 Fig. 13. Efficiency measurement results by (a) duty cycle variation and (b) switching frequency variation. converter load, an oscilloscope to confirm waveforms of voltage/current at several test points, a power analyzer to evaluate power efficiency, and a function generator for external gate control. This is shown in Fig. 12. Figure 13 shows the measurement results for the converter efficiency as a function of duty cycle and switching frequency. Under a switching frequency of 100 kHz and load resistance of 50 Ω, the converter efficiency is 93% at a duty cycle of 0.5. The converter efficiency is above 90% at a 0.5 duty cycle, 50-Ω load, and 500-kHz switching frequency. V. Conclusion This paper presents the design and characterization analysis of a cascode GaN FET integrated with a D-mode GaN FET and E-mode Si MOSFET for normally-off operation. In addition, this paper describes the proposed design and performance verification method for the cascode GaN FET using a resistive load dynamic performance test board and a boost converter evaluation board with a gate control option. The designed and fabricated D-mode GaN FET and cascode GaN FET are suitable for handheld applications that require a voltage below 100 V with a small form factor. ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 References [1] O. Ambacher et al., “Two-Dimensional Electron Gases Induced by Spontaneous and Piezoelectric Polarization Charges in N- and Ga-Face AlGaN/GaN Heterostructures,” J. Appl. Phys., vol. 85, no. 6, Mar. 1999, pp. 3222–3233. [2] A. Fontsere et al., “A HfO2 Based 800 V/300 °C Au-Free AlGaN/GaN-on-Si HEMT Technology,” Int. Symp. Power Semicond. Devices ICs, Bruges, Belgium, June 3–7, 2012, pp. 37–40. [3] H.S. Lee et al., “0.34 VT AlGaN/GaN-on-Si Large Schottky Barrier Diode With Recessed Dual Anode Metal,” IEEE Electron Device Lett., vol. 36, no. 11, Nov. 2015, pp. 1132–1134. [4] W. Saito et al., “Recessed-Gate Structure Approach Toward Normally Off High-Voltage AlGaN/GaN HEMT for Power Electronics Applications,” IEEE Trans. Electron Devices, vol. 53, no. 2, Feb. 2006, pp. 356–362. [5] O. Hilt et al., “70 mΩ / 600 V Normally-off GaN Transistors on SiC and Si Substrates,” IEEE Int. Symp. Power Semicond. Devices IC’s, Hong Kong, May 10–14, 2015, pp. 237–240. [6] Y. Cai et al., “High-Performance Enhancement-Mode AlGaN/GaN HEMTs Using Fluoride-Based Plasma Treatment,” IEEE Electron Device Lett., vol. 26, no. 7, July 2005, pp. 435– 437. [7] L. Yuan, H. Chen, and K.J. Chen, “Normally-off AlGaN/GaN Metal-2DEG Tunnel-Junction Field-Effect Transistors,” IEEE Electron Device Lett., vol. 32, no. 3, Mar. 2011, pp. 303–305. [8] Z. Tang et al., “600-V Normally Off SiNx/AlGaN/GaN MISHEMT with Large Gate Swing and Low Current Collapse,” IEEE Electron Device Lett., vol. 34, no. 11, Nov. 2013, pp. 1373– 1375. [9] Y. Park et al., “Normally-off GaN MIS-HEMT Using a Combination of Recessed-Gate Structure and CF4 Plasma Treatment,” Phys. Status Solidi A, vol. 212, no. 5, May 2015, pp. 1170–1173. [10] S.W. Han et al., “AlGaN/GaN Metal-Oxide-Semiconductor Heterojunction Field-Effect Transistor Integrated With Clamp Circuit to Enable Normally-off Operation,” IEEE Electron Device Lett., vol. 36, no. 6, June 2015, pp. 540–542. [11] X. Huang et al., “Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration,” IEEE Trans. Power Electron., vol. 29, no. 5, May 2014, pp. 2208–2219. [12] X. Huang et al., “Evaluation and Application of 600 V GaN HEMT in Cascode Structure,” IEEE Trans. Power Electron., vol. 29, no. 5, May 2014, pp. 2453–2461. [13] Z. Liu et al., “Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMT,” IEEE Trans. Power Electron., vol. 29, no. 4, Apr. 2014, pp. 1977–1985. [14] P.-C. Chou and S. Cheng, “Performance Characterization of ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173 [15] [16] [17] [18] Gallium Nitride HEMT Cascode Switch for Power Conditioning Application,” Mater. Sci. Eng., B, vol. 198, Aug. 2015, pp. 43–50. X. Huang et al., “Characterization and Enhancement of HighVoltage Cascode GaN Devices,” IEEE Trans. Power Electron., vol. 62, no. 2, Feb. 2015, pp. 270–277. W. Chang et al., “Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation,” ETRI J., vol. 38, no. 1, Feb. 2016, pp. 133–140. Z. Tang et al., “High-Voltage (600-V) Low-Leakage LowCurrent-Collapse AlGaN/GaN HEMTs With AlN/SiNx Passivation,” IEEE Electron Device Lett., vol. 34, no. 3, Mar. 2013, pp. 366–368. A. Calmels, VDS(on), VCE(sat) Measurement in a High Voltage, High Frequency System, Application note APT0407, Nov. 2004. http://www.advancedpowertech.com Dong Yun Jung received his BS degree in electronics and materials engineering (First class honors) from Kwangwoon University, Seoul, Rep. of Korea, in 2001, and his MS and PhD degrees (excellence graduate) in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Rep. of Korea, in 2003 and 2009, respectively. He studied broadband ICs for optical communications and low-power CMOS receiver circuits and 3-D modules using low-temperature co-fired ceramic (LTCC) technologies for millimeter-wave applications. He joined the ETRI, Daejeon, Rep. of Korea in 2003 as an engineering researcher. From 2009 to 2014, he was with the R&D Center of Samsung Electronics, Seoul, Rep. of Korea as a senior engineer, where he contributed to the development of millimeter-wave IC. Since 2014, he has been with ETRI as a senior researcher. His research interests include power electronics semiconductor devices and high-speed, highefficiency power electronics conversions for high-power and energy applications. Dr. Jung received the Best Paper Award from KAIST in 2007 and 2008. He received a Silver Award in the SAMSUNG Best Paper Award competition in 2012. Youngrak Park was born in Ulsan, Rep. of Korea, in 1986. He received his BS degree in information and communications engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 2008, and his MS degree in electrical engineering from Seoul National University, Rep. of Korea, in 2011. He studied the design of radio frequency power amplifiers and millimeterwave ICs. Since February 2011, he has been with the ETRI, Daejeon, Rep. of Korea. His research activities include the fabrication and design of GaN devices. Dong Yun Jung et al. 67 Hyun Soo Lee received his BS degree in electronics engineering from Dankook University, Cheonan, Rep. of Korea, in 2014. He received his MS in electricity and electronic engineering from Dankook University, Youngin, Rep. of Korea, in 2016. In 2016, he joined the ETRI, Daejeon, Rep. of Korea as a research scientist. His research interests include power electronics modules and power device fabrication. He is currently focused on GaN power devices. Chi Hoon Jun received his MS degree in mechanical engineering and his PhD degree in metallurgical engineering from Kyungpook National University, Daegu, Rep. of Korea, in 1984 and 1997, respectively. He joined the ETRI, Daejeon, Rep. of Korea, in 1985 as a member of the engineering staff. He became a principal member in 1999. He also served as a team leader of the Microsystem Team from 2001 to 2002. His primary research interests are in WBG power semiconductor devices, power packaging, energy harvesting, optical MEMS for telecommunication, physical microsensors, bioMEMS/bio chips, surface micromachining, DRAM metallization, and CVD/MOCVD processes for advanced semiconductors. He received the Outstanding Researcher Award and the R&D Award from the Ministry of Science & Technology, Rep. of Korea, in 1987 and 1990, respectively. Hyun Gyu Jang received his BS degree in electronics engineering from Korea Polytechnic University, Siheung, Rep. of Korea, in 2013, and his MS in advanced device technology from the University of Science, Daejeon, Rep. of Korea, in 2015. He studied gallium nitride power devices. In 2015, he joined the ETRI, located in Daejeon, Rep. of Korea, as a research engineer. His current research interests include the design, fabrication, and characterization of electronic devices based on compound semiconductors, and the design of power supply units such as the inverter and converter. Junbo Park received his BS degree in physics from Harvey Mudd College Claremont, CA, USA, in 2008. He received his PhD in applied physics from Cornell University Ithaca, NY, USA, in 2014. In 2015, he joined the ETRI, Daejeon, Rep. of Korea as a research scientist. His research interests include power electronics modules and power device fabrication. He is currently focused on SiC power devices. 68 Dong Yun Jung et al. Minki Kim received his BS degree in electrical engineering and computer science from Kyungpook National University, Daegu, Rep. of Korea, in 2008, and his MS degree in electrical engineering and computer science from Seoul National University, Rep. of Korea, in 2010. Since 2010, he has been working at ETRI, Daejeon, Rep. of Korea, as a research engineer. His research interests include wide-bandgap power devices and power control systems. He is currently focusing on the reliability of GaN power devices. Sang Choon Ko received his BS degree in electrical engineering from Sungkyunkwan University, Suwon, Rep. of Korea, in 1994, and his MS degree from the same university in 1996. From 1990 to 1991, he served in the military in the Army of Korea. After obtaining his MS degree, he moved to Tohoku University, Sendai, Japan. He received his PhD from Tohoku University in March 1999. That year, he joined the Microsystem Technology Laboratory of Daimler Chrysler Co., Stuttgart, Germany, as a visiting researcher. At the same time, he was a research associate in the Department of Mechatronics and Electronics at Tohoku University. In 2000, he joined Pohang University of Science and Technology, Rep. of Korea, in a postdoctoral position. Since October 2001, he has worked on the Microsystem Team of the ETRI, Daejeon, Rep. of Korea. He has studied piezoelectric acoustic devices, condenser microphones, and MEMS optical switches. Since 2011, he has been involved in the development of GaN-based discrete devices, e.g., SBD and FET. Eun Soo Nam received his BS degree in physics from Kyungpook National University, Daegu, Rep. of Korea, in 1983, and his MS and PhD degrees in physics from the State University of New York, Buffalo, USA, in 1992 and 1994, respectively. Since 1985, he has been with the ETRI, Daejeon, Rep. of Korea. In 2006, he was a visiting scholar in the Division of Engineering and Applied Sciences (now the School of Engineering and Applied Sciences), Harvard University, Cambridge, MA, USA. Dr. Nam holds over 50 patents and has published over 100 papers in several fields including compound semiconductors, microwave monolithic integrated circuits (MMICs), long-wavelength InP semiconductor photonic devices, and optoelectronic integrated circuits (OEICs). ETRI Journal, Volume 39, Number 1, February 2017 https://doi.org/10.4218/etrij.17.0116.0173