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UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences HW #4: Wire Modeling NEEI 6341 (Spring 2006) 1 Elmore Delay Calculate the Elmore delay from node A to node B using the values for the resistors and capacitors given in the table below. G A R1 R 5 R 2 D C2 R3 C R6 E C1 C5 C3 C4 Resistor R1 R2 R3 R4 R5 R6 R7 R8 2 2A Value (Ohms) 0.25 0.25 0.50 100 0.25 1.00 0.75 1000 B R8 C6 7 R 4 R F H C8 I C7 Capacitor C1 C2 C3 C4 C5 C6 C7 C8 Value (fF) 250 750 250 250 1000 250 500 250 RC Wire Compute the 0%-50% delay of a 500um x 0.5um wire with resistance of 0.08 Ohms/sq, with area capacitance of 30aF/um2, and fringe capacitance of 40aF/um. Assume the driver has a source resistance of 100 ohms and negligible output capacitance. i. Using a lumped model for the wire. ii. Using a PI model for the wire, and the Elmore equations to find tau. (see Chapter 4, figure 4.26). iii. Using the distributed RC line equations from Chapter 4, section 4.4.4. 2B 3 Simulate these circuits in SPICE and compare to your results from part 2A. Be sure to include the source resistance. For each simulation, measure the 0%-50% time for the output i. First, simulate a step input to a lumped R-C circuit. ii. Next, simulate a step input to your wire as a PI model. iii. Unfortunately, our version of SPICE does not support the distributed RC model as described in the book (Chapter 4, section 4.5.1). Instead, simulate a step input to your wire using a PI3 distributed RC model. Transmission line To connect a processor to an external memory an off –chip connection is necessary. The copper wire on the board is 15 cm long and acts as a transmission line with a characteristic impedance of 100 . The memory input pin presents a very high impedance which can be considered infinite. The bus driver is a CMOS inverter consisting of very large devices: (50/0.25) for the NMOS and (150/0.25) for the PMOS. The minimum size device, (0.25/0.25) for NMOS and (0.75/0.25) for PMOS, has the on resistance 35 k. 3A 3B 3C 4 Determine the time it takes for a change in the signal to propagate from source to destination (time of flight). The wire inductance per unit length equals 750 nH/m. Determine how long it will take the output signal to stay within 10% of its final value. You can model the driver as a voltage source with the driving device acting as a series resistance. Assume a supply and step voltage of 2.5V. Hint: draw the lattice diagram for the transmission line. Resize the dimensions of the driver to minimize the total delay. Buffering Line Drivers A two-stage buffer is used to drive a metal wire of 1 cm. The first inverter is a minimum size with an input capacitance Ci=10 fF and a propagation delay tp=150 ps when loaded with an identical gate, and assume gamma =1. The width of the metal wire is 2.5 m. The sheet resistance of the metal is 0.08 /sq, the capacitance value is 0.03 fF/m2, and the fringing field capacitance is 0.04 fF/m. 4A 4B What is the propagation delay of the metal wire? Compute the optimal size of the second inverter. What is the minimum delay through the buffer (i.e. the sum of the delays through both inverters)?