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EE4271 VLSI Design
Homework 7
Due in class on 11/30/2016
Name:
M-number:
1. Consider a 2-input gate F whose truth table is shown as follows.
A
B
F
0
0
1
0
1
1
1
0
0
1
1
1
Design a cell library based IC to implement the above system. In the system, there are
two input bits A and B, and one output bit F. Use AND, OR and NOT gates to implement
F. Use technology mapping to map the above circuit to the circuit with NOT and 2-input
NAND gates only and then implement the resulting circuit using CMOS transistors.
Indicate the number of transistors used.
2. Design an IC using full-custom design methodology for F in Problem 1. Note that only A
and B (but not A’ or B’) are given as inputs.
3. Implement F in Problem 1 using Programming Logic Array.
4. Compute the clock frequency for the following synchronous sequential circuit. Suppose
that the setup time for each flipflop is 1, the hold time is 0, and each combinational
circuit delay is as shown.
FF
2
1
FF
FF
3
4
FF
5. Consider performing buffer insertion to a wire of length 100 with identical buffers where
driving resistance is 1 and input capacitance is 2. Suppose that the unit wire capacitance
is 1 and unit wire resistance is 1. Suppose that the load capacitance at the end of the wire
is 0. What is the delay before buffer insertion? What is the optimal delay after buffer
insertion?
6. Perform buffer insertion to the following circuit. Note that the driver has the same
characteristic as a buffer and the solution is represented in the format of (C,Q). Find the
buffering solution with the maximum RAT at driver.
2
10
(v1, 1, 50)
Add wire
(v2, , )
(v3, , )
RAT =
Add wire
Add Driver
•
Unit r = 1, unit c = 1
•
Rb = 1, Cb = 1
• Rd = 1
(v2, , )
v
v
1 Insert Buffer
(v3, , )
Add wire
1
v
v
1
1
RAT =
Add Driver
DriDriver
driver
7. Perform buffer insertion to the following circuit. Note that the driver has the same
characteristic as a buffer and the solution is represented in the format of (C,Q). Find the
buffering solution with the maximum RAT at driver.
8. Suppose that unit wire capacitance is 1 and unit wire resistance is 1. Assuming that the arrival
time at all primary input gates is 0. Compute the arrival time at each gate.
C=2,R=2
2
C=10,R=2
1
2
C=2,R=4
1
C=2,R=2
1