Download Leakage Power Reduction

Leakage Modeling and Reduction
Zhen Cao, Zhe Feng
EDA Lab, EE, UCLA
Outline
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Background
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Threshold Voltage Variation
Leakage Power
Leakage Power Estimation
Leakage Power Reduction
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Background — CMOS Generations
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For each generation
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–
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0.7x gate delay
0.7x dimensions
1.4x frequency
1x area (0.7*0.7*2.1)
Background — Scaled CMOS Systems
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New generation microprocessors
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–
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augmented architecture and circuit techniques
an additional 60% frequency increase (2x for
each generation)
higher energy consumption
higher peak power dissipation
higher power delivery requirement
Background — Supply and threshold
Valtage Scaling
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Supply voltage have to scale to limit the energy and
power increase
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–
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MOS device threshold voltage have to scale to
sustain the traditional 30% gate delay reduction
Increase in the variation of threshold voltage
–
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the amount of energy reduction depends on the magnitude
of supply voltage scaling [Chandrakasan et al. 1992]
swiching power is proportional to area × ε/distance × Vdd
× Vdd × F
1*1/0.7*2.0* Vdd2 = 1.4x (Vdd = 0.7x)
due to worsening short channel effects
Increase leakage (exponentially)
Outline

Background

Threshold Voltage Variation

Leakage Power
Leakage Power Estimation
Leakage Power Reduction
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
Threshold Voltage Variation (1)
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Reduced device channel length
– Given technology generation,
since depletion widths are
predefined, the rate at which
the barrier height increases as
a function of distance from the
source into the channel is
constant
– Channel length is reduced, the
barrier for the majority carriers
to enter the channel also is
reduced
– Reduced Vth
Threshold Voltage Variation (2)

Reduced device channel length
– In other words, when the
depletion charge between the
source and drain terminals
become a larger fraction of the
channel length, the Vth
reduces
– In short channel transistor, the
barrier height and therefore
the Vth are a strong function of
the Vds
– In short channel devices,
threshold voltage depends on
the Vds
Threshold Voltage Variation (3)

For shorter the channel length, both channel length
and drain voltage reduce this barrier height
–
–
two-dimensional effect
channel length variation → threshold voltage variation
Threshold Voltage Variation (4)

Measurements of threshold voltage variations
Outline

Background
Threshold Voltage Variation

Leakage Power

Leakage Power Estimation
Leakage Power Reduction


Subthreshold Leakage Power (1)

Subthreshold leakage is the current that flows
between the source and drain of a MOSFET when
the transistor is in the weak-inversion region
picture from www.wikipedia.org
Subthreshold Leakage Power (2)

With technology scaling,
threshold voltage has to be
scaled along with supply
voltage, in order to maintain
performance

Reduction in Vth increases the
subthreshold leakage current
significantly
Subthreshold Leakage Power (3)

Switching power vs subthreshod
leakage power
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–
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Switching power increases by 1.4X per
generation
Subthreshold leakage power will
increase at a very rapid rate due to its
strong dependence on the Vth
Subthreshold leakage power will be
comparable to the switching power in
the 60–65 nm node
Gate Leakage Power (1)
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Scaling gate oxide thickness is important for
controlling threshold voltage tolerances
The gate cannot be considered as an ideally
insulated electrode
The leakage current can flow from the
channel to the gate
Affects the circuit functionality and increases
the standby power consumption
Gate Leakage Power (2)

Alternatives for silicon dioxide
–
high-permittivity gate dielectric, metal gate, novel device
structures and circuit-based techniques
picture from www.legitreviews.com
Quick Review
Technology 0.7x
Channel length ↓
Channel barrier ↓
Vds ↑
Vt variation
Delay 0.7x
Freq 2.0x
Vdd ↓ due to power
Vt ↓ due to delay
Isub ↑
Outline

Background
Threshold Voltage Variation
Leakage Power

Leakage Power Estimation

Leakage Power Reduction
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
Leakage Power Estimation(1)
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Why?
To limit the energy and the power increase
Vdd have to continually scale
To sustain the
Delay reduction
Leakage power increases
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Focus
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Subthreshold leakage power
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Active leakage power
Standby leakage power
Solution
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Statistical method
Vt have to continually scale
Leakage Power Estimation(2)—Present
Leakage Current Estimation Techniques
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Just provide lower and upper bounds on the leakage
current
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use the expected mean leakage currents per unit width of
PMOS and NMOS devices in a particular chip.
–
use the worst-case leakage current per unit width of PMOS
and NMOS devices.
Leakage Power Estimation(3)—Present
Leakage Current Estimation Techniques
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Acceptable
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Unacceptable
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For the old technology generation
It is a negligible component.
For the new technology generation
As much as half.
Pessimistic or optimistic
What else?
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The variation in within-die threshold voltage
Leakage Power Estimation(4)—Leakage Current
Estimation Including Within-die Variation
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What changes?
–
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Assumption
–
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Instead of the mean leakage and the worst-case leakage,
the entire range should be considered.
The within-die threshold voltage or channel length variation
follows a normal distribution.
Solution
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By performing the weighted sum of devices of different
leakage, we can estimate the total leakage of the chip.
Leakage Power Estimation(5)
—Comparison
(a) existing technique (b) new technique
Outline

Background
Threshold Voltage Variation
Leakage Power
Leakage Power Estimation

Leakage Power Reduction



Leakage Power Reduction
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Three main approaches
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Source Biasing
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Direct Vt Manipulation
–
Power Gating
Outline

Background
Threshold Voltage Variation
Leakage Power
Leakage Power Estimation

Leakage Power Reduction

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–
–
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Source Biasing
Direct Vt Manipulation
Power Gating
Source Biasing
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Main idea
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Bias the source terminal of an “off” transistor to
exponentially reduce the leakage currents.
Outline

Background
Threshold Voltage Variation
Leakage Power
Leakage Power Estimation

Leakage Power Reduction

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–
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Source Biasing
Direct Vt Manipulation
Power Gating
Direct Vt Manipulation(1)
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Main idea
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Solution
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Using low Vt in devices that need high performance.
Using high Vt in devices that need low leakage requirements.
Two kinds
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Adjust the Vt’s of transistors within a circuit
Multiple Vt
Variable Vt
Difficulties
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Determine which part need high performance, i.e. critical,
especially in the presence of process variation.
Direct Vt Manipulation(2) — Multiple Vt
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Popular way
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Dual Vt partitioning
Limitations
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In many optimized designs, the effectiveness is reduced.
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CAD tools must be developed and integrated into the
design flow to help optimize the partitioning process.
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It may not reduce standby leakage currents enough for ultra
low power, high performance applications.
Direct Vt Manipulation(3) — Multiple Vt
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Difficulties
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Noncritical gates which are converted to be high Vt devices can
become critical gates as follows
–
process variation
Conclusion
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Other leakage reduction techniques are important.
Direct Vt Manipulation(4) — Variable Vt
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Main idea
–
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Rely on biasing the body terminal of the device to
dynamically adjust the Vt.
Solution
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By applying maximum reverse biasing during the
standby mode, the threshold voltage is shifted
higher and subthreshold leakage current reduced.
Direct Vt Manipulation(5) — Variable Vt

Improvement
–
Reverse body bias does not scale well in nanoscale
CMOS while forward body bias controls the channel
better and therefore modulates the threshold voltage
better.
Direct Vt Manipulation(6) — Variable Vt
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Improvement
–

There exists an optimal forward bias
Conclusion
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Applying forward body bias in operation mode to achieve the
target frequency of operation and withdrawing forward body bias in
standby mode reduces leakage power is more effective.
Outline

Background
Threshold Voltage Variation
Leakage Power
Leakage Power Estimation

Leakage Power Reduction



–
–
–
Source Biasing
Direct Vt Manipulation
Power Gating
Power Gating(1)

Main idea
–
It is a dual Vt technique that is extremely effective
at reducing standby leakage currents at the
expense of performance penalty.
Power Gating(2)
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Important issue
–
Determine the proper sizing of the gating
transistor
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Tradeoff
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Minimize silicon area overhead
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Increase design complexity
Questions?