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MINISTRY OF EDUCATION AND SCIENCE OF THE RUSSIAN FEDERATION
FEDERAL STATE BUDGETARY EDUCATIONAL INSTITUTION OF HIGHER
PROFESSIONAL EDUCATION
«TOMSK POLYTECHNIC UNIVERSITY»
E.A. SHUTOV, G.A. NIZKODUBOV
COMPUTER TECHNOLOGIES OF ENERGY SUPPLY
Recommended as a study guide by Editorial Board of
Tomsk Polytechnic University
Publishing house of
Tomsk polytechnic university
2012
Library Bibliographic Classification (LBC) 658.26:621.31 – 52(076.5)
Universal Decimal Classification (UDC) 31.29-5Я73
SH978
Shutov E.A., G.A. Nizkodubov
SH978
Computer technologies of energy supply: study guide/E.A.
Shutov, G.A. Nizkodubov; Tomsk polytechnic university - Tomsk:
Publishing house of Tomsk Polytechnic University, 2012. – 51 p.
The study guide sets out the basis of building a channel for collecting
and processing data. Representation of individual components of the channel
is given.
The study guide is aimed at the first year students enrolled in
“Optimization of developing power supply systems”, and graduate students
enrolled in “Electrical Power Engineering and Electrical Engineering”
LBC 658.26:621.31 – 52(076.5)
UDC 31.29-5Я73
Recommended for printing and publishing by Editorial Board of
Tomsk Polytechnic University
Reviewers
Engineering manager of JSC “Tomsk Electric-Bulb Plant”
A.I. Prudnikov
Deputy Director of Future Policy Staff Department LLC “Gorseti”, Tomsk
T.N. Kirilova
© State Educational Institution of Higher Professional Education TPU, 2012
© Shutov E.A., 2012
© Cover by publishing house of Tomsk Polytechnic University, 2012
2
CONTENTS
INTRODUCTION……...................................................................................4
1. Components and nodes of analog converters ...........................................6
1.1. Operational Amplifier ............................................................................6
1.2. Active filters ..........................................................................................10
1.3. Voltage Comparators .............................................................................13
1.4. Sample and hold circuit .........................................................................15
2. Elements and components of ADC ..........................................................16
2.1. DAC ......................................................................................................16
2.2. ADC ......................................................................................................18
2.2.1. Incremental ADC .............................................................................19
2.2.2. Successive approximation ADC ....................................................... 20
2.3. Analog-digital multiplication-division units .........................................22
3. Microprocessor systems ............................................................................25
3.1. Architecture of digital computers ..........................................................25
3.2. PC address decoder ................................................................................27
3.3. ROM interface.........................................................................................28
3.4. Interface with I/O ports ..........................................................................30
3.5. Interrupt synchronization of data transfer in I/O devices……………...32
3.6. Errors detection in data transfer .............................................................35
3.7. System Interface .....................................................................................36
3.8. Structure of a basic microprocessor .......................................................39
REFERENCES ..............................................................................................45
3
INTRODUCTION
The course “Computer technologies of energy supply” focuses on a
study of microcomputer interface with control objects. The growth of control
and measurement facilities necessitated a high degree of automation in
calculation of control parameters. All these tasks can be solved on a basis of
systems intended for data collecting and processing (DCP).
Different requirements for cost and technical characteristics met by
DCP, determine the possibility of variations in the structure of DCP on the
basis of a method of signal processing.
The structure that implements a principle of parallel-processing
formation of analog signals from sensors of DCP is shown in fig. 1.1 a.
S
A
NC
SHD
FC
ADC
DS М P
S
A
NC
SHD
FC
АDC
а
S
A
NC
FC
SHD
CDev
АS
S
A
NC
FC
b
Fig. 1.1a
4
SHD
МP
АDC
A controlled parameter (speed, coordinates, temperature, pressure, etc.)
with an appropriate sensor S is converted into an electrical signal. Most
sensors have a high output from resistance and low dynamic range (for
example, when there is a temperature change by 1000C, sensor output
voltage will change to 3 mV). Therefore, it is necessary to use an adaptor (A)
which in general performs the following functions: signal amplification to a
required level, expands a dynamic range of input signal; sensor adjustment
and other DCP channel elements according to the load. Next, unwanted lowfrequency and high frequency components are removed from the signal when
a normalization circuit (NC) is used. Functional conversion (FC) of analog
signal is carried out in order to implement units in sensor structure to display
definite mathematical operations and improve its accuracy parameters. Thus,
measuring the flow rate of liquid or gas is based on the application of
differential pressure sensors at two points in the flow.
In this case, the flow rate is   2 gP . The converted signal enters a
sample and hold device (SHD), and then turns to an analog-to-digital
converter (ADC). A digital switch (DS) selects a channel and transfers data
to a microprocessor (MP).
Conversion of analog to digital values always occurs for a finite period
of time. During this time interval, the signal at the input of the ADC should
be maintained unchanged. This function is performed by SHD, the output
signal is proportional to a signal at the input until store instruction is given,
after that the output signal remains constant within the time required for
signal transformation into a digital form.
The shown structure (Fig. 1.1 a) provides maximum performance of
the equipment of all DCP system channels (due to independence of each
signal processed) and high-quality of signals transformation due to system
capability to ensure the required level of normalization of the signal at the
ADC input in each channel. This option for system data collection has a
promising future, but at the present stage of development of micro circuitry
its implementation has a high cost of DCP due to condition of relatively high
cost of ADC integrated circuits.
Another DCP system design (Fig. 1.1,b) is based on the principle of
sequential processing of analog signals and transfer controlled process
switching (a control device – CDev.) from a digital to analog domain (an
analog switch - AS). High technical characteristics of the structure are shown
in Figure 1.1,b and have the same functional blocks, which were incorporated
into the structure shown in Fig. 1.1, a. Performance of such system is directly
dependent on ADC speed and its limited dynamic parameters, therefore in
such systems ADC with the maximal speed is required.
5
In design of a particular system by a microcomputer it is necessary to
consider characteristics of digital circuitry and analog-threshold elements of
the interface, and an average degree of integration circuits which are multifunctional units of computers.
1. COMPONENTS AND NODES OF ANALOG CONVERTERS
In a data channel of object control and microprocessor some of the
analog conversion devices are required to be used, such as a current-voltage
converter, comparator, active filters, a sample-hold device etc. where an
operational amplifier is a basic element.
1.1. OPERATIONAL AMPLIFIERS
An operational amplifier (OA) - is an analog IE, voltage U O is formed
at its output, this voltage is equal to a gain difference between two input
voltages U 1 and U 2 . The ideal transfer characteristic of OA (dependence of
output voltage from the input status) can be represented by the expression
U O  K OL U1  U 2  ,
where K OL - gain of ОА without feedback.
In the first half of the 1960s analog computers were widely used. To
perform various mathematical operations the first OA were used. It explains a
traditional name for these devices – “operational amplifiers”.
However, since the scope of OA application has expanded, and now, as
will be seen from what follows, they are used to solve many tasks. Circuit
design of OA is shown in Fig. 1.2. Theoretically, OA is sensitive only to
_
difference of two input voltages:
U2
U0
U i  U1  U 2
U1
+
Fig. 1.2
which is called a differential input signal, and totally insensitive to any
component of the input signals common to both OA inputs. It is called a
common-mode signal and is given by
U i С ommod 
6
U1  U 2
.
2
OA gain open loop is a constant positive dimensionless quantity, which
is usually very high at low frequencies (0  30 Hz) and ranges from 105 to
106. If the input OA is only submitted by voltage U 1 ( U 2  0 ), then
U O  K OLU1 will be equal to a strong non-inverted input signal. If, however,
to the input of OA apply only U 2 (when U1  0 ), then U O   K OLU 2 , then
the output voltage is equal to a strong inverted input voltage. Thus, “lower”
input (U 1 ) is called a non-inverting and “upper” (U 2 ) - inverting.
Most of OA are powered by a split power supply with positive and

negative poles which are connected to special OA terminals. Both U and
U  voltage are equal in magnitude and opposite in sign. Voltage range is
typically in the range of  5 to  18V. Use of a dual power source makes it
possible to change the voltage at the OA input so that it can take on values
both above and below zero potential. For simplicity, the electrical connection
to connect the power supply is usually not drawn in the circuit.
U0
U+
1-2B
Ui
1-2B
UFig.1.3
The ideal OA transfer characteristic is shown in Fig. 1.3. Select a linear
part (amplification region), where U O  K OLU i bounded on both sides of the
saturation region, where the output voltage is limited by the supply voltage,
and no longer responds to changes in input voltage. Since gain is very large,
the width of the linear zone is very small and can be determined from the
expression
U i  U   U   2 В / KOL
Consequently, the signal in the OA output is equal to the enhanced
value of the input voltage, the amplitude of the input voltage must be
sufficiently small, usually less than 1 mV. Otherwise, OA gets in a saturation
zone and the output voltage doesn’t follow the input. Because of this
limitation, OA usually includes a feedback loop, so that part of the output


7
voltage returns to the inverting input (Figure 1.4). In this case the conditions
of implementation of negative feedback can be observed, it creates a number
of significant advantages.
When analyzing a non-inverting circuit (( U1  0,U 2  0 , in Fig. 1.4)
one must take into account the following key provisions:
• potential difference between the input OA operating in a linear regime is
equal to 0;
• currents through the OA input terminals are
R2
U /2 + U f b
not available.
In analysis of inverting circuits
R1
x _
U
( U 2  0,U1  0 in Fig. 1.4) one must take into
2
account the following key provisions:
U0
Ui
• potential of a summing point is equal to U 1
+
zero (point x in the Figure 1.4);
Fig. 1.4
• current, entering the summing point of the
circuit input is equal to the current flowing in the feedback circuit;
• currents are not available through the amplifier input terminals.
A coefficient, showing what part of the voltage returns to the inverting
input, called a feedback factor F . For the circuit in Figure 1.4 it is determined
from the relation
U fb
R1
F

U O R2  R1 .
This expression follows from the equation of a simple voltage divider.
Note, although the basic equation of the functioning of OA (U O  K OLU i ) is
still running, a differential component of the input voltage is no longer equal
U i  U1  U 2 , and is subject to equality
U i  U1  U 2'  U fb  U1  U 2'  FU O ,
whence


U O  KOLU i  KOL U1  U 2'  FUO .
Solving for U O , we obtain
8



 K OL 
UO  
U1  U 2'  K FL U1  U 2'

1  FKOL 

(7.1)
where K FL - gain with feedback. Note, since the signal now comes not
directly to the inverting input of OA but through a voltage divider ( R2 , R1 ),
voltage U 2' is associated with U 2 by the ratio
R2
U 2'  U 2
R1  R2
From expression (1.1) it follows that gain of OA with negative
feedback is
K OL
1  FKOL
and a feedback factor is less than OA without feedback. The magnitude
FK OL is called loop gain. With a large loop gain, when FK OL  1 , we have
K FL 
K FL  KOL /( FK OL ) , therefore, the coefficient of gain OA with negative
feedback (NFB) is practically independent of K OL , and is mainly determined
by the parameters of a feedback loop. For the circuit (Figure 1.4) gain with
feedback is
K FL  K OL / FK OL  1 / F  R2  R1  / R1  1  R2 / R1 .
The input signal U 1 which is fed to a non- inverting input of OA, then
transmitted to the output of OA with a gain1  R2 / R1 . The coefficient of
another input signal U 2 , firstly, has a negative sign, and secondly, the
transformation takes into account the voltage divider ( R2 , R1 ) and is equal to
 
R2
R 
R
  1  2    2 ,
R1  R2  
R1 
R1
finally we have U O  U1 1  R2 / R1   U 2 R2 / R1  .
The method described is valid considering OA in its ideality. For an
ideal amplifier output voltage is equal to zero, the input impedance is
infinitely large, output impedance is zero, gain does not depend on the
frequency of input signals.
9
1.2. ACTIVE FILTERS
One of the most important applications of OA is active filters.
An ideal frequency selective filter - a device or system which has a gaintransfer characteristic between input and output; it is constant in a certain
frequency bandwidth and there is a naught output in a stopband. Fig. 1.5
shows transfer characteristics of ideal and real band-pass (fig.1.5, a) and
notch (fig. 1.5, b) filters, high-pass (fig. 1.5, c) and low-pass filters (fig. 1.5,
d).
W
Идеальная
Error-free behavour
характеристика
W
Error-free
behaviour
Полоса
Stopband
подавления
Полоса
Bandwidth
пропускания
fc 1
W
Идеальная
Error-free behaviour
характеристика
Полоса
Stopband
подавления
c
fc 2
b
f
W
Error-free
behaviour
Полоса
Bandwidth
пропускания
fc
fc 1
f
fc 2
а
Полоса
Bandwidth
пропускания
f
Fig. 1.5
d
Полоса
Stopband
подавления
fc
f
In passive filters only passive components are used: resistors,
capacitors and inductors. A circuit of an active filter contains one or more
active devices, usually OA. Advantages of an active filter compared with a
passive filter are shown below.
1. Gain. The active filter with a maximum gain-transfer characteristic can
be greater than unity.
2. Minimal load impact. A gain-transfer characteristic of an active filter is
practically independent of the load the filter works for and a source
that controls the filter.
3. Non-inductive filters. To design an active filter only resistors and
capacitors are required, inductance is not required. This feature is
10
particularly important when operating at relatively low frequencies
(<10 Hz), otherwise it would require larger inductance.
Next, analyze a generalized circuit of two-pole active filter (Figure
1.6). Assuming that OA - ideal with infinitely gain without feedback, the
output voltage will be equal to the voltage at node B, i.e. U O  U B . Equation
for the nodal nodes A and B have the form
U iY1  U OY2  U OY3  U A Y1  Y2  Y3 
for node A,
U AY2  U O Y2  Y4  for node B.
By solving the last equation with respect to U A and substituting the
result into the equation of node A, we have:
U iY1  U O Y3  Y2   U O Y1  Y2  Y3 Y2  Y4  /Y2 .
Multiplying both sides by Y2 , we obtain:



U iY1Y2  U O Y3Y2  Y22  U O Y1Y2  Y22  Y2Y3  Y1Y4  Y2Y4  Y3Y4

After collecting like terms in the last equation and taking into account
that the transfer characteristic is defined as W  U O / U i , we obtain:
Y1Y2
.
Y1Y2  Y4 Y1  Y2  Y3 
Next consider a special case of a two-pole low-pass filter where
Y1  G1, Y2  G2 , Y3  sC3 , Y4  sC4 (G- active conductivity, s - the Laplace
operator). A transfer function in this case has the following form
W
W s  
G1G2
G1G2  sC4 G1  G2  sC3 
At zero frequency, where s  jw  0,W s   1 , and at a frequency
s  jw   , W s   0 the circuit that actually works as an active filter of
lower frequencies.
For simplicity, assume G1  G2  G  1 / R therefore a transfer function
can be rewritten as
11
W s  
G2
G 2  sC4 2G  sC3 

1
1

1  sRС4 2  sRC3  1  s4 2  s3 
where 4  RC4 , 3  RC3 . For getting to the frequency domain we use the
equation s  jw :
1
1
W s  

2
1  jw4 2  jw3  1  w 34  j 2w4 
.
The square of the amplitude of the filter transfer function can be
written as
1
2
W 
1  2w234  w43224  4w224


1

1  w2 424  234  w43224
If it is necessary to have frequency response of the filter as
“maximally flat”, monotonically decreasing with frequency, you must first
2
accept d W / d w  0 and then solve this equation under the condition that
obliquity should be zero only if w  0 . By carrying out these actions, we
obtain:


 
2w 424  234  4w3 3224  0 , or 224  34  w23224  0 .
Therefore, in order to have obliquity equal to zero only when w  0 , it
is necessary to fulfill the condition 2 4  3 , and thus
C3  2C4 .
Under these conditions the expression for the square of the modulus of
the transfer function takes the form
W
2

1
1  4w4  44

1
1  4w 4 4
.
The point of 3dB occurs at W  1 2 , i.e. 4w4 4  1 , or w  1
and bandwidth or cutoff frequency is equal to
2
12
2,
1
0,7071

 2f c .
RC4
2 4
This type of filter with a “maximally flat” transfer characteristic within
the passband is called a Butterworth filter. In practice, Butterworth,
Chebyshev, and Bessel filters are widely used, their analysis is described in
detail in V.K. Zakharov Electronics Automatics Teleautomatics. L.:
Energoatomizdat, 1984. 432 p.
w3 дБ 
1.3. VOLTAGE COMPARATOR
Comparator - a circuit (Figure 1.2) that compares two input voltages
U 1 and U 2 ; it generates output voltageU O  U H , if U1  U 2 and U O  U L
when U1  U 2 and where U H and U L - two fixed voltage levels (high and
low). In Fig. 7.3a a gain-transfer function of the comparator is shown
(dependence U O on U i  U1  U 2 )
The comparator can be represented as a one-bit analog-to-digital
converter that produces an output level of a logical “1” ( U O  U H ), if the
analog input voltage U 1 is higher than the reference voltage U ОП  U 2 . A
logical “0” ( U O  U L ) appears in the output when the input voltage falls
below the reference voltage.
In many respects a comparator is very similar to OA (operational
amplifier), any OA can be used as a comparator. However, a comparator is
designed to work without feedback, i.e. in a switching mode, while OA is
almost always used in a feedback mode and performs the function of a linear
amplifier.
An OA produces a zero output voltage when the differential
component of the input signal is zero. A comparator operates so that its
output voltage takes only two fixed values, so that at zero voltage in the input
of the output voltage is either U L or U H depending on the polarity of the
bias voltage.
Output voltage of OA has a saturation level that is about 1-2 V
different from levels of the supply voltage. A comparator is often designed so
that the high and low output voltage levels are compatible with other
components, such as digital logic circuits.
OA frequency response characteristic ensures a certain stability margin
of an amplifier in a feedback mode. This inevitably leads to a reduction in
bandwidth and reduction of slew rate. No restrictions on frequency response
are imposed in a comparator.
13
The most important characteristic of a comparator is response time or
delay time of signal propagation. This is the time between switching input
voltage and the time when the output voltage reaches a certain level. Usually
90% level is used. Response times of comparators are typically from 1 ms to
10 ns.
Change in input voltage, required to switch a comparator from one
state to another (sensitivity), is very small, typically from 0.1 to 3 mV. Due to
low input voltage output voltage switching of a comparator almost always
corresponds to a saturation level – either U L or U .
Bias voltage U CМ is another important characteristic of a comparator,
since it leads to a shift of the switching point in input voltage. Comparator
bias voltage usually ranges from 1 to 10 mV.
Since comparators are not used as linear amplifiers, but as key devices,
H
U0
_
U вх
UH
U0
+
R2
UW
R1
UL
U оп
U i( L - H )
а
U i ( H -L ) U i
b
U0
UH
U0
UH
UL
UL
t
U0
U оп
U вх
c
t
U0
U i( H -L )
U i (L -H )
t
d
t
Fig. 1.7
positive feedback can be successfully used in them to increase gain and to get
some hysteresis in mutual characteristic U O  f (U i ) . The increase in gain
leads to the fact that the amplitude of the input voltage, required to switch the
comparator, is reduced to very small quantities.
The circuit of a comparator with positive feedback is given in fig.1.7,
its transfer characteristic is shown in Fig. 1.7 b. Input voltage level when
switching of the output voltage from low to high takes place, is given by
U i L  H   U ОП R1  U L R2  R1  R2 ,
and the formula for the output voltage required for switching from high to
low, can be written as
14
U вх
U0
U оп
U i H  L   U ОП R1  U H R2  R1  R2 .
The width of the hysteresis loop is given by
Fig. 1.8
UW  U H  U L R2 R1  R2  .
In some cases, hysteresis loop is required to avoid the uncertainty of a
comparator switching point, i.e. prevent “bouncing” (Fig. 1.7, c). In Fig. 1.7g
a switching characteristic in case when there is a hysteresis loop is shown. If
the width of the hysteresis loop UW exceeds peak input voltage fluctuation,
switching time of a comparator will be strictly limited, with no “bouncing”.
Industrial comparators are made in the form of IE (K554SA1). A
graphic symbol of a comparator of integral performance is illustrated in Fig.
1.8.
1.4. SAMPLE AND HOLD CIRCUIT
To store changing analog signals for the time of conversion, switching
and other operations in data collection systems a sample and hold circuit is
used (Figure 1.9).
_
_
+
U1
U0
CН
+
Управляющее
Control voltage
напряжение
Fig. 1.9
Рис.
1.9
A field-controlled transistor with pn junction is used in the circuit as
an analog key.
At the end of the short time interval of sampling analog switch is
closed. It allows a capacitor C Н to become electrically isolated from the
input signal and voltage C Н , and hence output voltage U 0 remains
essentially equal to input voltage which was on a capacitor at the end of the
sampling interval. Nevertheless, there will be some voltage drop across a
capacitor during storage interval due to various leakage currents, including
15
field-controlled transistor leakage current, input OA current and internal
leakage current of a capacitor.
The most important characteristics of a sample and hold devices
include: sampling time - time from signalling to the sample prior to forming
an output signal; aperture time - time interval between the signal on the
storage and opening the key point, time of information erasure - change in
output voltage due to discharge storage capacity, pass-through - a part of the
input signal which is due to the finite resistance of open-loop key is
transmitted to the input.
In integral performance all sample and hold elements are located on the
same substrate, except for a condenser C Н which usually is an external
component.
2. ELEMENTS AND COMPONENTS OF ADC
Electrical signals, as the objects of processing, by its nature are analog
signals, i.e., they are continuous functions of voltage or current. Therefore, in
the process of formation and processing of these signals, with the help of
digital devices, transformations into digital form and vice versa have an
important role.
To perform these operations analog-to-digital and digital-to-analog
converters (ADCs and DACs) are used. The former connect a source of
analog signals with digital processing while the latter are primarily designed
for connecting digital devices, signal normalization and signal processing
with analog data consumers.
2.1. DAC
U ОП
Digital-to-analog
converter (DAC) - is an IDE
which converts digital input
code to output analog voltage
or current which are binaryweighted equivalents of a
digital input code. A simple
example of a N -bit DAC is
shown in a circuit in Fig. 2.1.
Output voltage is given by
X1
R
2R
R ОС
4R
_
2
N -1
R
+
Fig. 2.1
16
U0
X U
X U
X U 
XU
U 0  RОС  1 ОП  2 ОП  3 ОП    NN 1ОП  
2R
4R
 R
2
R 
 2RОС R   U ОП X1 2  X 2 4  X 3 8   X N 2 N ,


(2.1)
where X 1 - the most significant bit (MSB), X N - the least significant bit
(LSB).
Output voltage corresponding to the input code ..... 0001, is equal to



U 0 МЗР  2RОС R   U ОП 1 2 N  RОС R   U ОП 1 2 N 1

Output voltage corresponding to the input code 1000 ... is equal to
U 0 СЗР  U 0 МЗР  2 N 1 Maximum output voltage is generated when the
input code is 111 ... and is



U 0 max   2U 0 СЗР  U 0 МЗР  2 N  1  U 0 МЗР  2U 0 СЗР 1  1 2 N

Nominal output voltage of the full word length (bit grid) is given by
U 0 ПС  2U 0 СЗР  2 N U 0 МЗР
and, thus, greater than the maximum output voltage U 0 МЗР .
Many DAC output voltage of the full word length is set equal to
10.000 V.
Consequently,
in
the
4-bit
( N =4)
DAC
U 0 МЗР   10,00 2 N  10,00 2 4  0,625 B. Output voltage corresponding to
input the code 1000, is equal to U 0СЗР  U 0ПС 2  5,00 B and output
,
voltage when the input code has the value 1111 is
U 0max   U 0ПС  U 0МЗР  10,00  0,625  9,375 В .
The main disadvantages of the
R ОС
circuit (see Figure 2.1) are determined
R
R a 2R
by the need of the use of resistors with
_
U 0 a large range of denominations, such as
2R
2R
2R
2R
1R-1024R for 10-bit DAC.
+
XN
X N -1
X1
One of the rational ways to
reduce the number of resistor values is
U ОП
Fig. 2.2
17
to use resistive (ladder) of the matrix R-2R, shown in Fig. 2.2. Since the
potential of the summing point of the OA is zero, then by analyzing an
equivalent circuit shown in Fig. 2.3, can be written for a point A.
U a  U ОП X 1K1  U ОП X 2 K 2    U ОП X N K N
,
where K i -is a coefficient of
R
R
a
transmission to the point of discharge
2R
2R
2R
2R
2R
from the digital code corresponding to
the index. Values of the coefficients can
be determined by changing the
U О П X N U О П X N -1 U О П X 1
configuration of the equivalent circuit,
subject to the unity of equality only one
Fig. 2.3
digit numeric code. From the circuit it can be seen that the voltage transfer
ratio of any link to the subsequent is 1/2, except the last level, where the
coefficient
is
equal
to
1/3:
K1  1 3; K1  1 321;; K N  1 32 N 1 ,
we obtain


U a  2 3U ОП X1 2  X 2 4  X 3 8   X N 2 N .
When ROC  3R DAC circuit (Figure 2.2) implements the expression
(2.1).
In the circuits above assembly transistor operating in a pulsed mode are
used as keys to improve performance. There are many different types of
DACs in the integral version of the input code word length of 8 to 16 and a
conversion time of 5 ms to 35 ns (for example, IE K572PA1, studied in the
lab).
2.2. ADC
Analog-to-digital converter (ADC)
converts analog input voltage U a to an
output binary digital code corresponding to a
quantized input signal. In Fig. 2.4 transfer
characteristic of ADC is shown. Note that
D
i
g
i
t
a
l
111
110
101
100
011
010
c
001
o
d 000
e
0
-1 М З Р
1
2
3 4
5
6 7 Ua
1
2
3 4
5
6 7 Ua
а
18
б
Fig. 2.4
the output digital code can take only certain discrete values, so systematic
errors are inevitable during conversion process; such mistakes are called
quantization errors. Quantization error is defined as a difference between an
analog voltage that corresponds to the output code and the actual analog input
voltage. In Fig. 2.4 b a plot of the quantization D 1 1 1
i
error corresponding to the transfer characteristic g 1 1 0
is shown (Fig. 2.4 a). Note that the maximum it 1 0 1
quantization error is equal to the price of LSB a 100101
l
input code (1 LSB).
010
c
The maximum quantization error can be o 0 0 1
reduced to  0.5 LSB offset the additional d 0 0 0 1 2 3 4 5 6 7 U a
e
а
analog input signal at -0.5 LSB and +0.5 LSB
+ 1 /2 М З Р
reference voltage, which compares the analog
0
U
signal. Transfer function, obtained at a bias of - 1 /2 М З Р 1 2 3 b4 5 6 7 a
0.5 LSB is shown in Fig. 2.5, and a
Fig. 2.5
corresponding distribution of quantization error - in Fig.2.5, b. The maximum
quantization error is equal to  0.5 LSB, can be observed in each sub-band
input voltage.
2.2.1. INCREMENTAL ADC
Uа
ГTone
Т
In a feedback circuit, in a Аналоговое
Analog input
generator
voltage
lot of ADC, DAC is used. The Входное
напряжение
&
simplest ADC with DAC in a
feedback circuit is incremental
NN-bit
раDAC
зрядный
РгВЫХ N
ЦАП
ADC (Figure 2.6). The digital
Strobe
Строб
N
output N-bit binary counter is
N
connected to the N-bit DAC,
N-bit
N
раcounter
зрядный
N-bit
digital
Nразрядный
счетчик
code
which produces step output
цифровой код
voltage. DAC output voltage
Dump
Сброс
Fig. 2.6
increases from the discrete
1U 0 МЗР  to full discharge voltage of the bit grid 2 N U 0 МЗР . Comparator
compares this voltage with the input analog voltage until the DAC voltage is
lower than the analog input voltage U a and the output of the comparator has
a high level.
This layer keeps the valve (Figure 3I) open, and the clock, passing
through it, get on the counter, an increase in the output code which causes a
further increase in voltage output DAC. As soon as the voltage rises above
the level of the DAC analog input voltage, the comparator output appears
low. At the same time the valve closes, and the counter stops counting.
19
After a while the STROBE signal is high, N-bit output register is
available for recording, and the binary code of the counter is fed to the digital
output of the DAC. After STROBE pulse a DUMP pulse resets a counter,
after a while it begins to count again, and thus begins a new cycle of
transformation.
To handle the full input voltage of the discharge grid in the N-bit
converter, the counting must be 2N clock, so this type of ADC belongs to
relatively slow drives. In 14-bit ADC of this type conversion time is equal to
214ТС=16384 ТС. If we take Tc = 100 ns, the resulting conversion time is 1.64
ms, and the corresponding speed - 610 cycles per second conversion.
Accuracy of counting ADC is a function of bias voltage, gain of the
voltage comparator and DAC accuracy. Most often the main factor, which
determines ADC accuracy, is a precision DAC.
Another ADC type with feedback, the feedback loop which is the
DAC, ADC is a successive approximation. Accuracy of the ADC is basically
the same as that of calculating ADC but they have substantially less
conversion time that explains their popularity.
2.2.2. SUCCESSIVE APPROXIMATION ADC
Successive approximation ADC - the most popular type of ADC since
it combines high accuracy and high conversion rate. In Fig. 2.7 a generalized
block diagram of the successive approximation ADC is shown. In N-bit
converter, successive approximation register consists of N triggers which are
set in one state (X = 1) one by one, and their outputs are digital DAC inputs.
DAC output voltage is compared to analog input voltage.
A significant bit trigger U а
(indicator) is set first in one state
so that the first analog input
voltage is compared to DAC
DАC (N -bibit
output
voltage,
which
corresponds to the voltage СЗР
U СЗР  U ПС 2 . If the analog
УсControl
тройстNN-bit
-разsuccessive
рядныйapproximation
регистр
во уdevice
правregister
input voltage is higher U СЗР , a последов. приближений
ления
significant bit trigger remains in
УстрSynchronizer
ойство синa single state ( X 1  1) for the
хронизации
subsequent conversion cycle. If
Fig. 2.7
the analog input voltage is less
20
U СЗР , then the significant bit trigger is reset to zero ( X 1  0 ) and remains in
this state until the end of the conversion cycle.
Then, in one state is established the following trigger (second bit),
while the DAC output voltage is equal to U ПС  X 1 2  X 2 4  , and X 2  1 . If
this voltage is less than the analog input voltage U a , the second digit is equal
to unity ( X 2  1 ). If it is greater than the analog input voltage, the second bit
is reset to zero. This process is repeated for all remaining triggers (only N
times) until the completion of the conversion cycle. In each case, if the
analog input voltage is greater than the DAC voltage, the next flip-flop stores
its current state. If the analog input voltage is less than the DAC voltage, the
trigger, which was last set in one state ( X  1) is reset to zero ( X  0 ).
Thus, successive approximation ADC voltage occurs and, hence,
corresponding numerical codes to the analog input voltage take place,
starting with the superior at the beginning of a conversion cycle and ending
with the least at the end of the conversion cycle.
For example, consider a 10-bit successive approximation ADC with an
output voltage of the discharge full grid DAC U ПС  10,24 B at the same
time U МЗР  10 мВ . We also assume that the output voltage is shifted by 0.5
МЗР to minimize errors.
For the analog input voltage U a  7,5 B values of output codes of
successive approximation register and the corresponding DAC output
voltages are shown in
Table 2.1.
Number of Trigger conditions
synchroX 1 (СЗР)  X N (МЗР)
impulse
1
1000000000
2
1100000000
3
4
5
1010000000
1011000000
1011100000
6
1011110000
7
8
9
1011101000
1011101100
1011101110
21
Output voltage of DAC
(offset +0,5 МЗР), В
5,125
7,685
X2  0 )
6,405
7,045
7,365
7,525
X6  0)
7,445
7,485
7,525
(сброс
X2 ,
(сброс
X6,
(сброс
X9,
X9  0)
10
1011101101
7,495
Conversion will be completed in 10 cycles and the final state of
triggers of successive approximation register will be 1,011,101,101 which
correspond to the DAC output voltage 7.495 V. The resulting quantization
error is 5mV or 0.5 МЗР.
When analog input voltage is less than 5mV output code is equal to
0,000,000,000, and the DAC output voltage is equal to 5mV. When the input
analog voltage is 5 to 15 mV the output code is 0000000001. The maximum
output voltage of the DAC (including offset of 0.5 МЗР), corresponding to
the digital output code of 1111111111, is equal to
U max  10,24 B 10 мB  5 мB  10,235 B
The maximum analog input voltage which can be converted to the
quantization error does not exceed 0.5 МЗР and is equal to 10.240 V which
corresponds to the output voltage of the DAC total word length.
The output code of the ADC of successive approximations can be
removed not only in a parallel form at the end of the conversion cycle, but
also consistently remove in the output of the conversion process.
Total conversion time of N - bit successive approximation ADC is
approximately equal to  N  2 TC where TC - a period of clock pulses which
is usually equal to 1 ms. Consequently, 12-bit ADC successive
approximation will have total conversion time about 14 microseconds.
Compare this value with a conversion time 2 N TC of ADC countable type,
which is 4 ms.
2.3. ANALOG-DIGITAL AND MULTIPLICATION-DIVISION UNITS
ADCs and DACs, except for actual conversion, are able to produce
operations of multiplication and division. By using these features, you can
expand functions of the device input to the microprocessor spending some
functional transformation of the signals from the sensors to the input of the
processor, and thereby increase productivity of data processing systems.
Consider production of multiplication operations on the basis of DAC.
The operation of multiplying DAC circuit is produced itself, as the voltage at
the output of DAC
U0  U ОП X1 2  X 2 4  X 3 8   X N 2 N .


22
U ОП  U ВХ 1
X { X 1 , X 2 , X N }  X ВХ 2 ,
If
and
then
U 0  U ВХ 1 X ВХ 2 , this expression implements the multiplication circuit of
the analog signal to digital.
Circuits of analog and digital, and digital switches and sample-storage
circuits expand functions of a device multiplier (Figure 2.8) and divider
(Figure 2.9).
If a code combination on the control inputs of analog (AS) and digital
(DS) switches corresponds to specific open-analog and digital channels, i.e.
УпрАК 1  001 УпрАК 2  0 ; УпрАК 3  000 ; УпрЦК  000 , The voltage at
the output
U ВЫХ1  U ВХ2 X ВХ1 .
By changing code combinations at the inputs УпрАК 1 , УпрАК 3 ,
УпрЦК , the following can be obtained
U ВЫХ i  U ВХ j X ВХ k ;
i  1,2,,8 ;
j  2,3,8 ;
k  1,2,,8 .
We introduce a temporal separation of the device functioning into two
cycles t1 and t2 for recording results of SHD. In this case: when t1 and code
23
combinations at
УпрЦК  000
the
control
inputs
УпрАК 1  001 ;
УпрАК 2  1 ;
U ВХ 1  U ВХ 2 X ВХ 1 ,
When t2 and code combinations at the control inputs of
УпрАК 1  000 , УпрАК 2  0 , УпрЦК  000 , УпрАК 3  000
U ВЫХ 1  U ВХ 2 X ВХ 1 X ВХ 1 .
The following can be obtained by changing code combinations at the
inputs
U ВЫХ i  U ВХ j X ВХ n X ВХ m ; i  1,2,,8 ; j  2,3,8 ; m  1,2,,8 .
Next, implement time operation of the device for three (or more) clock
cycles, in this case it is possible to obtain product signals to any number of
digital inputs (1 to 8).
Division operations are implemented on the basis of ADC. ADC is shown
in Fig. 2.9. Voltage at the DAC output at any given time is equal to

U ВЫХ
 U ВХ 2 X ВЫХ . Code meter combinations change according to the

 U ВХ 1 the
natural series of numbers from 0 to N. At the time when U ВЫХ
comparator changes its state from “1” to “0” and prohibits signals receipt
from the oscillator clock to the summing input of ГТС counter. In this case,
U ВХ 2 X ВЫХ  U ВХ 1 or X ВЫХ  U ВХ 1 U ВХ 2
Elements for switching analog signals in the circuit are shown in Fig. 2.9,
the same as switching analog signals in the circuit shown in Fig. 2.8, allows
implementing dependence
X ВЫХ  U ВХ i U ВХ j ; i  1,2,,8 ; j  1,2,8 .
Separation of the device functioning at n clocks reveals a possibility of
implementing more complex relationships:


X ВЫХ  U ВХ i U ВХ jU ВХ k U ВХ n ;
i  1,2,,8 ; j  1,2,8 ; k  1,2,8 ; i  j; i  k ; i  n
Combining functions of multiplier and divider devices in terms of a
single analog-digital multiplier-divider unit, one can create a computing unit
which functional characteristic has the following form
24
Z   X1 X 2  X n  Y1Y2 Yn  ,
where X , Y , Z - variable functions of time which can be represented as
analog as well as digital signals.
3. MICROPROCESSOR SYSTEM
Information system shows how various devices are connected to the
microprocessor. Typical subsystems - adder-subtractors, counters, shift
registers, RAM, ROM, encoders, decoders, selectors, clock generators. This
section deals with microprocessor-based systems and methods of data
transfer in these systems.
3.1. ARCHITECTURE OF DIGITAL COMPUTERS
A simple computer contains five units: input source of information,
control and arithmetic operations that make up a central processing unit
(CPU) also memory and output devices of information processing. Devices
that are placed outside CPU are often referred to as peripheral devices.
Physical devices are hardware used by a program installed in the
memory which requires a list of procedures performed by a processor. A list
of commands (procedures) is called programming. The list of commands is a
program that is stored in memory temporarily or permanently. These
programs process information usually referred to as data. Software is also a
general term that comprises all programs. Thus, computer operates in the
following order: program and data are loaded into CPU and installed in a
designated area of the memory. CPU reads the first command from the
memory, processes and runs it. Once processing is complete, the result is
transferred to the output. Typically, CPU in such systems is a
microprocessor.
Microprocessor (MP) – a software-controlled device which can process
digital data and provide its control, it is built, as a rule, on one or more very
large scale integrated circuits (ASICs). In Fig. 3.1 architecture of a
conventional computer is shown.
25
От
периферийных
From
peripheral devices
устройств
Шина
Control bus
управления
Шина
Data bus
line
данных
П
орты
Ports
ВInput
ходы
МикропMP
роцессор
МП
УControl
правл
енsum
ие
and
и арфметика
Program
memory
Пам
ять пр
ограмм
RROM
ЗУ
ПамятStorage
ь данных
ОRAM
ЗУ
ВOutput
ыходы
ПPorts
орты
To peripheral
devices
Address bus
Fig. 3.1
Microprocessor controls all systems by means of control lines. There is
an address bus in parallel with control lines (e.g., 16 parallel conductors).The
address bus selects the memory cell data input ports or output data. Port - a
hardware device which provides a connection between MP with any device
of input or output information (keyboard, screen, etc.). Data bus line (e.g., 8
parallel conductors) is a bi-directional and is used to transfer data to a central
processing unit or information from it. The microprocessor can send data to
memory or to get them out of it through the data bus line. The program is
constantly in the memory, i.e. located in ROM. User programs which are
intrinsically changeable and placed in RAM with the data. RAM is shown in
Fig. 3.1 as a memory for storing data.
Here are the data used in the implementation of specific programs.
26
3.2. PC ADDRESS DECODER
Consider a 4-bit microprocessor system presented in Fig.. 3.2. This
system uses only 8 wires in the address bus and 4 conductors in the data bus.
RAM capacity is 64-bit IE
Address bus
ДешAddress
ифратор
decoder
Data
bus
МикропMP
роцессор
адреса
Линии
Access line
выборки
микросхемы
(0-15)
Линии
Access
line
выборки
микросхемы
(16-31)
RAM
О
ЗУ
(16х4)
0
БуTSO
фер
buffer
с тремя
состояниями
RAM
О
ЗУ
(16х4)
1
БуTSO
ф ер
buffer
с тремя
состояниями
Fig. 3.2
Address decoder, shown in Fig. 3.2 determines a kind of RAM to be used
and sends an enable signal through the access line. At any time, the enable
signal is given to only one access line. Address decoding unit consists of a
conventional combinational logic elements. RAM address 0 is selected when
cells are 0-15, RAM 1 - when cells are 16-31.
Tristable output buffers (TSO
A
1
buffers), as shown in Fig. 3.2,
A
A
disconnect the output of the relevant
1
A
МP
A
RAM from the memory data bus when
A
1
A
RAM is not involved in data transfer.
A
At any given time only one RAM is
Address decoder
ME
Access line
allowed sending data through a
ОЗУ A D A
(addresses
0-15)
(16х4) A D B
common data bus. Access lines are
ADC
0
ADD
also used to switch these buffers.
7
6
5
4
3
2
1
0
RAM
ME
ADA
(16х4) A D B
ADC
1
ADD
Access line
(addresses 1631)
RAM
ОЗУ
Fig. 3.3
27
When buffers are off, they say that output buffers are in high impedance
state, at the same time they are safely disconnected from the four data lines
connected to their inputs.
Logic circuits are used in a simple address decoder shown in Fig. 3.3.
In this example, only when all four address lines receive logic 0 signals from
A7 to A4 there is a low level at the output of the lower four-input gate OR
If these four line address decoder (Figure 3.3) are supplied with a binary
combination of 0001 ( A7  0 , A6  0 , A5  0 , A4  1 ), then switches the
upper gate OR. Binary combination of 0001 gives a rise to a low level at the
output of the gate in the decoder address, i.e. it leads to distribution of an
active signal level to the bottom line of the access RAM line. As a result
lower RAM is released. Address decoder, shown in fig.3.3, decodes the state
of the four most “senior” address lines to give the desired logic level at the
input of each sample chip RAM. States of the four most “junior” address
lines (from A0 to A3 ) are deciphered within the RAM chips, as a result the
exact address of a 4-bit words is chosen.
In the microprocessor system shown in Fig. 3.2 and Fig. 3.3, 8 address
lines are used. This means that the microprocessor can generate 256 (28)
different addresses.
3.3. ROM INTERFACE
Most of the microprocessors are functionally limited. Most of them
contain very few memory and I/O ports that connect them via interface with
peripherals. Interface - a set of standardized hardware and software required
to connect these devices to the system or one system to another. Among other
properties of the interface, we note their capability to solve synchronization
tasks, select the direction of data transfer and sometimes bringing levels or
waveforms.
Consider a task aimed at developing ROM interface. In Fig. 3.4 part of
the system, including MP and ROM is shown. ROM outputs D0  D7 are
connected with 8 data bus lines. The only way of RD read control comes
from the MP to the input activation of the OE ROM.
28
A 12 - A 15
ДешAddress
ифратор (4 )
аdecoder
дреса
Адресная
Address шина
bus
A 15
A0
RD
A 0 - A 11
D7
МP
D0
Шина
Data
bus
данных
(1 2 )
Линия
выбора
Die access
line кристалла
OE
A 15
ROM D 7
4 К хУ8
D0
A0
(8 )
CS
Fig. 3.4
12 lines of the address bus LSBs ( A0  A11 ) are connected with a
permanent storage device with a capacity of 4K-12. A decoder built into the
ROM of IE can access any of the 4096 (212 = 4096) 8 - bit words of ROM.
Address lines of the four most significant bits ( A12  A15 ) are in a
combinational logic device - an address decoder. To access the ROM and
read data from it to MP: to intensify the address line A0  A11 , set the low
level signal to the control line reading, set the low level signal on the line of
the address decoder and the die.
We assume that MP should contact the memory address 0000H (0000
0000 0000 0000 2). Lower 12 bits of address lines are connected to the
contour of the decoder ROM A0  A11 . Address also belongs to the older 4bit A12  A15 . They are decoded by decoder addresses. If ( A12  A15 ) =
00002, the address decoder outputs a signal that activates the chip-select
input CS (Figure 3.4). Thus, the older 4-bit address select segment of
memory, and the lower 12 bits define the desired memory cell in this
segment.
Addressing and synchronization play an important role in ROM
interface. Addressing has been considered, now consider synchronization. In
Fig. 3.5 timing diagram of signals of the MP is shown. It controls reading 8bit words of ROM.
The upper line of the chart represents the transition to the address lines
A0  A15 of the appropriate logic level. According to Fig. 3.4 address lines
29
A0  A11 activate address inputs of ROM, while the address lines A12  A15
are decoded by decoder address and
MP signals
Memory reading
Address bus  A0  A15 
 
Read output RD
Вводимые
данные ( D0  D7 )
Input data
Input
Ввод
Время
Reading доступа
access timeк чтению
Fig. 3.5
activate the chip CS select input of the ROM. After some time, output
reading control RD of MP activates the data output from the ROM. The data
given here is placed on the data bus and are accepted by the MP.
In Fig. 3.5 critical timing constraints are shown. Once the appropriate
logic level input is established on the address lines, and CS ROM is
activated, a certain amount of time to retrieve word data is needed. This time
is required for internal ROM decoders to find a desired byte in the memory.
In Fig. 3.5 circles and arrows are used. These indicators, when
changed, refer to relations of cause and effect on a temporary chart. As an
example, transition from H-to L-level (from HIGH to LOW) at the read
output switch tristable MP data bus outputs from the state of high resistance
to the state of receiving input data. The dashed part of the timeline on the
input line corresponds to high resistance. In the transition from L-to H-level
RD output MP data bus outputs will switch back to the third condition and
will not accept data from the bus. Interface with RAM is considered similar
to the circuit. Its uniqueness lies in the possibility of not only read
information from the memory, but also record information in RAM.
3.4. INTERFACE WITH I/O PORTS
Input or output operation involves data transfer from (or in) required
peripherals. Developers release I/O ports in the form of IE, for example - 8bit Intel 8212 I/O element. Intel 8212 integrated circuit can be used as an
30
adapter input or output port. The function of the adapter is regulation of
output or input from MP interface to peripherals. In Fig. 3.6 a typical MP
which has an interface with a seven-segment indicator element of the Intel
8212 is shown. This indicator is periphery. In the diagram MP has an isolated
I/O. Note that in this case, the output line selection device is fully decoded
through eight address lines of the least significant bits ( A0  A7 ).
In Fig. 3.6 IE 8212 is used in the output port. At MD control state
input H-level is set. The lines of data bus connected to eight input lines
are
DI 0  DI 7 of the element BB 8212, which output lines DO0  DO7
connected to the inputs of the indicator. Intel 8212 element has eight data
latches (8-bit parallel register) and output buffers (8 tristable elements). Two
choice devices inputs DS1 and DS 2 control 8212 element which is used in
this I/O.
When DS1 is activated by L-signal and DS 2 -H-signal data received
from the bus are latched by data latches and appear at DO0  DO7 outputs
activating indicator segments.
A7
ДAddress
ешифdecoder
ратор ( 8 )
адреса
A
(1 6 )
0
A 15
D7
МP
A0
(8 )
D0
Record line control
DS1
Линия
Choice выбора
device lineустройства
(HIGH-Output)
(LOW-Input)
Управление
State control
HIGH состоянием
HIGH
HIGH
ЭлI/O
емElements
ент ВВ
Intel 8212
DS2
Защ
елки
Data
M D даlatches
нных
ф ер ы
C L R БуOutput
Input adapter
buffers
вы
вода
interface
DO0
DO7
Peripherals
Fig. 3.6
31
In Fig. 3.7 timing circuit of the port Intel 8212 in a state of withdrawal
is shown. Once input control signals DS1 and DS 2 are activated output
data are captured in the I/O port and placed at the output pins. Output buffers
are enabled; therefore, latched data appear even after control lines DS1 and
DS 2 are back in a clear condition.
3.5.
INTERRUPT SYNCHRONIZATION OF DATA TRANSFER
IN I/O DEVICES
According to above mentioned information the program sent a command
to MP to enter data into the port, however, data were available and were
placed in a special place. Therefore, this is not always the case, since
operation speed of peripherals (such as a keyboard device) is different from
MP operation speed. In this case there are several ways to solve the problem.
These include techniques of polling and interruptions.
Polling technique is also called programmable I/O. This is the simplest
method of synchronization, it is used in small dedicated devices. The basic
function of a polling technique is to input and (or) output data in series
implementing a polling cycle in a program.
In general, one or more I/O devices can be polled during a cycle. MP polls
the first device – if it requires maintenance or not, and if so, sets a status
indicator, i.e. a device is maintained. Otherwise, MP proceeds with polling.
The system shown in Fig. 3.8 is equipped with an on-demand interrupt
line ( INTR ), the line informs MP that data are ready to be transferred to
32
CPU. MP, activated by H-signal, runs a current command, interim results are
sent to a special memory area and branches in a sub-program of interrupt
maintenance. Then MP returns to the main program.
Microprocessor has an I/O interface port with a keyboard device, built on
IE 8212 (Figure 3.8). Control (MD line) of device state has L-level and has
an impact on an input adapter. Clear input CLR in the device 8212 is
deactivated by H-signal. From a keyboard device regular 8-bit data get to
data inputs DI 0  DI 7 of 8212 element. In this system a strobe line ( STB )
controls data latches, whereas inputs of choice devices DS1 and DS 2 of
Periphery(клавиатура)
(keyboard)
Периферия
Strobeстроба
line
Линия
ST B
(HIGH - Вывод)
Управление
State control
input
(LOW – Ввод)
состоянием
HIGH
LOW
output
MD
CLR
Линия выбора
устройства
Choice device
line
Линия
ВВ line
чтения
I/O reading
Data
Защ
елки
D S 2 дlatches
анных
DO0
БOutput
уферы
вbuffers
ывода D O
7
D S 1 ЭлеI/Oмеelement
нт ВВ Intel 8212
(8 )
IN T
1
Линия
Interruptзапроса
request
line
прерывания
A7
Деш
ифратор ( 8 )
Address
decoder
адреса
A
0
(1 6 )
D7
A 15
МP
A0
D0
IN T R
Fig. 3.8
8212 element control output buffers.
A keyboard device must put an 8-bit word at the input data of 8212
element and provide impulse HIGH (strobe) to keep data in internal latches
of I/O port. These events are shown in fig.3.9 by three upper graphs.
According to a lower graph in Fig. 3.9, after data are gated by latches,
circuit element 8212 provides interruption impulse INT which is sent to MP
through an interrupt request line, control lines of output buffer ( DS1
and DS 2 ) are activated. Curves 3 and 6 illustrate location of captured data by
DS1 and DS 2 commands of Intel 8212 element on data bus in a very short
33
period of time. Note that outputs of I/O 8212 Intel return in its third state
immediately after buffer commands DS1 and DS 2 are cancelled.
Consider interface of a keyboard device (Figure 3.8) in case when the
system has an isolated I/O. Special control signal activates DS1 input of Intel
8212 device. Eight address lines with the least significant bits ( A0  A7 ) are
fully decoded by an address decoder which outputs activate a line input DS 2
through a choice device line ( DS1 and DS 2 control output buffer of I/O
8212 element). An inverter coordinates L-active way INT Intel 8212 with Hactive input of INTR MP.
Сигналы
элементе ВВ
I/Oна
signals
Состояние
входа
Input state
Входные
Input data
данные
Input DI 0  DI 7 
2
Strobe input STB
1
Данные
захвачены
Latched
data
Data latches
5
Buffer control
DS1
4
DS2
3
6
Вывод
Output
data
данных
Data bus outputs
DO0  DO7 
Interrupt exit mistake INT
Fig. 3.9
Interruption informs MP that I/O is standby and maintenance is required.
This operation is implemented by a special program which interrupts service
routine. If multiple devices cause MP interruption, a signal interruption lines
undergo special actions OR and for MP, in this case, it is necessary to
determine a device which will be responsible for I/O interruption (I/O
device). This selection process relates to a polling technique and is called a
circuit of polling-interruption. In this case, each port corresponds to one state
of I/O, which code indicates MP - if the port is ready to input or output data.
There are MPs which are equipped with multiple inputs and commands of
interrupt acceptance or rejection of at least some of these inputs. Some MPs
are equipped with interrupt vector, when MP identifies the device that caused
interrupt, it branches on a service sub-program of a corresponding interrupt.
34
Some MPs are also equipped with devices which can determine maintenance
(service) priority (hardware or software) in the case of two simultaneous
interrupts (interrupt priority arbitration). The system decides whether to agree
with maintenance priority of one of the interrupt, it is usually a part of IE (for
example, device Intel 8259).
The advantage of polling over the interrupt procedure is that the former
requires less hardware and is synchronous under software control. The
disadvantage is the need for very advanced software which takes too much
time of MP in case when there are a lot of devices need to be polled, and the
need for some considerable period of time to respond to a request.
The advantage of interruptions over polling is a speed of response, better
use of MP and the need for less software. The drawback is that MP operation
is asynchronous and requires sophisticated hardware interface.
3.6. ERRORS DETECTION IN DATA TRANSFER
The cause of an error could be: a large “parasitic” capacitance between
parallel lines of a transmission path, speed inconsistency of data receiver and
transmitter, mechanical damage, etc. In order to ensure accuracy of digital
devices special methods of error detection are used.
To detect errors a constant check of transferred data must be carried
out. For this purpose one additional check parity digit is formed and
transferred along with the data. This parity digit complements units in a
transferred code to even, i.e. it contains a unit if it is odd. In Fig. 3.10, a block
circuit of data transfer is shown. In this system, three information categories
A, B, C are sent in parallel for a large distance. Before entering the system
input data passes through a generator control parity bit. This check digit is
transferred with the data which are checked before transfer. If there is an
Output
Transfer
Input
A
B
C
A
B
C
Контрольный
Check bit
Разряд четности
A B C
Генератор
Check bit
контрольного
generator
разряда
четности
Сигнал
Error
ошибки
signal
а
А
В
=1 Parity
bit
С
Р
А
В
С
Р
P C B A
Детектор
Error
ошибок
detector
Сигнал
Error
signal
=1 ошибки
c
b
Fig. 3.10
35
error while transfer, the error detector signals about it. If values of all data
bits in the output of the system are the same as its input there is no error
signal.
In the Table 3.1 an operating principle of error detection is shown.
This table is actually a truth table for a parity bit generator in the system
shown in Fig. 3.10, a. The value of output in each horizontal row of Table 3.1
is defined in such a way that the
Outputs
total number of “units” in the Inputs
Parity bit
line is even (0 “units”, 2 Parallel data
B
A
P
“units”, 4 “units”). Next for the С
0
0
0
table a corresponding logic 0
0
1
1
circuit is selected, in our case a 0
1
0
1
circuit of a check bit generator 0
1
1
0
is shown in Fig. 3.10, b. A 0
circuit that produces a logic 1 at 1
0
0
1
its output whenever its input 1
0
1
0
gets an odd number of “units”, 1
1
0
0
is shown in Fig. 3.10, i.e. it can 1
1
1
1
be used as an error detector.
The system with parity bit only detects errors but does not fix them; it is just
one of the control systems.
3.7. SYSTEM INTERFACE
In most cases, data receivers and transmitters can lag from each other on a
fairly large distance (10 meters). An example of such
Sequence of binary bit
1 0
1
1 1 0
0 0
1 1
0 0
1
Код безNRZ
возвращения
code
к нулю
NRZI code
Code Manchester II
Sequence of binary bit
а
1
0 0 1 1 0
NRZI code
инхросигsignal
н ал
Synchronization
Code Manchester II
b
Fig. 3.11
36
0
arrangement can be a local network area. In this case, use of the system
interface is required. System interface – as a rule a multi-level architecture
(set) of hardware and software tools that exchange information, transfer
messages i.e. command, data and response words. A specific language to
transfer these words is used. A typical protocol word with bit arrangement
contains an initial indicator, address, control and information fields, sequence
words check and a final indicator.
To send words with a bit arrangement NRZ code, NRZI code and
Manchester II code are used.
NRZ code (Fig. 3.11 a) shows a sequence of binary bits of voltage
levels sequence that are constant on the interval of transmitted bits.
In NRZI code “1” is transmitted by lack of change in the level of the
previous bit and “0” – by an inversion of this level (Fig. 3.11 a). Thus, “1”
and “0” in this code may be represented as a sequence of low and high
voltage levels, and the longest sequence of “1” constitutes a constant level,
and the longest sequence of “0” - a periodic bipolar signal.
Manchester II code displays every bit of a binary sequence of level
transition, if a low level is followed by high, “0” is transferred, if a high level
is followed by low – “1”. Transitions occur in the middle of the time interval
allocated to each binary bit (fig.3.11 a). Manchester II code can be easily
obtained from NRZ code if NRZ is sent to the input of a logical equivalence
circuit; the second input receives sync signals in the form of a meander with a
period equal to NRZ code, and in-phase (Fig. 3.11 and b). This code has a
higher noise immunity compared to NRZ code since: firstly, the bandwidth
is between half and full value of clock frequency, while NRZ code - from DC
constant to half the clock speed (lack of DC component when encoding
Manchester II allows applying a simple bandpass amplifier AC, use lowfrequency noise suppression); secondly, use of Manchester II code makes it
possible to detect errors in each transmitted discharge, taking into account
that data transfer takes place in the middle of the interval corresponding to
the bit. Since a high level or low level during bit interval is unacceptable,
such situations may indicate the presence of errors. Decoding “0” (“1”)
while transmission of “1” (“0”) in Manchester II code can occur only due to
interference; inversion of logic levels will occur in each half of the interval of
one bit, however, simultaneous phase inversion within one bit is low.
Finally, application of Manchester II code allows reducing the cost of
transmission lines by eliminating wires to transmit clock pulses on the
interface, since the sequence information in Manchester II code contains both
clock and data signals. Moreover, in application of NRZ code occurrence of
37
phase shifts between data and synchronizing sequences is possible. With a
self-locking feature Manchester II code allows avoiding these problems.
Data from a receiver to a transmitter is transmitted sequentially by
frames shown in Fig. 3.12.
Indicator
(8bit)
Address
Control
Information Representative Indicator
sequence field
field (8,16 field (8,16 field
(8bit)
(8,16 bit)
bit)
bit)
(Random
bit number)
Fig.3.12
To define different parts of a message the protocol of serial data
transfer with a bit arrangement uses position of these parts in a sequence of
bits. The frame on both sides is limited to a sequence of indicators, for
example: 01111110. If the screenshot does not end with the indicator but
with a sequence of numbers  15, it means that the transmitter has completed
the transfer, and other devices on the network can begin data transfer. A
transmitting device can complete the frame by sending a combination from 7
to 14 units, which means the mode of early frame termination.
The receiver in this case does not take the last frame and cannot be
transferred until it receives a command from a transmitting device. The frame
contains address, control and information fields (Figure 3.12). The address
field follows the first indicator of the frame and determines address of the
sender and frame receiver. There are two addressing modes: a basic
addressing mode, which uses an address byte, and an extended addressing
mode, where the length of the address field is 1 byte or more. In the latter
case, if the least significant bit of the first address byte is “0”, the next byte is
a continuation of the address field. This field ends with the first encountered
byte where the least significant bit is “1”. Thus, the address field can be
extended to any number of bytes.
A control field with the length of 1 or 2 bytes follows the address field
to encode commands and responses required to control data transfer line. The
format of a control field is also strictly defined.
An indicator is placed at the end of a frame field of check sequence
which provides error detection (one of the bits of the sequence is a parity bit).
The information field includes actual data sent and information on data
distribution of this field. An important feature of the protocol serial data bitarrangement is the introduction and exclusion of zero which ensures
transparency (a selection) of the data in the frame. Within the frame bit
sequence is between two indicators, a zero is automatically inserted in the
transmission after five consecutive ones and excluded at the reception.
38
Therefore, none of the bit sequence in the frame can be taken as an
indicator, as a combination of interface release.
3.8. STRUCTURE OF A BASIC MICROPROCESSOR
Microprocessor – an all-in-one data processing device controlled by
software stored in the memory.
In their design MPs can be divided into single-chip MPs with a fixed
length (capacity) words and a certain command system; multichip
(partitioned) MPs with a scalable word capacity and firmware control (they
are composed of two or more very large-scale integration circuits (VLSI
circuit)).
Architecture of a multichip MP with firmware control allows achieving
flexibility in its application and a relatively simple means to organize
performance of individual machine operations which improves performance
computers for such MPs.
Despite the fact that performance of multichip MP is significantly
higher than that of a single-chip MP, most applications of the task are
successfully solved using a single-chip MP.
Structure of MP (see Figure 3.13) includes an arithmetic logic unit,
control unit and an internal register unit.
39
An arithmetic logic unit (ALU) consists of binary adder circuits with
fast (parallel) transport, a shift register and a register for temporary storage of
operands (arguments of the function involved in the transaction). Typically,
this device performs commands of a few simple operations: addition,
subtraction, shift, transfer, logical disjunction (OR), logical conjunction
(AND), according to a module 2.
A control unit (CU) controls operation of ALU and internal registers.
According to the operation code it generates control signals for the internal
blocks of MP. Address command with control signals is used to read data
from a specific memory location or to write data into a cell. By CU signals
new sample of the next command is carried out.
An internal register unit (IRU), expands ALU possibilities, it is the
internal memory of MP and is used to temporarily store data and instructions.
It also performs some procedures for handling information.
In Fig. 3.14 a more detailed block diagram of a single-die magnetic
field is shown. IRU contains general purpose registers and special registers:
an accumulator register, address buffer register, data buffer register,
operation register, stack register and a search register.
40
General purpose registers (GPR), its number can vary from 4 to 64, to
a large extent determine computational capabilities of the MP. Their main
function - store operands. But they can be special registers as well.
41
All GPR are available for a programmer who is considering them as a
scratchpad memory. Paired location of registers B and C, D, E, H and L
makes it possible to process double-byte words, called treatment of
“doubles”. Data exchange with GPR (reading and writing data) through a
multiplexer, and the desired register is selected by the selector registers on
signal CU.
An accumulator register, commonly called an accumulator (also known
as a “drive”), is designed for temporary storage of operands and intermediate
results of arithmetic and logical operations performed by ALU. When you
perform an operation with two operands the register contains one of the
operands used, and after completion of an operation - its result. Bit register is
equal to the bit data word.
An address buffer register is used for receiving and storing the address
of the executable command. In other words, it contains the word address to
the issue on the address bus. The possible number of addresses, i.e., directly
addressable memory words, is determined by the bit of this register. Thus, in
16-bit register, changing the values of digits two-byte word, you can place
any of the 216 = 65536 cell addresses (words) of memory.
A data buffer register is used to temporarily store a selected word from
memory before issuing it in the external data bus. Its capacity is determined
by the number of bytes of data word.
A program counter contains memory cell address where bytes of an
executed program are placed. Usually some program commands are in
consecutive memory locations: a number indicating the address of each of the
next cell, one more than the number marking address of the cell. Therefore,
transition to the next command is achieved by increasing the number
contained in the counter command unit. In the course of the current
command, i.e., transfer command from the memory in a magnetic field, the
contents of program counter is incremented and the next instruction address
is generated. If you want to use this command, the command is not stored in
the next, and in another, such as a remote, memory location, then the signal
in the N counter address of the remote cell is recorded.
An operation register receives and stores the code of the next
instruction; the address is located in the program counter. By CU signal
information is transmitted to it from the register.
Stack registers are divided into the stack and stack pointer. Name
“stack” is derived from the English word stack, which literally means a pile
(of wood), a pile (of papers), etc. The MP stack is a set of registers that store
return address commands when accessing the routines or the state of internal
registers in interrupt handling. This collection is organized in such a way that
a word address or data is selected on the basis of “last logged on - comes
42
first”. When writing the next word in the stack are all the words in it are
shifted by one register down. After sampling the words from the stack, the
remaining words are shifted by one register up. The stack can be performed
not only on the internal registers of MPs making up part of it, but to be in
memory, taking it to a selected area. In the latter case, the stack is more
profound, far-reaching, however, to refer to it requires a special case - the
stack pointer.
A stack pointer holds the address of the last occupied cell stack, which
is called the apex. A number which is contained in the index indicates where
the top of the stack. When another word is written in the stack, the number in
the stack pointer is increased. Extracting words from the stack is
accompanied, on the contrary, a decrease in the number of filling the stack
pointer. In addition to this procedure, ability to read without destroying the
contents of any cell stack with a constant number stored in the stack pointer
is provided.
A search register is a set of triggers - indicators. Depending on the
results of operations performed by ALU, each trigger is set to 0 or 1.
Indicator-bits that define the contents of the register indicate conventional
signs: no results, the sign of the result, overflow, etc. This information
characterizes the state of the processor and is important to choose the way of
further calculations.
Let us consider in more detail the main parts of the microprocessor
(see Figure 3.14). The internal data bus connects the main part of the MP.
Bus is a group of lines of communication united by a common functional
feature. In the microprocessor system three types of tire data, addresses, and
control are used.
Bit internal data bus, i.e., the number of passed bits through it
simultaneously (in parallel) corresponds to the bit words to be operated on
MP. Obviously, the capacity of internal and external data bus must be the
same. At eight-megapixel internal bus consists of eight lines which can
sequentially transmit eight-word - bytes.
It should be borne in mind that not only ALU processed words are
transmitted over the bus but also command information. Consequently, a high
enough bit data bus can limit composition (complexity) and the number of
commands. Therefore, data bus width refer to the important characteristics of
a microprocessor - it is to a large extent determines its structure (number of
bits indicated in the figure in brackets next to the blocks).
MP data bus operates on a bi-directional transmission, i.e. it is possible
to transmit words in both directions but not simultaneously. In this case
special buffering schemes and multiplex mode of data exchange between the
MP and the external memory are required. Multiplex mode (from the English
43
word multiple), sometimes called multi-point - a mode of simultaneous use of
a large number of channel subscribers with time-division exchange controls.
An 8-bit arithmetic-logic unit performs all arithmetic and logical
operations. The first ALU input receives a byte from an 8-bit accumulator,
and the second input receives a byte from an 8-bit intermediate register
(register for temporary storage). The result of the addition of two bytes is
transmitted from the output of ALU via the internal data bus to the
accumulator. Such an organization satisfies a single-address microprocessor
arrangement. It is typical that one of the operands involved in the process is
always located in the accumulator which address is given implicitly.
Therefore, when performing addition of two operands it is necessary to
specify only one address - the second operand is contained, for example, in
one of the eight general purpose registers (GPR). Search registers are
connected to ALU, they are designed to store and analyze characteristics of
the operation.
44
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1. Design of electronic devices on integrated circuit/ Edited by S.Ya. Schatz.
M: Sov. radio, 1976.-312 p.
2. Horowitz P. Art of circuitry. -M., New York, 2009.-704 p.
3. Gurov V.V. Design of microprocessors - Internet-University of
information technologies - INTUIT.ru, 2010. - 273 p.
4. Mikushin A.V. Digital devices and microprocessors - Saint-Petersburg.:
BHV-Petersburg, 2010.-832 p.
5. Dinesh S. Dube Electronics. Diagrams and analysis.-M.: Tekhnosfera,
2008.-432 p.
6. James A. Reg Industrial Electronics.-M.: DMK Press, 2011.-1136 p.
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