Download A Novel Continuous-Time Common

10.4
A Novel Continuous-Time Common-Mode Feedback
for Low-Voltage Switched-OPAMP
M. Ali-Bakhshian
K. Sadeghi
Electrical Engineering Dept.
Electrical Engineering Dept.
Sharif University of Tech.
Sharif University of Tech.
Azadi Ave., Tehran, IRAN
Azadi Ave., Tehran, IRAN
[email protected]
[email protected]
critical in low-voltage applications. To measure the settling time
it can be considered that for CM voltage error lower than small
percentage of the desired value, change in small signal model can
be tolerated [4].
ABSTRACT
A novel rail-to-rail and fast continuous-time common-mode
feedback (CMFB) strategy is presented proper for low-voltage
Switched-OPAMP (SO) circuits. The threshold voltage change
due to bulk signal is used to measure the output voltage. To
satisfy speed requirements, averaging common-mode (CM) level
and amplifying error signal are realized in a single block. Finally,
the measured CM level is controlled by applying an error-voltage
dependent current to the output nodes. As a design example, a
modified low-voltage switched-OPAMP in a cascade 2-1
delta-sigma modulator adopting the proposed technique is
presented. SPICE simulation using a 0.18µm technology and
VDD=0.9V is provided which confirms the expected accuracy and
speed of the CMFB circuitry.
Categories and Subject Descriptors
B.7.1 [Integrated Circuits]: Types and Design Styles –
algorithms implemented in hardware.
Figure 1. A modern SC CMFB presented in [5]
General Terms
Design, Verification.
Keywords
CMFB, Continuous-Time, Switched-OPAMP, Low-Voltage,
Delta-Sigma
1. INTRODUCTION
Switched-OPAMP (SO) is a well-known solution for
implementation of switched-capacitor (SC) circuits as supply
voltage decreases below 1.5V [2]. However, to deal with lowvoltage and high-speed SO circuits, it is necessary to develop
new CMFB strategies. As the amplifier output in OFF phase is
connected to positive or negative power supply, the CMFB must
be fast enough to settle the output CM level to the desired value
in a short while after switching ON the amplifier. Also, the
CMFB circuitry should not limit the output swing which is very
Figure 2. (a) Output stage of a typical OPAMP (b) Blockdiagram presentation of the proposed CMFB
Switched-Capacitor strategies result in lower power consumption
and a higher voltage gain so that they have been the best
candidates for CMFB implementation in many circuits reported.
Traditional SC CMFB networks introduce charge error as
consequence of clock feed-through and charge injection which
both arises due to the connection of the amplifier output nodes
with a MOS switch. Also, some instances presented for lowvoltage implementation will lead to large output capacitor
because of the feedback factor imposed. Although some modern
SC CMFB networks, like the one shown in Figure 1, avoid these
problems [5], they face some other constraints for fast OPAMP
switching.
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296
limitation results in speed degradation. However, the bulk pin
can tolerate a full scale signal without changing the activity
region of the MOS. Monitoring the VT fluctuation of a transistor
due to bulk signal can be used to measure the main OPAMP
output voltage. For the scheme shown in Figure 3-a and
assuming a constant bias current, if the bulk voltage is varied due
to VIN, VOUT will be affected as VT changes. Thus a one to one
correspondence can be made between VOUT and VIN.
As shown in the figure, the reset of the sampling capacitors (C1
and C2) to VDD in OFF phase increases the charge in output
nodes to be discharged. The initial condition of Zero for their
voltages needs some additional switches to disconnect the
capacitors from output or it results in signal-dependent charge
loss of integrating capacitors. The CMFB output shown in the
figure is used to control some internal current sources as a mean
to control the output CM level. The loop created between output
and internal nodes can introduce some additional poles and zeros
which in turn can change the transfer function. On the other
hand, the biasing constraints can limit the additional current
imposed to the circuit to discharge the output. Finally, if this
CMFB circuit is used with OPAMP topology shown in Figure 7,
a class AB OTA proper for low-voltage implementation, it needs
some additional transistors to compare the measured CM voltage
with reference, amplify the error signal and to apply CMFB
output current to nodes n1 and n2 [2]. This additional block and
above mentioned reasons can influence the time needed to set the
output CM level.
On the other hand, connecting bulk pin to a full-range signal can
forward bias bulk-source junction and increase the bulk current.
Increase in bulk current can decrease the overall gain by loading
the output impedance. To overcome this problem, the scheme
shown in Figure 2-b can be used. SPICE simulation is done for
both PMOS and NMOS devices to find the best choice and the
best range of value for VDBB. Applying a full range signal to the
bulk pin and performing Fourier analysis, Figure 4 shows the
total harmonic distortion (THD) of the output signal as a function
of VDBB. For the same aspect ratio, it can be seen that the
minimum level of THD for PMOS devices is as high as the
highest level in NMOS case. Furthermore, the DC component of
the output signal for PMOS is negative (-0.3V for VDBB=
0.2V), that with VDD=0.9V it’s out of the range that can be
handled. Although for NMOS transistors around VDBB=0.55V
the minimum THD can be achieved, as the simulation shows, the
voltage across current source is about -0.2V which is impossible
for CMOS implementation. Trading off between THD and
voltage headroom across biasing current source, it can be
concluded that VDBB in the range of 0.2V-0.3V with NMOS
type is the best choice.
In this paper, a new non-linear continuous-time CMFB is
presented. Without manipulation of internal nodes, the output
and input of the CMFB are connected to the output of the
amplifier. Output voltage is sensed due to the variation of the
threshold voltage according to bulk signal. Averaging the output
sensed voltages to calculate the CM value, comparison to
reference voltage and amplifying the error signal is done in a
single block called average-error amplifier. To control the output
CM level, proper amount of current proportional to the amplified
error signal is applied to the OPAMP output nodes. The nonlinear behavior of the Gm module satisfies speed requirement
expected.
2. THE PROPOSED STRATEGY
The output node in most OPAMPs is the cross junction of two
sink and source current sources. Considering channel length
modulation in Figure 2-a, any change in IMa due to VIN results in
variation of output node voltage, Vout, such that IMa=IMb is
maintained. Furthermore, in equilibrium condition and with a
fixed voltage at output node, the injection of any positive
(negative) current to output node, increases (decreases) Vout.
Taking advantage of this well-known fact, the new CMFB
strategy can be developed as following:
Figure 3. (a) Using a NMOS as a voltage sensor (b) Modified
scheme for both PMOS and NMOS
A. Output voltages are measured and averaged to calculate the
CM level.
B. The measured CM voltage is compared to a reference voltage
level and the error signal is amplified using an amplifier.
C. Using a Gm module, a current proportional to the error signal
is injected into the output nodes.
Figure 2-b shows the block diagram representation of the circuit.
In the following sections, the details of low-voltage CMOS
implementation of the blocks are presented.
2.1 Output Voltage Measurement
There are some constraints to apply a full range voltage to the
gates of input transistors in a typical continuous-time CMFB.
The applied voltage should support enough large VGS to keep the
transistors in ON state and any additional circuit to avoid this
Figure 4. THD of output signal in term of VDBB
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2.2 Generation of the Amplified Error Signal
decreases as signal amplitude increases. It leaves easier
constraints for Phase Margin (PM) and Gain Margin (GM) of
the average-error amplifier [1]. Simulation shows that an
OPAMP with 3 degrees PM can be used and the feedback loop
is very fast and stable as well.
For faster response, averaging of the output signals to calculate
the CM level, comparison with reference voltage, and
amplification of the error signal should be done in a single block
called average-error amplifier. The implemented low-voltage
error amplifier is shown in Figure 5-a [2]. The main drawback of
this architecture is the need for an additional block to specify the
CM level. Using additional blocks can result in more
complicated design process as well as slowing the CMFB and
degrading stability. The implemented solution is shown in
Figure 5-b. The following equations hold for circuit shown in the
figure:
VOUT = ( Kg m1 VIN + − g m 2 a VIN1− − g m 2 b VIN 2 − ) × R OUT
VIN + = VαCM,REF
VIN1− = VαCM + VαDiff
Figure 5. (a) Low-voltage amplifier proposed in [2] (b) The
modified amplifier
VIN 2 − = VαCM − VαDiff
VOUT = a × VαCM ,REF − b × VαCM + c × VαDiff (1)
VαCM and VαDiff are the voltage levels proportional to the real CM
level and AC amplitude of the output voltage respectively. As
mentioned in section 2.1, these signals are sensed by the bulk pin
of the CMFB input transistors. Using Equation (1), considering
non-linear effects of CMOS transistors and adjusting the aspect
ratios for transistors, any value can be achieved for a and b
coefficients. Setting c equal to zero, VαDiff term can be removed
completely.
2.3 Charge Injection into the Output Nodes
After the evaluation and amplification of error signal, the proper
amount of current must be injected into the output nodes to
correct the CM level. The used Gm block circuit should be
capable of both sourcing and sinking current with high output
impedance such that the main OPAMP gain is not affected.
Figure 6. Full schematic of the proposed CMFB
The proposed Gm circuit explored in this investigation is a
CMOS inverter. Considering Figure 6, PMOS and NMOS
transistors source or sink current to or from the output nodes.
The difference between these two amounts of current can be
known as the CMFB output current. Using an inverter as the Gm
block circuit has some advantages listed below:
• In a good system design, for desired output CM level the
voltage at the input node of the inverter can be set around
VDD/2. This keeps both transistors in sub-threshold region,
resulting in high output impedance for CMFB. Even in a case
of poor system deign, VGS of one of the transistors is larger
than VT and the transistor is ON. Thus, the output
impedance of only one transistor is parallel to the output of
the main amplifier.
• Because of the nonlinear transfer function of an inverter, the
start of the process is fast and as the output CM approaches
the desired value and the amplified error signal decreases, the
current driving capability is diminished. This behavior results
in fast response with reasonable amount of overshoot.
• Due to the nonlinear behavior of the inverter, the gain of this
block is input-dependent. The open loop gain of the feedback
Figure 7. Low-voltage switched-OPAMP implemented
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Finally, the complete transistor level scheme of the proposed
CMFB is shown in Figure 6. Transistor M10 in conjunction with
ISS3 is used to set the source voltages of M11-13 in the
predetermined range of value for VDBB.
3. EXPERIMENTAL RESULTS
3.1 OPAMP Design
To evaluate the in-circuit performance of the developed CMFB,
it is realized in a well-known low-voltage SO architecture shown
in Figure 7.
The OPAMP is the same as [2], except for four additional current
sources, IST1-4, added to increase the bias current of input
transistors to enhance input Gm. Without this modification, the
quiescent current of M2 and M5 transistors increases as the
current of input transistors rises. To achieve this, either W/L
ratio or VGS of these devices should be increased too. The later
Figure 8. Main OPAMP frequency response
opposes low-voltage consideration and former will cause poor
frequency response. Furthermore, mirror effect leads to the same
amount of increase in the output stage which leads to more
power consumption. Figure 8 shows the frequency response of
the amplifier.
To switch the amplifier the current paths from the power
supplies to the circuit are interrupted with switches MSW1-2 [2]. It
should be pointed out that for fast starting the bias circuit should
not be switched OFF [2]. The same policy should be considered
as switching strategy in CMFB. To satisfy the speed
requirements, voltage sensing transistors, M10-13, should not be
switched OFF either.
Figure 9. Output CM voltage settling
Figure 9 shows the output voltage of amplifier (zero AC
amplitude) with initial conditions equal to 0V and 0.9V. It’s
apparent that within less than 30nsec output CM voltage settles
to 95% of the final value. Within this range, the small signal
model can be assumed fixed [4]. While the gain of the amplifier
equals to 60dB, applying a 20 KHz sinusoidal differential input
signal with the amplitude of 0.4mV results in output THD less
than 0.5%.
The error voltage as a function of the desired CM voltage is
shown in Figure 10. Also Table 1 shows the characteristics of
this amplifier operating at VDD=0.9V.
Figure 10. Output CM voltage error
Table 1. Implemented OPAMP characteristics
Parameter
Value
Unit
Open loop Gain
62.3
dB
GBW (CL=4pf)
39.7
MHz
Phase Margin
68
Degrees
Supply Voltage
0.9
V
Power Dissipation
43.7
µW
Differential Output Swing
±0.8
V
CMOS Technology
0.18
µm
3.2. Delta-Sigma Modulator
The simulated OTA with the proposed CMFB has been
implemented in a cascade 2-1 low-voltage delta-sigma
modulator. The accuracy and stability of the common-mode
voltage in the implemented OTA and fast settling response are
important for fast OTA switching. Although the allowable peak
to peak output voltage swing for integrators is ±0.8V, appropriate
signal scaling coefficients [3] are considered to limit the output
swing of each integrator as shown in Fig.11. Decreased range of
voltages results in faster output settling.
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The characteristics of the simulated cascade 2-1 Delta-Sigma
modulator are listed in Table 2.
Table 2. The implemented cascade 2-1 ∆Σ modulator specs
Density
Parameter
Input Level (Volt)
Figure 11. Probability density function of integrator outputs
in the realized cascade 2-1 delta-sigma modulator
Value
Unit
Dynamic Range
105
dB
Peak SNDR
100.86
dB
Overload Level
-2.49
dB
MHz
Sampling Rate
4.096
Over-sampling Ratio
128
Signal Bandwidth
16
KHz
Power Supply Voltage
0.9
V
Power Dissipation
160
µW
CMOS Technology
0.18
µm
4. CONCLUSION
A continuous-time CMFB circuit is presented. The technique
used to estimate CM level is based on the monitoring of VT
variation due to bulk signal equal to output voltage of the main
amplifier. Because of integrating the averaging, comparing and
amplifying units in a single block and using an inverter as the
output Gm block, the short simulated settling time makes the
CMFB strategy ideal for fast SO circuits. The reported result of
the implemented OPAMP has proven the superior performance
of the proposed CMFB. Also the realized OPAMP with the
proposed CMFB circuitry is used in a cascade 2-1 low-voltage
Delta-Sigma modulator. Limited voltage range for each integrator
output and short settling time of output CM level permits faster
OTA switching. The simulation results confirm the expected
accuracy and speed of the CMFB circuitry in SO circuits.
Figure 12. The simulated Delta-Sigma modulator output
spectrum at VDD=0.9V and 1 KHz sinusoidal input signal
5. REFERENCES
Measurements are performed at clock frequency of 4.096MHz
and there is only 122nsec for each integrator output to settle.
Figure 12 shows the simulated output spectrum at VDD=0.9V and
1 KHz sinusoidal input signal. Considering over-sampling rate
equal to 128, the measured dynamic range is 105dB and the peak
SNDR is 100.86dB (16.5-bit).
[1] Dorf, R.C., Bishop, R.H., Modern Control Systems, Addison
Wesley Publishing Company, Massachusetts, 1995.
Total power dissipation is 160µWatt. Several units like OTAs,
switches, bias circuit, comparators, logic and clock generation
circuits contribute to this power consumption. As mentioned in
Table 1, implemented OTA dissipates 43.7µWatt. Noting the
modulator includes three integrators (three OTAs) and every
OTA is ON for half of the period, the total theoretical amount of
power needed for OTAs is 66µWatt. As simulation shows, the
real amount of power differs from the theoretical value. The
measured power dissipated by OTAs is 97µWatt and the
difference is due to the CMFB strategy. As explained in section
2.3, an inverter is realized as the output Gm module. After
switching ON the OTA, to adjust the output CM level a large
amount of current is injected into output nodes. This short while
current causes the difference between the theoretical and the
measured value of the power dissipated by OTAs.
[3] Rabii, Sh., Wooley, B. A., The Design of low-voltage, lowpower Sigma-Delta Modulators. Kluwer Academic Publishers,
Boston, 1999.
[2] Peluso, V., Steyart, M., and Sansen, W., Design of LowVoltage Low-Power CMOS Delta-Sigma A/D Converters. Kluwer
Academic, Boston, 1999.
[4] Razavi, B., Design of Analog CMOS integrated Circuits,
McGraw-Hill, Boston, 2001.
[5] Waltari, M., Halonen, K., A Switched-Opamp With Fast
Common Mode Feedback, Proceedings of the 1999 IEEE
International Conference on Electronics, Circuits and Systems,
Sept 1999, Pafos, Cyprus, pp. 1523-1525.
[6] Yan, S., and Sanchez-Sinencioo, S., Low-Voltage Analog
Circuit Design Techniques: a Tutorial, IEICE Trans.
Fundamentals, Vol.E83-A, No.2 February 2000.
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