Download EE 501 Project 1

EE 501, Fall 2009 Project 1
Fully Differential Multi-Stage CMOS Op Amp Design
Objectives:
1. Understand fundamental limits, constraints, trade-offs, and optimization issues in
multistage CMOS op amp design
2. Understand stability, compensation, and common mode feedback.
3. Gain experience in designing and simulating Op Amps and supporting circuits
4. Gain experience in floor planning, matching layout, and taping out for fabrication.
Tasks:
1. Design a fully differential multi stage CMOS Op Amp, including
a. Op Amp architecture selection and justification
b. I_REF generator, biasing circuits, compensation network, CMFB circuit.
c. Large signal constraints to ensure all transistors in their intended operation region
d. Small signal equations showing relationships between biasing/sizing and various
specifications
e. Simulation test bench circuits for schematic simulation of op amp performance
f. Simulation results of amplifier performance at normal and various corners.
g. Floor planning with justifications, overall layout, detailed layout of match-critical
components.
h. Proof of DRC and LVS, and post layout simulation results showing performance
at nominal and various corners.
Architecture constraints:
1. Fully differential structure for which CMFB is necessary
2. At least two stages for which frequency compensation is a necessity.
3. You may have additional pins, but the following 7 are needed:
a. + Vin, – Vin, +Vout, – Vout, VDD, VSS, Vcm.
Process constraints:
1. To facilitate free fabrication through MOSIS, you are to use AMI0.5
2. If you do not plan to fabricate, you may choose to use a different process
3. Supply voltage should be commensurate with process selection
Op Amp Basic Specification Targets:
1.
2.
3.
4.
5.
Power supply variation tolerance: + – 20%.
Total power consumption of chip: <= 2 mA * (Vdd-Vss)
Output driving capability: a capacitive load of 2 pf on each output.
Unity gain frequency: >= 50 MHz.
Maximum percentage overshoot in small size step response:
a. With gain of 1 buffer connection: <= 25%.
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b. With gain of -1 capacitive feedback Cf = Ci = 0.5p: <=15%
c. With gain of -1 resistive feedback Rf =Ri = 100K: <=10%
6. Peak DC gain: >= 90dB
7. Vout swing range: covers [–1.5 V, +1.5 V] at +-2V supply.
a. If in a different process, 75% of Vdd-Vss
8. Input common mode range: >= 50%, should target >=60% of Vdd-Vss.
9. Systematic differential offset voltage: should be zero in schematic simulation, and should
be <=15 mV with process variations.
10. Slew rate: >= 100 V/S, target 200 V/S.
11. Settling time in 0.2 V step response in unity feedback: <= 50 nS for +– 0.1%.
Other Specifications to consider:
1. CMFB loop stability: phase margin >= 55 degrees
2. CMFB loop unity gain bandwidth: around 5 to 10 MHz, or about 5 to 10 times lower than
DM UGF.
3. CMRR: >= 60 dB at DC
4. PSRR: >= 60 dB at DC
5. Input referred noise voltage: in nV/sqrt(Hz), should consider in design and should report
but no specific requirement imposed.
6. Gain linearity: in terms of gain variation over Vout swing range, should simulate and
report, but no specific requirement imposed.
7. AC response linearity in unity gain feedback configuration (inverting and noninverting
may have different linearity), should simulate and report, but no specific requirement
imposed:
a. THD vs frequency and/or vs output signal magnitude
b. SFDR vs frequency and/or vs output signal magnitude
Suggested choices:
1. Two stages, first stage cascode or folded cascode, 2nd stage common source
2. CMFB: as in lab; need to make sure Vocm stability and input CM range of CMFB circuit
are appropriately taken care of.
3. Compensation: pole placement for UGF maximization
4. Biasing circuit: accommodate Vicm variation, as discussed in class
5. Layout: input pair high order common centroid matching pattern
6.
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