Download A voltage reduction technique for battery-operated systems

IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.
1136
25, NO. 5, OCTOBER 1990
A Voltage Reduction Technique
for Battery-Operated Systems
VINCENT VON KAENEL, PETER MACKEN, AND MARC G . R. DEGRWWE, MEMBER,
IEEE
Absfmd -A self-regulatingvoltage reduction circuit is presentedwhich
adjusts the internal supply voltage at the lowest value compatible with
the speed requirements of the chip, taking temperature and technology
parameters into account. Besides enhancing reliability, this new technique also saves power, which is important for battery-operated systems
such as laptop computers and portable instrumentation for radio-communication systems.
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EQUIVALENT
CRITICAL
PATH
SIGNAL
COMPARATOR
4,
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EOUIVALENT
CRITICAL
I. INTRODUC~ON
S
UPPLY voltage reduction of VLSI chips is important
OUT I
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to save power and to avoid undesirable effects, such
as punchthrough and substrate currents, when smallgeometry technologies are used. In order to remain comI Nn
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patible with the external supply voltage standards and the
I
technology requirements, on-chip voltage reduction techFig. 1. Principle of a self-adjusted voltage reducer.
niques can be used.
In the past such techniques have been applied to memories [1]-[4], watches, etc., where the on-chip voltage is
11. PRINCIPLE
OF SELF-ADJUSTED
reduced to a fixed value. Such static systems of reduction
VOLTAGE
REDUCXION
can neither take into account speed requirements nor all
technology parameters.
The power consumption of a digital circuit is given by
In this paper, a new voltage reduction technique based the well-known formula
on functional comparison is presented. With this new
technique, a regulated system adjusts the supply voltage
power = f * c vgD VDDzDC
of a digital circuit at the functional boundary for the
(1)
speed requirements, the temperature, and the technology
parameters.
In the next section, the principle of the self-adjusted where f is the operating frequency, C is the equivalent
technique is discussed. In Section 111 the fixed-voltage capacitance of the circuit, and ZDc is the static current.
technique with temperature compensation is presented. Reducing the supply voltage will decrease power conThe results of measurements are given in Section IV. sumption, however, it will also slow d o m the critical path
Finally, in Section V possible applications are discussed. of the circuit. If the supply voltage is further reduced, the
critical path finally becomes too slow to assure the correct
functioning of the chip. The general voltage reduction
Manuscript received April 18, 1990; revised May 28, 1990. This work technique presented in Fig. 1 is based on this last obserwas supported by the Centre Electronique Horloger S.A.
vation. The following functional blocks need to be added
V. Von Kaenel and M. G. R. Degrauwe are with Recherche et
DCvelop ement Centre Suisse d’Electronique et de Microtechnique to the circuit: two “equivalent critical paths,” a signal
S.A., CL2000 NeuchPtel 7, Switzerland.
comparator, and an integrator.
P. Macken was with Recherche et Dkvelop ement, Centre Suisse
The “equivalent critical path” is a small circuit with
d‘Electronique et de Microtechnique S.A., 8H-2OOO Neuchltel 7,
Switzerland. He is now with the University of Chicago, Chicago, IL electrical properties which are comparable to those of the
60637.
actual critical path of the original circuit..
IEEE Log Number 9037773.
-
0018-9200/90/1000-1136$01.00 01990 IEEE
+
VON KAENEL
et al.: VOLTAGE REDUCTION
1137
FOR BATTERY-OPERATED SYSTEMS
The signal comparator will detect if there is a difference between the signals coming out of the two equivalent critical paths, one of which is biased at the full
voltage supply while the other is biased at a reduced
voltage. Due to the feedback loop the system will adjust
the reduced voltage so that one “equivalent critical path”
is biased at the minimum required value to produce a
correct output signal.
Since the equivalent critical path has the same behavior
as the actual critical path of the original circuit, one can
use the reduced voltage as a supply for the original
circuit. Eventually a small voltage shift can be implemented to obtain a security margin.
In order to reduce the overall power consumption and
to have a reliable circuit, it is mandatory to have a small
circuit which can model the actual critical path in an
accurate way.
It can be shown that, in a first-order approximation, the
ratio of the delay of a critical path to the period of a ring
oscillator is a constant which depends only on the number
of stages, the dimensions of the transistors, and the load
capacitances. That means that a ring oscillator can be
used as an equivalent critical path for all digital circuits.
Since by changing the supply voltage of a ring oscillator
the frequency changes (VCO), one can implement the
system shown in Fig. 1 with a phase-locked loop (PLL)as
shown in Fig. 2. The fixed-frequency divider ( N I is used
to implement the ratio between the delay of the VCO and
that of the actual critical path. The input signal fin, which
affects the reduced voltage value, represents the speed
requirement. The chip’s general clock frequency can be
used as f-,.
By adjusting the VCO supply voltage, the PLL causes
the VCO to oscillate at N.fi,. Supposing that the dimensions of the VCO transistors are such that the critical
path functions correctly at the regulated voltage, the
digital circuit will always function correctly, since changing technology parameters, temperature, or the frequency
fin affects the VCO in the same way as it affects the
circuitry. So it is sufficient to measure or simulate the
delay of the critical path at a certain supply voltage and
calculate the dimensions of the VCO and the division
factor N accordingly. One is then assured that the digital
circuit will always work properly.
111. FIXED-VOLTAGE
REDUCTOR
This technique consists of imposing a fixed reduced
supply voltage to the circuit [5]-[7]. In this case there is
no activation signal, so the work frequency is fixed. Only
static technology parameters can be taken into account by
this technique. There is no feedback from the digital
circuit to the voltage generator, so there is no functional
verification of the circuit. In this way, the reliability is not
guaranteed.
In the simple circuit like that shown in Fig. 3, the
reduced voltage is approximately equal to the maximum
Regulated
fin-Phase
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A
Charge
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LOOP
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voltage
filter
DIGITAL
SYSTEM
U
U
Fig. 2. Implementation of the supply voltage reducer by a PLL.
Vdd
0
0
Vred
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1 7 -
3--c----,
vss
Fig. 3. Generator of fiied reduced voltage.
of both threshold voltages. The main advantages of this
approach are the small surface and the low consumption
of this circuit. As shown hereunder, some security margins must be employed to ensure that the digital circuit
still works in the worst case of technology parameters and
temperature.
The reduced voltage takes into account technology parameters such as the VT’s and p’s, however, capacitor
variation must be considered separately. It is interesting
to note that the oxide thickness To, does not influence
the speed of a digital circuit in first approximation when
the gate capacitors are the dominant load capacitance.
For temperature effect, the current reference versus
temperature can be modeled as follows:
where a is the temperature coefficient of the reference,
Trefis some reference temperature, T is the temperature
value, and Zpo is the current reference at Tref.
The p’s are modeled as follows:
where a is the temperature coefficient of the mobility
(a= 1.5) and Po is the beta at Trer.
It is assumed that the VT’svary linearly with a temperature coefficient of -2 mV/”C. These laws applied to the
circuit shown in Fig. 3, and to a digital circuit they give an
important characteristic of the fixed reductor circuit,
namely the slope of Ked versus temperature as a function
of I/red (Fig. 4). By adjusting the ratio of well resistance to
polysilicon resistance used for R in the current reference
(Fig. 9, it is possible to obtain a similar temperature
coefficient for reduced voltage and the digital circuit.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
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25, NO. 5, OCTOBER 1990
Vdd
b
-6
1
00
I
-
7
Ilo
0 5
15
Fig. 4. Slope of
-
7 -
20
-
vrCd [ V J
7
-
2 5
30
Ked as function of Ked.
5,
Vdd
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,2
t IP
IN
1
Path 3
(b)
I
0
++++D.D.D.D.D.D.D.D.D.D-
vss
-
3
Path 4
Fig. 5. Current reference.
Since variations of resistor values affect the current and
thus also the value of the reduced voltage, this technique
demands the use of large security margins during the
design.
Because of the low consumption and small area used
for the fixed-voltage reduction, this technique is suitable
for small digital circuits with low power consumption.
IV. MEASUREMENTS
In order to show the validity of the proposed selfadjusted principle, the system in Fig. 2 has been integrated in a 2-pm n-well CMOS process. To model the
critical path, four test circuits have been implemented:
1) a short series of inverters with the same dimensions
as those of the VCO, but charged with an extra gate
capacitance at the inverter output (Fig. 6(a));
2) a long series of these inverters, to see the effect of a
long path (Fig. 6(a));
3) a series of inverters with four NMOS and four
PMOS transistors in series, to test the influence of
putting transistors in series (Fig. 6(b)); and
4) a frequency divider, which is a small digital circuit
(Fig. 6(c)).
Furthermore, in order to be able to show the influence
of technology variation, a “split lot” integration was done
(C)
Fig. 6. (a) Schematic of critical paths 1 and 2. (b) Schematic of critical
path 3. (c) Schematic of critical path 4.
which changed the oxide thickness over 10% and the sum
of the threshold voltages of the n- and p-transistor MOS
from 1.07 to 1.60 V.
As shown in Fig. 7(a) and (b), the ratio of delay of the
critical path integrated -to the period of the VCO depends
weakly on the supply voltage (Ked)and the temperature.
This confirms that a VCO can be used as an equivalent
critical path. The variations are caused by foreseeable
changes in the gate capacitance near the threshold voltage. If one wants the digital circuit to operate correctly in
a range of frequencies (f.,), the operating points should
be chosen where the critical path is the slowest relative to
the VCO. As a consequence, the regulated voltage will be
too high for all other frequencies.
Fig. 8 shows the ratio of the regulated supply voltage to
the minimum supply voltage, for frequencies of fin ranging from 400 Hz to 4 MHz. For the four cases of critical
paths integrated, the regulated voltage is at worst 10%
too high, which means that the circuit will always work
near the point of lowest power consumption.
Technology parameters are accurately tracked, as shown
in Fig. 9, which represents the regulated voltage (Ked)for
two different wafers. The ratio of the delay of a critical
,
VON KAENEL
t
et al.: VOLTAGE REDUCTION FOR BATTERY-OPERATED
2UOolaylPsriod o f
1139
SYSTEMS
VCO
1.11
1.011
path 2
/
'"(-1
/ \\
p a t h- 1
path 4
path 2
path 4
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.11
2.0
[VI
I . O d p a t h 30.2
a:+
/OIB
oh
112
L'O
I.'+
1.i
1
Fig. 8. Ratio of regulated voltage to the minimum voltage necessary to
fulfill speed requirements.
Vred
0.1
. 7.
(b)
(a) Ratio of delay of a critical path to the period of the VCO.
$b) Ratio of delay of a critical path to the period of the VCO, for
three different temperatures.
Fi
path to the period of the VCO varies less than 20% while
the sum of the threshold voltage changes 250 mV.
Power consumption for the whole system is only a few
microamperes. Tests have shown that it can be reduced to
the nanoampere level by operating the voltage regulation
system intermittently. Indeed, for a stable fin signal, the
rate of variation of the reduced voltage is very slow
because of the slow variation of the temperature and
technology parameters. The system can operate intermittently by opening the regulation loop for a given time and
closing it only in order to compensate for the leakage
currents that empty the loop
capacitance (Fig' 'O).
OTHERAPPLICATIONS
V. POSSIBLE
In battery-operating systems it is important to detect
when the battery should be changed in order to avoid
reliability problems.
0.6
Oh
If0
I.'Z
114
I.'6
I
1.1
8
-
2.O[V]
Fig. 9. Reference frequency as function of regulated voltage
two different wafers.
ccd,
for
A common way to detect the end of life (EOL) of a
battery is to compare the battery voltage to a fixed boundary value. This fixed value of comparison must be calculated in the worst case of technology and temperature.
However, the actual speed requirements, temperature,
and technology parameters of the circuit are not taken
into account in the detection. That means a fixed value
cannot be the optimum value for all cases of technology
and temperature because the security margin alters the
EOL detection.
The best way to detect the EOL of the battery is to use
a threshold value that depends on the minimum supply
voltage of the digital circuit. When using the proposed
voltage reduction technique, the EOL detection is very
simple and reliable. It suffices to compare the battery
voltage to the reduced voltage supply with a small margin
for detection just before the limit as shown in Fig. 11. In
this way, the EOL detection is dependent on the technology parameters and the temperature. This allows the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.
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fin-Phase
dectector
Charge
pump
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REFERENCES
Regulated
voltage
LOOP
filter
D IGlTAL
SYSTEM
I
Acttvation
f
I
I
I
I
I
1
Toff
’
I
I
I
Ton
I
I
I
c
I Ton
time
‘
1
:
Toff
I
Fig. 10. Supply voltage reducer for intermittent operation.
I”“““’“
I
H. Fukuda et al., “A BICMOS channelless masterslice with on-chip
voltage convertor,” in ISSCC Dig. Tech. Papers, Feb. 1989, pp.
176- 177.
T. Furuyama et al., “A new on-chip voltage convertor for submicron high density DRAM’S,” in Proc. ESSCIRC, Sept. 1989, pp.
10-12.
K. Itoh et al., “ A n experimental 1Mb DRAM with on-chip voltage
limiter,” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 282-283.
T. Mano et al., “Circuit techniques for a VLSI memory,” ZEEE .I.
Solid-state Circuits, vol. SC-18, pp. 463-470, Oct. 1983.
E. Vittoz, “The design of high-performance analog circuit on digital
CMOS chips,” IEEE J . Solid-State Circuits, vol. SC-20, no. 3, pp.
522-528, June 1985.
M. Degrauwe et al., “Adaptive biasing CMOS amplifier,” IEEE J .
Solid-state Circuits, vol. SC-17, no. 3, pp. 657-665, June 1982.
E. Vittoz, M. G. R. Degrauwe, and S. Bitz, High-performance
crystal oscillator circuits: Theory and application,” IEEE J . SofidState Circuits, vol. 23, no. 3, pp. 774-783, June 1988.
S. Chou et al., “Chip voltage: Why less is better,” IEEE Specbum,
vol. 24, no. 4, Apr. 1987.
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25, NO. 5, OCTOBER 1990
EOL
time
detection
Fig. 11. EOL detection for battery-operated systems.
Vincent Von Kaenel was born in NeuchPtel, Switzerland, on March 5,
1964. He received the engineering degree in electronics from the Ecole
d‘hgtnieur d’yverdon, Yverdon, Switzerland, in 1989.
He was employed as a technical collaborator and worked in the
development of software for the design automation of building blocks
from 1985 to 1987. He is now involved at the Centre Suisse d’Electronique et de Microtechnique S.A., Neuchltel, Switzerland, in the development of systems working at minimum power consumption.
Peter Macken was born in Sint Niklaas, Belgium, on November 22, 1962.
He received the engineering degree in electronics from the Katholieke
Universiteit Leuven’ (KUL), Leuven, Belgium, in 1986. He is currently
working towards the Master of Business Administration degree at the
University of Chicago, Chicago, IL.
He executed a training period from October 1986 to March 1987 at
the Centre Suisse d’Electronique et de Microtechnique S.A. (CSEM),
NeuchPtel, Switzerland. He developed SRAM cells for watch applications. After completion of military service he came back to CSEM,
where he was involved in the development of electronic systems working
at minimum power consumption.
complete use of the battery with respect to the actual
needs of the digital circuit.
VI. CONCLUSION
In this paper, two techniques of voltage reduction have
been presented. Both techniques can significantly reduce
the power consumption of digital CMOS circuits.
The fixed reduction of voltage is usable for small systems with a low initial consumption. In this case, the
optimum voltage is not reached and the correct operation
of the circuit is not guaranteed.
The self-adjusted reduction of voltage is adapted to
bigger digital systems. The correct operation of the digital
circuit is guaranteed. The supply voltage is near the
optimum for the speed requirements. This new technique
is more versatile, more accurate, and more reliable than
the fixed one.
Marc G . R. Degrauwe (S’78-MJ84) was born in
Brussels, Belgium, on August 16, 1957. He received the engineering degree in electronics and
the Ph.D. degree in applied sciences from the
Katholieke Universiteit Leuven (KUL), Leuven,
Belgium, in 1980 and 1983, respectively.
During the summer of 1980 he was on leave
at the Centre Electronique Horloger S.A.
(CEH), NeuchPtel, Switzerland. From autumn
1980 to 1983 he was associated with KUL where
he worked on the design of micropower amplifiers and sampled date filters. In July 1983 he returned to CEH. In 1984
when CEH was reorganized into the Swiss Centre of Electronics and
Microtechnics (CSEM), he became Head of the Circuits Department.
Now he is Head of the Design Automation Division. His actual field of
interest is design automation of analog circuits. He is also lecturing on
analog circuit design and supervising student work at the University of
NeuchPtel.
Dr. Degrauwe received the 1987 ESSCIRC Conference Best Paper
Award for a paper on crystal oscillators he co-authored.