Download Challenges of Electrical Measurements of Advanced Gate

2003 International Conference on Characterization and
Metrology for ULSI Technology
CHALLENGES OF ELECTRICAL
MEASUREMENTS OF ADVANCED
GATE DIELECTRICS IN METALOXIDE-SEMICONDUCTOR DEVICES
Eric M. Vogel¶ and George A. Brown*
¶National
Institute of Standards and Technology, Semiconductor Electronics Division
*International SEMATECH
March 27, 2003
Material in this presentation is Non-Confidential
Overview
• Introduction
• C-V Measurement Challenges
• EOT Extraction Challenges
• Interface State Density Measurements
• Extrinsic Defect Density
• Reliability Evaluation Challenges
• Summary
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Introduction
• Lots of effects and unknowns, only four terminals!
(two on capacitors!)
• We will need many well-chosen measurements to
extract our required parameters.
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C-V Measurement Challenges
A Primer of Capacitive Impedance Measurements
• Capacitance measurements with an LCR meter provide
two output parameters, an energy-storage component
(L or C) and an energy loss component (R or G).
• These are expressed in terms of either a series or
parallel equivalent circuit.
Series Circuit • They are truly equivalent:
Rs
Cs
Parallel Circuit
Cs = Cp * (1 + D2)
D = ωRsCs = 1/ωRpCp = 1/Q
Rp
Cp
• D is called the Dissipation Factor
• Q is called the Quality Factor
• They express the magnitude and phase of
the sample’s response to the applied signal.
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C-V Measurement Challenges
ωt =
δ
Applied voltage
Θ
applied voltage
pure capacitor response
lossy capacitor response
pure conductance response
1
0.8
Cp
δ
0.6
Θ
0.4
Time Æ
0.2
0
t=0
Gp
-0.2 0
1
2
3
4
5
6
-0.4
-0.6
-0.8
-1
Gp
Cp Y = Gp + jωCp
D = Dissipation Factor = tan δ
• Ideal resistors have a response exactly in phase with the applied
voltage (like the green curve).
• Ideal capacitors have a response completely out of phase with the
applied voltage (like the pink curve).
• Lossy capacitors, like ultra-thin oxides or some high-k dielectrics,
are somewhere in between (like the blue curve).
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C-V Measurement Challenges
Measurement Conditions and Errors
• Applied ac voltages should be close to the thermal
voltage (25 mV at room temperature) to maintain the
small-signal approximation.
• Open and short-circuit (and perhaps calibrated load)
zeroing must comprehend test fixture and cabling.
Probe station resonance effects may become
important at higher frequencies.
• Light and ambient shielding will be important for
some measurements.
• Even with great care taken, errors are an inherent
part of all measurements.
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C-V Measurement Challenges
Measurement Conditions and Errors
• A calculation of relative measurement accuracy of the widely used
Agilent 4284A LCR meter has been done. It depends upon the
measurement frequency and the nominal capacitance and conductance
of the sample under test.
• The relative capacitance
measurement accuracy
of an LCR meter decreases
with:
→ decreasing frequency
→ increasing conductance
→ decreasing capacitance
• For some conditions, errors
can truly dominate the
measurement!
Capacitance Error (+/- %)
105
-11
-3
C = 10 F, G = 10 S
-6
-11
C = 10 F, G = 10 S
-10
-6
C = 10 F, G = 10 S
104
103
102
101
100
10-1
10-2
102
103
104
105
106
Frequency (Hz)
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Relationship of LCR Meter Output
to Sample Parameters
• In general, we can’t count on
LCR meter output parameters to
relate directly to our sample
parameters.
• Only in the simplified case
shown here of a high-qualityfactor, low leakage insulator on a
resistive substrate can we hope
to identify Cs with Coxide, Rs with
Rsubstrate in a series-mode
measurement.
gate
Cs
substrate
oxide
Rs
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Evolution of Sample
Equivalent Circuits
• For some samples, capacitive and
resistive impedances of the insulator
may be comparable, but still greater than
the series resistance of the substrate or
connections. Here, the parallel
equivalent circuit output mode will
provide a valid description of the
sample.
• Eventually, however, all three may
become of comparable size, and none
can be ignored. We then need a 3element equivalent circuit.
Gp
Cp
Ci
Ri
Rs
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Shortcomings of a Two-Element
Equivalent Circuit
• Use of the threeelement model will
sometimes yield a valid
model of the structure.
Specific Capacitance [F/cm2]
• Capacitance roll-over
is a common
consequence of using
the two-element Cp
meter output to
represent a conductive
dielectric on a resistive
substrate.
3.5E-06
f = 100 kHz
3.0E-06
A=5.0E-5 cm^2 inv=>acc
A=5.0E-5 cm^2 acc=>inv
A = 1.0E-4 cm^2
2.5E-06
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
-2.5
Go
-2
-1.5
Co
-1
Cp
-0.5
Voltage [V]
~
~
0
0.5
1
Gs2
(Gs + Go)2
1.5
* Co
Gs
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Shortcomings of a Three-Element
Equivalent Circuit
2.0E-11
Area = 4.0x10-6 cm2
f = 100 kHz
Go
Co
Rs
Ls
Capacitance [F]
1.0E-11
0.0E+00
-1.0E-11
-2.0E-11
-3.0E-11
-4.0E-11
-2.5
-2
-1.5
-1
-0.5
Voltage [V]
0
0.5
1
• A series inductance in addition to the three-element circuit is
necessary to model negative capacitance or capacitance rising
above Co.
• The source of the inductance is not clear; it could be a
measurement effect or physical phenomenon.
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A Distributed Transistor
Channel Equivalent Circuit
• This near-ultimate transmission line equivalent
circuit was developed by Ahmed, et al.[1] It was used
to show that channel lengths less than about 10 µm
are needed to assure proper response of devices with
2 nm gate oxides.
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Modeling the C-V Measurements
with an Equivalent Circuit
• Since a single capacitance measurement yields only
two parameters, the real and imaginary parts of the
impedance, we will need multiple measurements to
solve for the 3, 4, or more elements in our equivalent
circuits. Several approaches have been suggested:
• An iterative technique to isolate and evaluate series
components [2]
• Use of two measurement frequencies to give four parameters
• For the three-element equivalent circuit [3]
• for the four-element circuit [4]
• Evaluation of transmission line parameters for the distributed
equivalent circuit [1]
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Determination of EOT and CET
• Once an accurate capacitance value representing the
dielectric is obtained from the modeling above, values
of EOT and CET may be determined.
• Definitions:
• EOT (Equivalent Oxide Thickness): The thickness of
an SiO2 film having the same specific capacitance as
the dielectric film in question, without any effects
from quantum confinement or polysilicon depletion
in its electrodes.
• CET (Capacitance Equivalent Thickness): This
thickness determined by computing εSiO2*Area/Cmeas
where Cmeas is the measured capacitance in inversion
or accumulation at some defined voltage.
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Significance of EOT, CET
EOT:
Because of its independence of device
structural effects, this is basically a materials
parameter. It is normally evaluated with the device
biased in accumulation, where errors involved in its
calculation are expected to be minimized.
CET:
The simplicity of its calculation suggests that
all device-related shortcomings are included in this
parameter. It does, however, govern device operating
parameters such as drive current. Thus it is usually
evaluated in inversion, the operating mode of the
device, yielding the parameter CET(inv).
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EOT Determination: A Choice
of Simulators
1.50
1.25
1.00
2
C (µF/cm )
• Simulators show a difference
of up to 20% in the calculated
accumulation capacitance.
• This will lead to significant
differences in EOT from the same
C-V data.
• Possible reasons include
the use of approximations for
quantum effects vs. Schrödinger
equation, wave function
boundary conditions, and
type of carrier statistics.
• It is wise to choose one
simulator, and always specify it
when quoting values.
0.75
0.50
UTQuant [30]
NIST
Schred [32]
NCSU [25]
NEMO [29]
Berkeley [31]
Tox = 2.0 nm
18
Nsub = 10 cm
-3
0.25 Npoly = 1020 cm-3
n-channel, n-poly gate
0.00
-3
-2
-1
0
1
2
3
Vg (V)
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Interface State Density, Dit
Measurement of interface state density has been one of
the greatest challenges in advanced dielectric
characterization. This has been because most
standard techniques have significant shortcomings
for these structures. The standard techniques are
1. Terman technique: based on high-frequency C-V stretch-out.
Low sensitivity for thin films, high frequency assumption
often not met.
2. High-low frequency C-V: Quasi-static (low frequency) C-V
not usually measurable because of high dielectric leakage.
3. AC conductance-frequency: Very sensitive but complicated
technique; also leakage-sensitive.
4. Charge pumping: Requires transistor structures, also
leakage sensitive, but corrections are possible.
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Charge Pumping Measurement
0.1 V
Vgbl
Va
tr
tf
• Base-level charge pumping measurement:
- fixed amplitude Va, base voltage stepped in 0.1V increments
- rise and fall times tr and tf = 100 ns
- traps fill from S/D during tr, empty into substrate during tf
• Charge pumping current is given by
I cp = fqAG Dit ∆E
f= freq, AG= channel area, Dit= average Dit over ∆E (Ef,inv –Ef,acc)
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Leakage Correction: Key to
D
Measurement
it
2 nm SiO gate
2
6.E-10
•
1MHz
5.E-10
– “Looks” like DC relative to
1 MHz, 500 kHz, or 100
kHz data
100kHz
Icp
Icp [A]
4.E-10
Measure Icp at 1 kHz
1kHz
3.E-10
2.E-10
1.E-10
0.E+00
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
Vgbl [V]
2.0E-10
1.5E-10
1MHz-1kHz
1.0E-10
•
100kHz-1kHz
5.0E-11
0.0E+00
-1.8
-1.6
-1.4
-1.2
Vgbl [V]
-1
-0.8
-0.6
3.0E+10
2.5E+10
Dit [cm -2 eV -1 ]
Subtract 1 kHz Icp data from
high frequency Icp data
– Effectively removes DC
leakage current
2.5E-10
-2
Dit
•
3.0E-10
Icp [A]
Corrected Icp
-2
Use small transistors to
reduce leakage current
relative to the charge
pumping current
– Example: W/L = 10/1 µm
2.0E+10
1.5E+10
Note frequency independence of
Dit in the 100 kHz-1MHz range.
Dit 1MHz - 1kHz
1.0E+10
Dit 100 kHz - 1 kHz
5.0E+09
0.0E+00
-2
-1.8
-1.6
-1.4
-1.2
Vgbl [V]
-1
-0.8
-0.6
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Charge Pumping in High-k Devices
Fixed Amplitude-Variable Base Measurement
nFET W/L=10/1µm
10
2
Nit [10 /cycle*cm ]
TH75-2072317 #08
2.4
2.2 V = 1.2V
peak
2.0
10 kHz
1.8
1.6
100 kHz
1.4
1.2
1.0
0.8
1 MHz
0.6
0.4
0.2
0.0
-1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
• Frequency dependence
of interface state density
is a characteristic of many
high-k gate stacks.
• It may be interpreted in
terms of depth-related
time constant variation [5],
associated with bulk of
interfacial traps.
0.2
Vbase [V]
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Extrinsic Defect Density
in High-k Films
• Extrinsic defect distributions have been driven to
relatively low levels in conventional SiO2 gate dielectrics.
•High-k films, because of their structure and deposition
conditions, may not have the same low defect densities
we have become accustomed to in conventional devices.
• In thicker SiO2 films, extrinsic defects are sensed by low
oxide breakdown voltage, or early failure on constantcurrent/voltage stress tests. Such failures are often not
easily sensed in high-k films, particularly in large-area
devices needed for low defect density resolution.
• It has been observed that defects in high-k films often
result in a higher level of conductivity over their entire I-V
characteristic.
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Typical Full-Wafer CurrentVoltage Map
Lot/Wafer 1081503-03
2
Area = 5E-3 cm , 52 units
1
71% YIELD
0.1
0.01
0.001
CURRENT [-A]
0.0001
1E-05
1E-06
1E-07
Yield Criterion: Ig(-2V) < -2.0E-6 A
1E-08
1E-09
1E-10
1E-11
1E-12
0
0.5
1
1.5
2
2.5
3
3.5
4
VOLTAGE [-V]
• Yield criterion easily identified for a given wafer
DIE 3,1
DIE 4,1
DIE 5,1
DIE 6,1
DIE 7,2
DIE 6,2
DIE 5,2
DIE 4,2
DIE 3,2
DIE 2,2
DIE 1,3
DIE 2,3
DIE 3,3
DIE 4,3
DIE 5,3
DIE 6,3
DIE 7,3
DIE 8,3
DIE 8,4
DIE 7,4
DIE 6,4
DIE 5,4
DIE 4,4
DIE 3,4
DIE 2,4
DIE 1,4
DIE 1,5
DIE 2,5
DIE 3,5
DIE 4,5
DIE 5,5
DIE 6,5
DIE 7,5
DIE 8,5
DIE 8,6
DIE 7,6
DIE 6,6
DIE 5,6
DIE 4,6
DIE 3,6
DIE 2,6
DIE 1,6
DIE 2,7
DIE 3,7
DIE 4,7
DIE 5,7
DIE 6,7
DIE 7,7
DIE 6,8
DIE 5,8
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Extrinsic Defect Density
Determination
Defect Density Determination: Lot-wafer 1081503-03
2
Defect Density = 60 /cm
1
Wafer data
Poisson Model
0.9
Yield Fraction
0.8
0.7
Poisson Model:
0.6
Yield = exp -(Area * Defect Density)
• Assuming a
good fit, defect
density equals
the inverse of
the sample area
for which the
yield is 37%.
0.5
Measured Parameter: Gate Current at Vg=-2V
52 units/sample area
0.4
0.3
0.2
D0 = 1/A(0.37)
0.1
0
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
2
Sample Area [cm ]
• Preliminary measurements show defect densities ranging from about
1 /cm2 up to as high as 2.7x104 /cm2 or higher. No clear process
dependence has yet been established.
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Reliability: Defect Distribution
in High-k Dielectrics
∆Dit/Dit,0
10-1
100
ZrO2
Vg,stress = 2.75 V
10-2
3
CP, F = 10 Hz
4
CP, F = 10 Hz
5
CP, F = 10 Hz
6
CP, F = 10 Hz
10-3
10-4
10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103
Time (s)
∆Dit/Dit,0
100
2.0 nm SiO2
Vg,stress = 4.3 V
10-1
4
10-2
CP, F = 10 Hz
CP, F = 105 Hz
CP, F = 106 Hz
10-3
10-6 10-5 10-4 10-3 10-2 10-1 100 101 102
Time (s)
• Interface state density generation under constant voltage stress is
compared for ZrO2 and SiO2 FET’s, using charge pumping.
• Higher generation rates are observed in the bulk of the ZrO2 film
than at its surface; SiO2 shows no frequency (or depth) dependence.
• Device parameter drift (e.g. Dit) may be a greater reliability problem
in high-k films than dielectric breakdown.
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Summary
• The low, complex impedance of advanced gate
dielectrics forces us to be thorough in our
understanding, measurement, and analysis of MIS C-V
characteristics.
• Multi-element equivalent circuits are required to
describe these structures adequately, and parameter
extraction requires sophisticated modeling.
• Many of our conventional measurement techniques
are not applicable to these structures, or detailed
correction procedures must be invoked.
• The different material properties of high-k dielectrics
compared to SiO2 suggest that we may find new
primary reliability issues, requiring development of
new characterization techniques.
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Acknowledgement
The authors would like to thank NIST and
International SEMATECH for financial
support, and C. Richter, J. Suehle, D. Heh, C.
Weintraub, P. Hung, C. Young, and J. Han for
valuable discussions.
Certain commercial equipment, instruments, or materials are identified in this paper in order to specify
the experimental procedure adequately. Such identification is not intended to imply recommendation or
endorsement by the National Institute of Standards and Technology or SEMATECH Inc. d/b/a
International SEMATECH, nor is it intended to imply that the materials or equipment identified are
necessarily the best available for the purpose.
SEMATECH, the SEMATECH logo, International SEMATECH, and the International SEMATECH logo are
registered service marks of SEMATECH, Inc.
4/3/2003 11:40 AM j:\stndpres\template\ISMT.ppt - 26
References
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Wortman, and J. R. Hauser, IEEE Trans. Elec. Dev 46, 1650-1655 (1999).
2. E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, IEEE
Trans. Elec. Dev. 47, 601-608 (2000).
3. K. J. Yang, and C. M. Hu, IEEE Trans. Elec. Dev 46, 1500-1501
(1999).
4. H.-T. Lue, C. Y. Liu, and T. Y. Tseng, IEEE Elec. Dev. Letts. 23, 553555 (2002).
5. C. Weintraub, E. Vogel, J. R. Hauser, N. Yang, V. Misra, J. J.
Wortman, J. Ganem, and P. Masson, IEEE Trans. Elec. Dev. 48, 27542762 (2001).
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