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CSE 120 SALESH ASWANI ID: - 993-70-9953 PROFESSOR: - MR. MATAR CLASS: - MWF 8:40 HARDWARE LAB # 2: - THREE-STATE BUFFERS, OPEN-COLLECTOR BUFFERS. INTRODUCTION In Hardware Lab 2, we will look further at debugging techniques and we will investigate the three-state and common-collector buffers. In this lab, we will use another debugging tool, the voltmeter. (Refer to the Hardware Lab 0: Using a Prototype Board, Logic Probe & Voltmeter for a description of how to use a voltmeter.) In TTL chips, as in most types of digital logic, information is passed in terms of voltage. A value of +5 V. is used to represent a digital 1 (logical true) condition and a digital 0 (logical false) is represented by 0 V. (or ground.) Because of design and manufacturing issues, it is impossible to guarantee that the output voltages of an IC or input voltages feeding an IC will be precisely these values; hence a designer designs IC’s so that a certain range of input values will be interpreted as a digital 1 (or 0) and a certain range of output values will be produced by inputs within this range. It is important in the design that the guaranteed output values are a subset of the allowable input values; that way, slight inaccuracies in the output values will still produce an input value that falls within the acceptable range. To be more precise, let's define the following variables: •VOLmax is the maximum output voltage value that a circuit with a low logic-level will produce. •VILmax is the maximum input voltage value that a circuit will interpret as a low-logic level. •VOHmin is the minimum output voltage value that a circuit with a high-logic level will produce. •VIHmin is the minimum input voltage value that a circuit will interpret as a high-logic level. The relationship between these quantities is shown in Figure 2-1. Notice that VOLmax<VILmax and VOHmin >VIHmin. Convince yourself that if the outputs of digital logic gates are to feed inputs of other gates and if the outputs of these gates are to feed other inputs, and so on, that this relationship must be the case. The strict inequality relationship (e.g. strictly ‘greater than’, rather that ‘greater than or equal to’) is necessary to provide a margin of safety so that even with the vagaries of the manufacturing process and the addition of electrical-noise voltage to signals (caused by stray electrical radiation), the digital logic circuits will work reliably. The experiments in this lab manual are designed to be performed using TTL logic; however, many educational laboratories rely on donations from semiconductor manufactures to stock their IC bins; hence you may be completing some of these experiments with IC's made with other technologies, specifically CMOS (ComplementaryMetal-Oxide Semiconductor) IC’s. With CMOS IC’s the same voltage relationships hold, but the ranges are different as shown in Figures below: In the following tasks, we will intentionally be connecting IC's in unusual, and sometimes undesirable, ways. The objective of this perverse approach is to allow you to measure the voltage values produced by TTL circuits when they are used with questionable wiring practices. Some practices that we have regarded heretofore as heresy will give surprisingly acceptable, even if unreliable, results. Some wiring practices will yield voltage measurements that violate the VOLmax, VILmax, VOHmin, or VIHmin criteria. Once you learn to associate the wiring practices with the violations that they cause, you will be able to make the intuitive leap and associate the voltage violations you measure in the lab with the questionable wiring practices that cause them. Although this reverse association is not always correct (causally related), it may identify one possible cause of the voltage violation problems you encounter in the lab and provides at least a starting point for identifying your problem. Equipment: - Digital Trainer Board, Voltmeter, Logic Probe Circuit Components: - You will need the following circuits to complete the tasks in this lab: •(2) 7404 (Hex Inverters) •(1) 7405 (Hex Open-Collector Inverter Buffers) •(1) 74LS126(Three-State Buffers) (Not 74HC126) •(1) 1000 Ohm Resistor. •(1) 100 Ohm Resistor (Task 2-7 and Task 2-8 only.) •(1) 5.6 V. Zener Diode (Task 2-7 and Task 2-8 only.) Objective: - In this laboratory exercise, you will learn to identify the electrical and thermal effects of questionable wiring practices. You will also learn how to electrically connect three-state and open-collector buffer circuits to drive a common communication bus. Outcomes: - When you have completed this laboratory exercise you will be able to: •Make and interpret electrical voltage measurements. •Detect and recognize the thermal and electrical effects of driving a common point with two conflicting output signals. •Describe the different ways in which three-state and open-collector buffer circuits must be controlled to drive a common bus. •Electrically connect three-state and open-collector buffer circuits to drive a common communication bus. Task 2-1: Effect of Missing Inputs to TTL Gates In this task we have to Insert a TTL 7404 IC (quad inverters) into the breadboard and connect its V CC and GND pins. Connect the input of one of the NOT gates to a data switch. We have to record the input and output voltages of the NOT gate for inputs of digital 0 and 1. Next disconnect the switch from the NOT gate. Now that there is no input to the NOT gate, record the voltages at the input and output of the NOT gate. Table that shows the reading on Volmeter when inputs are connected. Inputs 0 1 Input Volt. +00.000 +05.026 Output Volt. +03.764 +00.111 Table that shows the reading on the Volmeter when inputs are NOT connected. Input Volt. +01.501 Output Volt. +00.106 WHAT I LEARNED In this task I learned how to use a volmeter and read the readings from it. I also learned that when inputs are not connected to the IC the volmeter gives voltage which is not normal. Task 2-2: Observe How Hot the Chips Get In this task we had to connect the chip in a wrong way and then observe it that how hot it gets. Well I removed the input of a switch from the 7404 IC, that made the IC hot which told me that there is something wrong in my connections. This was basically a very simple task. Task 2-3: Gates with Common Outputs In this task we had to connect the circuit using second 7404 IC on the same breadboard. The figure of the circuit built is shown below: The above built circuit will allow us to see what happens when two outputs are connected together. For all four possible input combinations, I have recorded the output voltage and the results given by the binary probe in the table, which is shown below:A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 Voltage +03.837 +01.597 +01.524 +00.110 WORK PREFORMED And THINGS LEARNT In this task I built a circuit with a 7404 IC using two NOT gates and connected the outputs of these gates together. Then I recorded the output voltage, which is presented in the table above. The inputs that made the voltage appear normal were 00 and 11. The inputs that gave abnormal readings were 01 and 10. Therefore I concluded that when ever I get the voltage reading above 0.4 volts and below 2.4 volts means that the outputs of the two gates are connected together. I learnt that an error in a circuit is easy to detect by using Volmeter than logic probe. Task 2-4: Missing Ground and Vcc Connections In this task we will measure the effect on the output signals of removing the ground and V CC connections, one at a time. WORK PREFORMED AND THINGS LEARNT In this task I set up the circuit shown in the Figure below using two NOT gates on the same IC. I Wired the IC so that the V CC pin is connected to +5 V. but left the GND pin unconnected. Since we need a ground return path for the power supply to supply electrical power to the IC, the IC will get no power from the power supply; hence it seems reasonable to expect that the IC will not function properly. This is proved by the table which shows the reading from the Volmeter and also the logic level at Y for all four input combinations using the logic probe. The table that shows the Volt. and Logic Level when GND pin is unconnected. A 0 0 1 1 B 0 1 0 1 Y 1 1 0 1 Voltage +03.746 +03.711 +00.761 +03.772 Then I reconnected GND, and disconnect V CC from the 7404 and repeated the measurements of Y using a voltmeter and logic probe for all four input combinations of A and B. The results of this surprised me a little. The table that shows the volt and logic level when Vcc is disconnected is shown below: This the table that shows the Logic Level and Voltage when Vcc is unconnected. A 0 0 1 1 B 0 1 0 1 Y 0 0 0 0 Voltage +00.000 +00.000 +00.000 +00.000 In this task I learnt that the problem of unconnected V cc and GND can be detected with both Logic Probe and Volmeter. Task 2-5: Build and Test a Common-Collector Buffer Circuit In this task I had to build the using the 7405 common-collector buffer. The figure of the circuit I built in this circuit is given below: WORKED PREFORMED And THINGS LEARNT I built up a circuit using a 7405 IC which is a open collector IC. The circuit made was same as the figure shown above. The data recorded from the circuit is shown in the table below. A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0 In this task I realized that the chip dose not get heated up because there is no conflict between the outputs of the two gates. Since there is no conflict between the outputs of the two gates we get the right results which are presented by Y in the above shown table. This kind of wired circuit presents a NAND gate. Task 2-6: Build and Test a Three-State Buffer Circuit In this task I had to build a Three-State buffer circuit. The figure of the circuit is shown below: The three-state buffer has three output states, as its name implies. When the enable input of the three-state buffer, EN, is active, the output is the same as the input. If EN is inactive, the device enters its third state, a high impedance state. In this state, the voltage measured at the output is not related to the input value A. In the high-impedance state, the output voltage is controlled by the downstream devices not by the buffer’s input signal. This means that three-state buffers can have their outputs connected together provided all but one are in the high-impedance state. Using this control scheme, only the active buffer controls the value measured at the output; however, if the outputs do not ‘take turns’ properly, (i.e., if more than one of the three-state buffers is active) the potential exists for a data conflict. Therefore, it is necessary when connecting together the outputs of several three-state devices to be sure that, at most, one of the outputs is active. WORK PERFORMED And THINGS LEARNT First I took down voltage measurements for all input combinations then measured the logic levels for all input combinations using a logic probe set to TTL. The table of the results that I got by using Logic Probe and Volmeter is shown below: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 EN 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 EN 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 Voltage +00.000 +00.115 +00.000 +03.596 +00.126 +00.120 +00.126 +01.246 +00.000 +00.113 +00.000 +03.603 +03.603 +01.387 +03.627 +03.633 When the enable, EN, of one of the buffers is 0, changing A dose not change the output. When the enables of both the gates are 0, the output we get is 0. When both EN values are 1, the output we get for all combinations of A and B is 0. -------------------------------------------------------------X--------------------------------------------------------------------