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Transcript
Introduction to CMOS VLSI Design Circuit Pitfalls Outline Circuit Pitfalls – Detective puzzle – Given circuit and symptom, diagnose cause and recommend solution – All these pitfalls have caused failures in real chips Noise Budgets Reliability Circuit Pitfalls CMOS VLSI Design Slide 2 Bad Circuit 1 Circuit – 2:1 multiplexer S D0 D1 X S Y Symptom – Mux works when selected D is 0 but not 1. – Or fails at low VDD. – Or fails in SFSF corner. Principle: Solution: Circuit Pitfalls CMOS VLSI Design Slide 3 Bad Circuit 1 Circuit – 2:1 multiplexer S D0 D1 X S Y Symptom – Mux works when selected D is 0 but not 1. – Or fails at low VDD. – Or fails in SFSF corner. Principle: Threshold drop – X never rises above VDD-Vt – Vt is raised by the body effect – The threshold drop is most serious as Vt becomes a greater fraction of VDD. Solution: Circuit Pitfalls CMOS VLSI Design Slide 4 Bad Circuit 1 Circuit – 2:1 multiplexer S D0 D1 X S Y Symptom – Mux works when selected D is 0 but not 1. – Or fails at low VDD. – Or fails in SFSF corner. Principle: Threshold drop – X never rises above VDD-Vt – Vt is raised by the body effect – The threshold drop is most serious as Vt becomes a greater fraction of VDD. Solution: Use transmission gates, not pass transistors Circuit Pitfalls CMOS VLSI Design Slide 5 Bad Circuit 2 Circuit – Latch f X D f Q Symptom – Load a 0 into Q – Set f = 0 – Eventually Q spontaneously flips to 1 Principle: Solution: Circuit Pitfalls CMOS VLSI Design Slide 6 Bad Circuit 2 Circuit – Latch f X D f Q Symptom – Load a 0 into Q – Set f = 0 – Eventually Q spontaneously flips to 1 Principle: Leakage – X is a dynamic node holding value as charge on the node – Eventually subthreshold leakage may disturb charge Solution: Circuit Pitfalls CMOS VLSI Design Slide 7 Bad Circuit 2 Circuit – Latch f X D f Q Symptom – Load a 0 into Q – Set f = 0 – Eventually Q spontaneously flips to 1 Principle: Leakage – X is a dynamic node holding value as charge on the node – Eventually subthreshold leakage may disturb charge f Solution: Staticize node with feedback X D f – Or periodically refresh node (requires fast clock, f not practical processes with big leakage) f Circuit Pitfalls CMOS VLSI Design Slide 8 Q Bad Circuit 3 Circuit – Domino AND gate f 0 1 X Y Symptom – Precharge gate (Y=0) – Then evaluate – Eventually Y spontaneously flips to 1 Principle: Solution: Circuit Pitfalls CMOS VLSI Design Slide 9 Bad Circuit 3 Circuit – Domino AND gate f 0 1 X Y Symptom – Precharge gate (Y=0) – Then evaluate – Eventually Y spontaneously flips to 1 Principle: Leakage – X is a dynamic node holding value as charge on the node – Eventually subthreshold leakage may disturb charge Solution: Circuit Pitfalls CMOS VLSI Design Slide 10 Bad Circuit 3 Circuit – Domino AND gate f X Y 0 1 Symptom – Precharge gate (Y=0) – Then evaluate – Eventually Y spontaneously flips to 1 Principle: Leakage – X is a dynamic node holding value as charge on the node – Eventually subthreshold leakage may disturb charge f Solution: Keeper Y 0 X 1 Circuit Pitfalls CMOS VLSI Design Slide 11 Bad Circuit 4 Circuit – Pseudo-nMOS OR X A B Y Symptom – When only one input is true, Y = 0. – Perhaps only happens in SF corner. Principle: Solution: Circuit Pitfalls CMOS VLSI Design Slide 12 Bad Circuit 4 Circuit – Pseudo-nMOS OR X A B Y Symptom – When only one input is true, Y = 0. – Perhaps only happens in SF corner. Principle: Ratio Failure – nMOS and pMOS fight each other. – If the pMOS is too strong, nMOS cannot pull X low enough. Solution: Circuit Pitfalls CMOS VLSI Design Slide 13 Bad Circuit 4 Circuit – Pseudo-nMOS OR X A B Y Symptom – When only one input is true, Y = 0. – Perhaps only happens in SF corner. Principle: Ratio Failure – nMOS and pMOS fight each other. – If the pMOS is too strong, nMOS cannot pull X low enough. Solution: Check that ratio is satisfied in all corners Circuit Pitfalls CMOS VLSI Design Slide 14 Bad Circuit 5 Circuit – Latch f D Q X f weak Principle: Symptom – Q stuck at 1. – May only happen for certain latches where input is driven by a small gate located far away. Solutions: Circuit Pitfalls CMOS VLSI Design Slide 15 Bad Circuit 5 Circuit – Latch f D Q X f weak Symptom – Q stuck at 1. – May only happen for certain latches where input is driven by a small gate located far away. Principle: Ratio Failure (again) – Series resistance of D driver, wire resistance, and tgate must be much less than weak feedback inverter. Solutions: Circuit Pitfalls CMOS VLSI Design f D Q f weak stronger Slide 16 Bad Circuit 5 Circuit – Latch f D Q X f weak Symptom – Q stuck at 1. – May only happen for certain latches where input is driven by a small gate located far away. Principle: Ratio Failure (again) f – Series resistance of D driver, wire D Q resistance, and tgate must be much f weak less than weak feedback inverter. stronger Solutions: Check relative strengths – Avoid unbuffered diffusion inputs where driver is unknown Circuit Pitfalls CMOS VLSI Design Slide 17 Bad Circuit 6 Circuit – Domino AND gate f A Y X B Principle: Z Symptom – Precharge gate while A = B = 0, so Z = 0 – Set f = 1 – A rises – Z is observed to sometimes rise Solutions: Circuit Pitfalls CMOS VLSI Design Slide 18 Bad Circuit 6 Circuit – Domino AND gate f A B Y X Z Symptom – Precharge gate while A = B = 0, so Z = 0 – Set f = 1 – A rises – Z is observed to sometimes rise Principle: Charge Sharing – If X was low, it shares charge with Y Solutions: f A B Circuit Pitfalls CMOS VLSI Design Y X Z CY Cx Slide 19 Bad Circuit 6 Circuit – Domino AND gate f A Y Symptom – Precharge gate while A = B = 0, so Z = 0 – Set f = 1 – A rises – Z is observed to sometimes rise Z X B Principle: Charge Sharing – If X was low, it shares charge with Y Solutions: Limit charge sharing CY Vx VY VDD Cx CY f A B Y X Z CY Cx – Safe if CY >> CX – Or precharge node X too Circuit Pitfalls CMOS VLSI Design Slide 20 Bad Circuit 7 Circuit – Dynamic gate + latch f X 0 Principle: Y Symptom – Precharge gate while transmission gate latch is opaque – Evaluate – When latch becomes transparent, X falls Solution: Circuit Pitfalls CMOS VLSI Design Slide 21 Bad Circuit 7 Circuit – Dynamic gate + latch f 0 X Y Symptom – Precharge gate while transmission gate latch is opaque – Evaluate – When latch becomes transparent, X falls Principle: Charge Sharing – If Y was low, it shares charge with X Solution: Circuit Pitfalls CMOS VLSI Design Slide 22 Bad Circuit 7 Circuit – Dynamic gate + latch f 0 X Y Symptom – Precharge gate while transmission gate latch is opaque – Evaluate – When latch becomes transparent, X falls Principle: Charge Sharing – If Y was low, it shares charge with X Solution: Buffer dynamic nodes before driving transmission gate Circuit Pitfalls CMOS VLSI Design Slide 23 Bad Circuit 8 Circuit – Latch D GND VDD VDD Q weak Symptom – Q changes while latch is opaque – Especially if D comes from a far-away driver Principle: Solution: Circuit Pitfalls CMOS VLSI Design Slide 24 Bad Circuit 8 Circuit – Latch D GND VDD VDD Q weak Symptom – Q changes while latch is opaque – Especially if D comes from a far-away driver Principle: Diffusion Input Noise Sensitivity – If D < -Vt, transmission gate turns on – Most likely because of power supply noise or coupling on D Solution: Circuit Pitfalls CMOS VLSI Design Slide 25 Bad Circuit 8 Circuit – Latch D GND VDD VDD Q weak Symptom – Q changes while latch is opaque – Especially if D comes from a far-away driver Principle: Diffusion Input Noise Sensitivity – If D < -Vt, transmission gate turns on – Most likely because of power supply noise or coupling on D Solution: Buffer D locally 0 VDD D VDD Circuit Pitfalls CMOS VLSI Design Q weak Slide 26 Bad Circuit 9 Circuit – Anything Symptom – Some gates are slower than expected Principle: Circuit Pitfalls CMOS VLSI Design Slide 27 Bad Circuit 9 Circuit – Anything Symptom – Some gates are slower than expected Principle: Hot Spots and Power Supply Noise Circuit Pitfalls CMOS VLSI Design Slide 28 Noise Sources – Power supply noise / ground bounce – Capacitive coupling – Charge sharing – Leakage – Noise feedthrough Consequences – Increased delay (for noise to settle out) – Or incorrect computations Circuit Pitfalls CMOS VLSI Design Slide 29 Reliability Hard Errors Soft Errors Failure Rate Infant Mortality Useful Operating Life Wear Out Time Circuit Pitfalls CMOS VLSI Design Slide 30 Electromigration “Electron wind” causes movement of metal atoms along wires Excessive electromigration leads to open circuits Most significant for unidirectional (DC) current – Depends on current density Jdc (current / area) – Exponential dependence on temperature Ea kT e – Black’s Equation: MTTF n J dc – Typical limits: Jdc < 1 – 2 mA / mm2 See videos Circuit Pitfalls CMOS VLSI Design Slide 31 Self-Heating Current through wire resistance generates heat – Oxide surrounding wires is a thermal insulator – Heat tends to build up in wires – Hotter wires are more resistive, slower Self-heating limits AC current densities for reliability T I (t ) dt 2 I rms 0 T – Typical limits: Jrms < 15 mA / mm2 Circuit Pitfalls CMOS VLSI Design Slide 32 Hot Carriers E-field across channel impart high energies to some carriers – These “hot” carriers may be blasted into the gate oxide where they become trapped – Charge accumulation causes shift in Vt over time – Eventually Vt shifts too far for correct operation Choose VDD to achieve reasonable product lifetime – Worst problems when substrate current is large – Highest current: saturated nMOS devices • worst for inverters and NORs with fast input rise-time and long propagation delays Circuit Pitfalls CMOS VLSI Design Slide 33 Latchup Latchup: positive feedback leading to VDD – GND short – Major problem for 1970’s CMOS processes before it was well understood Avoid by minimizing resistance of body to GND / VDD – Use plenty ofAsubstrate and well taps GND VDD Y p+ n+ Rsub substrate tap Circuit Pitfalls n+ p substrate p+ n well n well Vwell Vsub p+ n+ Rwell Vwell Rwell Vsub Rsub well tap CMOS VLSI Design Slide 34 Guard Rings Latchup risk greatest when diffusion-to-substrate diodes could become forward-biased Surround sensitive region with guard ring to collect injected charge Circuit Pitfalls CMOS VLSI Design Slide 35 Overvoltage High voltages can damage transistors – Electrostatic discharge – Oxide arcing – Punchthrough – Time-dependent dielectric breakdown (TDDB) • Accumulated wear from tunneling currents Requires low VDD for thin oxides and short channels Use ESD protection structures where chip meets real world Circuit Pitfalls CMOS VLSI Design Slide 36 Summary Static CMOS gates are very robust – Will settle to correct value if you wait long enough Other circuits suffer from a variety of pitfalls – Tradeoff between performance & robustness Very important to check circuits for pitfalls – For large chips, you need an automatic checker. – Design rules aren’t worth the paper they are printed on unless you back them up with a tool. Circuit Pitfalls CMOS VLSI Design Slide 37 Soft Errors In 1970’s, DRAMs were observed to occasionally flip bits for no apparent reason – Ultimately linked to alpha particles and cosmic rays Collisions with particles create electron-hole pairs in substrate – These carriers are collected on dynamic nodes, disturbing the voltage Minimize soft errors by having plenty of charge on dynamic nodes Tolerate errors through ECC, redundancy Circuit Pitfalls CMOS VLSI Design Slide 38