Download Predictive Digital Control of Power Factor Preregulators With Input

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
Predictive Digital Control of Power Factor
Preregulators With Input Voltage Estimation
Using Disturbance Observers
Paolo Mattavelli, Member, IEEE, Giorgio Spiazzi, Member, IEEE, and Paolo Tenti, Fellow, IEEE
Abstract—The paper presents a fully digital control of
single-phase boost power factor preregulators (PFPs) based
on inductor (or switch) current and output voltage measurements.
Input voltage sensing is avoided using a disturbance observer,
which provides a waveform proportional to the rectified input
voltage. The proposed solution is based on a multiloop structure
for PFPs with an internal deadbeat current control and a conventional outer voltage control, possibly with fast dynamic response.
The resulting control algorithm is simple, accurate, and robust
with respect to parameter mismatch. The digital control has been
implemented both in a field programmable gate array and in
a digital signal processor (TMS320F2812), to test the proposed
algorithm with different control delays. Experimental results on
a single-phase boost PFPs show the effectiveness of the proposed
solution.
Index Terms—Digital signal processor (DSP), field programmable gate array (FPGA), power factor preregulators
(PFPs).
I. INTRODUCTION
D
IGITAL controllers for switch-mode power supplies have
some interesting advantages compared to their analog
counterparts, i.e., immunity to analog component variations
and ability to implement sophisticated control schemes and
system diagnostics. While the application of digital control in
high-frequency switching converters was almost impractical
up to now due to cost, performance, and availability of digital
signal processor (DSP) and microcontroller systems, the feasibility of low-cost dedicated digital integrated circuits (ICs)
[1], [2] is somehow changing the future roadmaps of digital
controller applications for switched-mode power supplies.
The investigation of digital control for power factor preregulators (PFPs) is relatively new, and some works are now available [3]–[10]. The control structure described in previous papers is defined according to what is normally done in conventional analog controllers and widely discussed in literature; thus,
the control algorithm is essentially based on a multiloop control
where the outer voltage loop determines the amplitude of the
current reference, while its waveform is given by the rectified
input voltage. Moreover, in [3]–[5], [8], and [9], some advantages of the digital implementation have been investigated, and,
more specifically, digital techniques aimed to remove the output
voltage ripple at twice the line frequency have been used in order
to increase voltage loop bandwidth. Finally, a recent implementation with a field programmable gate array (FPGA) has been
proposed [3], which exploits the potentiality of simultaneous
executions of control procedures. To the authors’ knowledge,
while three-phase PFPs control without input voltage sensing
has been widely investigated in the past, single-phase digitally
controlled PFPs proposed up to now require the measurement of
the input voltage. From the point of view of IC integration, the
main advantages of PFPs control without input voltage sensing
are the elimination of the dedicated analog-to-digital converter
(ADC) and the related pin on the IC package.
This paper presents a fully digital control of boost PFPs,
where line input voltage sensing is avoided, and a disturbance
observer is used for its estimation. More specifically, the proposed solution is based on a multiloop structure for PFPs with
an internal deadbeat current control, which highlights a simple
algorithm for input voltage estimation and an outer voltage
control with fast dynamic response. Stability analysis of the
proposed scheme shows that the system is stable, even in the
presence of a relatively large parameter mismatch. Moreover,
the proposed estimation scheme reduces possible interactions
with the electromagnetic interference (EMI) filter compared
to the solution where input voltage sensing is adopted. The
control algorithm has been first implemented in an FPGA
board with fast A/D converters, where the overall control delay
is quite small with respect to the sampling period and, thus,
negligible for the control law derivation. The proposed solution
has also been implemented in a DSP (TMS320F2812), where
the conventional one-sampling-period delay has been taken into
account in the control algorithm. In both cases, experimental
results confirm the properties of the proposed approach.
II. CONTROL METHOD
Manuscript received August 27, 2003; revised April 29, 2004. This work was
supported in part by Altera and Texas Instruments. Recommended by Associate
Editor B. Lehman.
P. Mattavelli is with the Department of Electrical, Management, and Mechanical Engineering (DIEGM), University of Udine, Udine 33100, Italy (e-mail:
[email protected]).
G. Spiazzi and P. Tenti are with the Department of Information Engineering,
University of Padova, Padova 35141, Italy (e-mail: [email protected];
[email protected]).
Digital Object Identifier 10.1109/TPEL.2004.839821
Fig. 1 shows the basic scheme of the proposed method applied to a boost PFPs. The PFPs current controller operates the
whose waveswitch so as to draw from the grid a current
form is proportional to the line voltage
by a factor determined by the voltage control loop. Being the estimated line
, the proposed control requires the sampling of two
voltage
variables: output voltage and average input current.
0885-8993/$20.00 © 2005 IEEE
MATTAVELLI et al.: PREDICTIVE DIGITAL CONTROL
141
Fig. 2. Basic waveforms of triangle PWM and of sampling instants in the
middle of switch-on period.
Fig. 1.
Digital control of boost PFC with line voltage estimation.
In Section II-B–D, we derive the control technique taking
into account the one-sampling-period delay usually required
due to computational time in microcontrollers and DSPs. In
Section II-E, we extend the technique to the case where digital
processing time is negligible.
dead-beat controller, the control algorithm calculates the dutycycle to ensure that the current reaches its reference by the end
of the following modulation period, taking into account one period delay in the digital implementation. By imposing that the
is equal to the current reference
at incurrent
, the following control algorithm is obtained:
stant
A. Sampling Instants
An advantage of the digital approach is that the average
value of the sensed current is obtained, without lowpass filters
in the loop, by synchronizing sampling and modulation so that
the current is always sampled in the middle of the switch-on
or switch-off period if continuous conduction mode (CCM) is
assumed. One common procedure to avoid possible sampling
noise around the switching transition is to choose the sampling
in the middle of the switch-on period when the duty-cycle is
greater than 0.5 and in the middle of the switch-off period
when it is lower than 0.5. While the two sampling instants are
equivalent in CCM, there are some differences in discontinuous
conduction mode (DCM) so that the crossover distortion may
be different depending on the sampling strategy. As far as
the digital pulse-width modulation (PWM) is concerned, the
triangle modulation has been adopted, as depicted in Fig. 2,
which provides the sampling instants either in the middle of the
switch-on or switch-off period when the PWM carrier changes
slopes, at least under steady-state conditions. Moreover, compared to trailing edge or leading edge modulation, it ensures
both constant sampling frequency and sampling instants in the
middle of the switch-on or switch-off period [11].
(2)
where we have assumed that
and
. If the rectified line voltage
is sensed, control algois able to follow the
rithm (2) ensures that the line current
with two-cycle delay.
reference current
C. Disturbance Observer
is not sensed,
Assuming that the rectified line voltage
we propose to put this term to zero in (2), obtaining the following control law:
(3)
Using (3), the current is now able to follow the reference with
a two-cycle delay, as well as with an uncompensated disturbance
given by the rectified input voltage. In order to evaluate the expression of this uncompensated term, let us combine (1) and (3)
can be
using the -transform; thus, the inductor current
written as
(4)
B. Digital Deadbeat Current Control
As far as the current control is concerned, the discrete-time
model of inductor dynamics in CCM can be expressed as
(1)
where
is the average inductor current,
the rectified
input voltage,
the output voltage, and
the comple, all of them evaluated at the samment of the duty-cycle
. The inductor current control is performed
pling instant
by means of the dead-beat control technique [12], which ensures fast dynamic response and simple implementation. In a
where the first term is the two-cycle delay inherently present in
the deadbeat control, and the second term represents the uncompensated disturbance, which is, indeed, proportional to a combination of delays of the rectified input voltage. Assuming that
the input voltage is slowly varying compared to sampling time
so that it can be considered constant between two samples [i.e.,
], (4) can be written in the following form
[13]:
(5)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
where
. Thus, the proposed
current control can be represented as the block diagram reis the unknown disturbance
ported in Fig. 3(a), where
which includes the uncompensated rectified input voltage and
. Looking at (3), the control law can be
seen as a proportional controller, with proportional gain equal
and a delay compensation [given by term
to
]; from this point of view, (5) shows that the disturbance
is the current error of controller (3), which, due
current
to the purely proportional action, does not provide sufficient
loop gain to ensure precise current tracking.
In order to provide a precise current control, disturbance
needs to be estimated and then compensated by a
feedforward action, subtracting the estimated disturbance
to actual current reference
, as shown in
term
Fig. 3(b). The feedforward action ensures, under ideal operation, that the current error is reduces to zero under state-state
conditions, as reported hereafter. One interesting properties of
, which is needed for
the proposed scheme is that signal
improving the current control tracking, also gives an estimation
of the rectified input voltage waveform, which is useful for the
generation of the current reference waveform.
is obtained folThe estimation of the disturbance
lowing Fig. 3(a) and assuming
; using
and the delayed reference current
the disturbance term
as state variables, the following state
equations can be written:
(6)
The observer for disturbance
the following Luenberger estimator:
(11)
and it is reported in Fig. 3(b). Note that the control algorithm is
very simple and requires only a delay line and a subtraction. The
shown
feedforward compensation of disturbance term
in Fig. 3(b) realizes an additional loop in the proposed control.
However, it is easy to verify that, without accounting for parameter or model mismatches, the closed-loop poles of the resulting
scheme shown in Fig. 3(b) are still in the origin, thus ensuring
the deadbeat response of the overall system.
D. PFC Control With Line Voltage Estimation
and
,
where
and
are the estimator gains. It is not convenient to
where
implement (7) in a real-time algorithm, since it is too complex,
and it would provide also the direct estimation of the state vari, which is useless in the proposed solution. Instead,
able
(7) can be solved to obtain the algorithm only for the direct esti. For such a purpose, (7)
mation of the disturbance term
is first written using the -transform as
(8)
. Solving (8), the estimated state vector
is
(9)
is the 2
where
solving (9) for
where coefficients
and
determine the speed of response
and
of the estimator. In the case of deadbeat estimation,
, and the final estimation law is
is then evaluated using
(7)
where
given by
Fig. 3. (a) Equivalent block diagram of the current control and (b) proposed
control with deadbeat disturbance estimation.
2 identity matrix. The result obtained
is
(10)
One of the main properties of the proposed approach is that
, estimated using (10) and (11), is theoretically
signal
. Even in the
proportional to the rectified input voltage
practical case, we expect this term to be dominant respect to
second-order effects, such as delays in the gate pulse, inductor
can be
saturation, etc. Thus, the estimated disturbance
used for the determination of the waveform of the actual in, as reported in Fig. 3(b), where
ductor current reference
the proposed digital control algorithm, including a possible implementation for the voltage loop, is shown. Indeed, the use of
in order to determine the refthe estimated disturbance
introduces an additional loop in the proerence current
posed scheme, which must be analyzed in order to validate the
proposed approach, as performed in Section III-B.
E. Control Algorithm in Case of Negligible Delay in the
Digital Implementation
If A/D conversion time and control algorithm execution are
just a small fraction of the sampling period, which may be the
case in FPGA implementation with fast A/D converters or in
dedicated digital ICs, the duty cycle can be updated just after
; thus, there is no delay
the sampling of inductor current
in the digital implementation and the predictive algorithm needs
MATTAVELLI et al.: PREDICTIVE DIGITAL CONTROL
143
to be modified accordingly. It is easy to verify that the control
algorithm (3) becomes
(12)
is able to follow the reference curand the line current
with only one-cycle delay. Moreover, the estimation
rent
process (11) simplifies as
(13)
and this term can again be used for the estimation of the input
voltage waveform. Note that the resulting control algorithm is
even simpler, requiring only a proportional gain (12), a delay
line, and a few additions/subtractions.
Fig. 4. Real and imaginary part of the closed-loop poles with Case A, = 0; varied between 0.1 and 1.3.
III. STABILITY ANALYSIS
In order to highlight some properties of the proposed scheme,
the robustness against parameter variations, the effects of the
reference current generation, and the behavior in DCM mode
are analyzed. For such purpose, let us define the inductor current
as
reference
(14)
is determined by the voltage loop control [see
where
Fig. 3(b)]. Moreover, we define
as the modeled inductor
value, which is assumed in the control gain derivation, and
as a factor which accounts for parameter mismatch, where
.
A. Effects of Parameter Variations
In this section, we focus on the current control, neglecting the
interaction with the reference current generation and, thus, we
assume that the coefficient is equal to zero. In this simplified
case, the stability analysis of the closed-loop system can be performed by applying the -transform to (1) and (3), where has
been substituted by
, by deriving the characteristic polynomial of the closed-loop system and by mapping the closed-loop
poles. If the magnitude of the closed-loop poles is equal to or
greater than one, the resulting system is, of course, unstable.
Following this procedure, we found that the characteristic
polynomial is given by
(15)
if the control delay is included, which we refer as Case A. Instead, if the control delay is negligible, which we refer as Case
B, the characteristic polynomial has the same structure as (15),
is substituted with , and
with , as it
as long as term
is easy to verify using (1), (12), and (13). Inspection of (15)
shows that the system is stable as long as parameter is below
a factor of around 1.33, showing that underestimation of the inductor value L does not cause stability problem. Clearly, severe
underestimation also decreases the current control bandwidth so
Fig. 5. Real and imaginary part of the closed-loop poles with Case B, = 0; varied between 0.1 and 1.3.
that a tradeoff between robustness and speed of response determines the control gain. As an example, Figs. 4 and 5 report the
closed-loop poles of Case A and B, respectively, when the
parameter is varied between 0.1 and 1.3. In both cases, system
stability is verified.
It is worth pointing out that unstable conditions occur when
is overestimated and derived from the fast deadbeat estimator
and
. If different estiused in (11), where
mation gains were used, a much higher stability margin would
have been achieved. This solution has not been adopted due
to the higher complexity ofthe second-order filter [see (10)].
Moreover, due to the slower estimator, this solution gives also a
slower dynamic response that is quite similar to that obtainable
using (11) with an underestimation of the value. As a result,
the proposed solution with an underestimation of gives a very
similar performance in terms of control bandwidth and system
robustness compared to the more complex estimation algorithm.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
Fig. 6. Real and imaginary part of the closed-loop poles with Case A,
0–0:8; = 0:6.
=
Fig. 7.
Real and imaginary part of the closed-loop poles with Case A,
0–0:8; = 1:3.
=
in the case A and
B. Effects of Reference Current Proportional to Estimated
Input Voltage
Including (14) in the stability analysis, (15) is modified as
(16)
Let us first estimate the value of parameter . A steady-state
analysis of the PFPs boost converter in CCM shows that
(17)
where
is the maximum peak-to-peak ripple current octhe peak of the sinusoidal input current,
curring at
and the peak input voltage. Analysis of (16) shows that, with
, there is alrespect to the case of the previous section
,
ways an increase of the system phase margin as long as
which is very likely to happen in a standard CCM design [see
(17)]. As an example, Fig. 6 reports the closed-loop poles of
. SimCase A, when is varied between 0 and 0.8, and
ilarly, Fig. 7 reports the closed-loop of Case A, when is varied
. In both cases, phase margin is
between 0 and 0.8 and
improved when is increased.
C. Issues in DCM Mode
Inordertounderstandhowtheclosed-looppolesmovewhenthe
converter operates in DCM, the discrete time dynamic model (1)
is substituted with the dynamic equation corresponding to DCM.
Taking into account the triangle PWM modulation (Fig. 2) and the
sampling at the middle of the switch-on period, the dynamic equation in DCM is expressed by
(18)
Applying the same procedure presented in previous sections,
we found that the characteristic polynomial is given by
(19)
(20)
. Inspection of (19) and (20)
in the case B, where
shows that the stability of the system is ensured in both cases A
and B, even for parameter variations of and greater than that
founded in CCM. The main issue in DCM is that the loop gain is
much lower, as typically reported also in the analog controller,
and thus, current tracking is somehow compromised.
IV. INTERACTIONS BETWEEN EMI FILTER AND PFPs
In order to evaluate possible interactions between the EMI
filter and the closed-loop PFPs, the ratio of the EMI filter output
and the converter input impedance
impedance
needs to be analyzed. In fact, such ratio can be interpreted as
the loop gain
(21)
which must satisfy stability criteria in order to avoid interaction
between the EMI filter and the power converter [14]. In order to
highlight possible reduction of these interactions due to the proposed estimation scheme, we have reported in Fig. 8, the magnitude and phase of the closed-loop input admittance using the
scheme of Fig. 3(b) where inductor current reference
has been evaluated using the measurement of the input voltage
(trace a) and the proposed estimation scheme (trace b). In order
to simplify the analysis, the voltage loop control has been ne, and a parameter mismatch of
glected by imposing
. Note that the proposed so40% has been adopted
lution shows a magnitude reduced by around 4 to 5 dB, with a
small phase increase close to the current loop corner frequency,
where interactions with the EMI filter usually occur. Thus, the
proposed solution gives a small advantage even from this point
of view.
V. EXPERIMENTAL RESULTS
The proposed solution has been tested both using numerical simulations and experimental prototypes. Simulation results
MATTAVELLI et al.: PREDICTIVE DIGITAL CONTROL
Fig. 8. Closed-loop PFPs input admittance with the (a) measurement and the
(b) estimation of the input voltage.
Fig. 9.
145
Fig. 10. Line input voltage v (100 V/div) and input current
100% of the nominal load without offset compensation.
i
(2 A/div) at
Line input voltage v (100 V/div) and input current i (1 A/div).
have confirmed the analysis presented in the previous sections
and are not here reported. From the experimental point of view,
a boost PFPs prototype has been realized with the following pa2 mH,
F,
rameters:
kHz,
V, and
W. The digital
controller has been first implemented using an FPGA by Altera
(specifically the EPF10K20 device, a member of FLEX 10 K
family) and the control algorithm has been developed using a
hardware description language (VHDL), providing great flexibility and technology independence. Fast A/D converters (with
10-b resolution) have been used so that the overall control algorithm takes less than 1 s, which can be considered a negligible
delay compared to the switching period. The internal arithmetic
of 10 b has been adopted in the FPGA, and the voltage loop
notch filter has not been included in the FPGA implementation
prototype, since we did not consider it important for the verification of the performance of algorithms (11) and (12). Some
W),
results are reported in Fig. 9 (for
which shows that the filtered input current waveform reproduces
the highly distorted input voltage waveform, thus achieving an
almost unity power factor.
The control algorithm has been intensively tested also in a
newly developed DSP by Texas Instruments (TMS320F2812),
which we found a powerful and flexible hardware support for
rapid prototyping. Indeed, the DSP used is much more powerful than needed for the specific application since we needed
only a few percent of the processor time to implement the proposed algorithm. The use of this specific hardware should be
seen only for rapid-prototyping purposes. In the DSP case, the
Fig. 11. Normalized input current spectrum at 100% of the nominal load
without offset compensation (Vertical scale: 10 dB/div, horizontal scale:
50 Hz/div).
control delay is assumed to be equal to the PWM period. Indeed, all experimental results reported, besides Fig. 9, are related to the DSP implementation mainly because this experimental setup was developed in a laboratory where a low distorted sinusoidal power supply is available.
and unfiltered input curFig. 10 shows the input voltage
rent
at full load and nominal input voltage of 230
.
Note that the distortion on the current waveform is quite small,
even during zero crossing of the input current. This is also verified by the input current spectrum, reported in Fig. 11, where
all harmonics are below 40 dB of the fundamental one, besides
the third harmonic component. Fig. 12 also shows the wave, which is obtained
form of the estimated disturbance term
using an auxiliary PWM with a lowpass filter. Note that
closely tracks the input voltage, besides a small phase shift due
to the lowpass filter. Note also that a small offset is present in the
estimated term due to a constant error (offset) between the actual duty-cycle and the duty-cycle driven by the digital control,
which is equal to 3% of the switching period in our prototype.
Indeed, by compensating this error in the DSP software, which
is due to our drive circuit, we were able to further reduce the
THD, bringing all harmonics below 40 dB, as shown in Fig. 13.
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 1, JANUARY 2005
Fig. 12. Rectified input voltage v (100 V/div), estimated disturbance i ,
and input current i (2 A/div) at 100% of the nominal load without offset
compensation.
Fig. 15. Normalized input current spectrum at 25% of the nominal load
(Vertical scale: 10 dB/div, horizontal scale: 50 Hz/div).
Fig. 16. Load transient from 25% to 100% of nominal load. Ouput voltage v
(20 V/div) and input current i (2 A/div).
Fig. 13. Normalized input current spectrum at 100% of the nominal load with
offset compensation (Vertical scale: 10 dB/div, horizontal scale: 50 Hz/div).
Fig. 17. Load transient from 100% to 25% of nominal load. Ouput voltage v
(20 V/div) and input current i (2 A/div).
Fig. 14. Line input voltage v (100 V/div) and input current
25% of the nominal load power with offset compensation.
i
(1 A/div) at
We have also tested our system at 25% of the nominal power
where the converter operates in DCM for a part of the line peand unfiltered input
riod. Fig. 14 reports the input voltage
and Fig. 15 the normalized input current spectrum.
current
In this case, the current waveform distortion is higher due to the
lower control gain in DCM.
Finally, we have tested the dynamics of the voltage control
imposing step load changes from 25% to 100% of the nominal
load (Fig. 16) and vice versa (Fig. 17). One important advantage
of the digital implementation is the possibility to obtain quite
easily a fast dynamic response. Among the solutions proposed
in the past, we have implemented a notch filter tuned at twice
the line frequency. Figs. 16 and 17 report the load transients and
MATTAVELLI et al.: PREDICTIVE DIGITAL CONTROL
confirm the possibility to realize a high control loop bandwidth,
which is not easy to achieve by analog means.
VI. CONCLUSION
This paper has proposed a fully digital control of boost Power
Factor Preregulators, where the line input voltage sensing is
avoided, and a disturbance observer is used for its estimation. A
predictive-type current control has been adopted since it features
simple implementation, fast dynamic response, and a direct algorithm for input voltage estimation. As shown in the stability
analysis, the proposed solution is robust against parameter variations, especially if the inductor value is underestimated. The
proposed algorithms have been verified by experimental tests
on a boost PFPs, basically confirming the theoretical analysis.
ACKNOWLEDGMENT
The authors wish to thank R. Sartorello and M. De Sanctis
for their support in the experimental activities.
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Paolo Mattavelli (S’95–A’96–M’00) received the M.S. (with honors) and Ph.D.
degrees in electrical engineering from the University of Padova, Padova, Italy,
in 1992 and 1995, respectively.
From 1995 to 2001, he was a Researcher at the University of Padova. In
2001, he joined the Department of Electrical, Mechanical and Management Engineering (DIEGM), University of Udine, Udine, Italy, where he has been an
Associate Professor of electronics since 2002. He is responsible of the Power
Electronics Laboratory, DIEGM, which he founded in 2001. His major field
of interest include analysis, modeling and control of power converters, digital
control techniques for power electronic circuits, active power filters, and power
quality issues.
Dr. Mattavelli is a Member of the IEEE Power Electronics, Industry Applications, and Industrial Electronics Societies and the Italian Association of Electrical and Electronic Engineers (AEI). He currently serves as an Associate Editor
for IEEE TRANSACTIONS ON POWER ELECTRONICS and Member-at-Large of the
PELS Adcom.
Giorgio Spiazzi (S’92–M’95) received the M.S. degree (with honors) in electronic engineering and the Ph.D. degree in industrial electronics and informatics
from the University of Padova, Padova, Italy, in 1988 and 1993, respectively.
He is an Associate Professor in the Department of Information Engineering,
University of Padova. His main research interests are in the fields of power factor
correctors, soft-switching techniques, lamp ballast, and electromagnetic compatibility in power electronics.
Paolo Tenti (F’99) is a Professor of power electronics and head of the Department of Information Engineering, University of Padova, Padova, Italy. His main
interests are industrial and power electronics and electromagnetic compatibility.
In these areas, he holds national and international patents and has published
more than 100 scientific and technical papers. He is President of CREIVen (an
industrial research consortium for tecnological advancements in industrial electronics, with special emphasis on electromagnetic compatibility), Padova, Italy.
His research focuses on application of modern control methods to power electronics and EMC analysis of electronic equipment.
Dr. Tenti was elected Vice-President of the IEEE Industry Applications Society (IAS), in 1996 and served as IAS President in 1997. In 2000, he chaired
the IEEE World Conference on Industrial Applications of Electrical Energy
(Rome). From 2000 to 2001, he was appointed IEEE-IAS Distinguished Lecturer on “Electromagnetic compatibility in industrial equipment.”