Download Abstract dfm I. Introduction II. Dynamic and short

Dynamic
and Short-Circuit
Power of CMOS
Driving
Lossless
Transmission
Lines
Yehea
1. Ismail,
Eby G. Friedman,
Department
of Electrical
Engineering
University
of Roche&r
Rochester,
New York 14627
Abstract
I.
Introduction
Historically,
interconnec( has been modeled as a
single lumped capacitance in the pcrfcrmance analysis
oi on-chip interconnects
[l]-[6]. With the scaling of
technology and increasing chip size. the csosssectional
arca of w&es has scaled down while interconnect length
hx incrcascd. The rcsistancc of the interconnccl has
therefore hccome significant.
requiring more ac~ulatc
KC delay mod& 171. Initially, the inlcrconnect
was
mod&d as a lumped KC circuit. To further improve
is often modeled as a
accuracy, the interconnect
dislributed KC circuit (as multiple T or Fl sections) for
those nets requiring increased accuracy [Xl, [9].
Currently, inductance is becoming mow important
with deweasing on-chip l-ix times and longer wire
lengths [IO]-[16]. Wide wires al-e irequently encountered
in clock distribution nclwol-ks and in data busses. These
wires. ,a,1
at the uppcr metal layers. arc low
resistance wires that can cxhihir significant inductive
Gates
and Jose L. Neves’
‘IBM Microelectronics
IS80 Route 52
East Fishkill, New York
12533
dfm
Furthermore
performance
[151, j161.
requirements are accelerating the introduction
of neu’
materials such as low resistivity copper interconnect
1171. In the
limitine
case,
high
temperature
superconductors may possibly become commerciall)
available [IS]. More accurate RLC transmission
line
models are therefore becoming necessary in the analysis
of VLSI-based interconnect.
The RC model can be viewed as a limiting case of
the RLC transmission line model where the inductance
is considered to be negligible.
This case has been
thoroughly investigated and is well represented in the
literature [19]-[24]. The other limiting case is an LC
transmission
line where the resis&nce is negligible.
This case approximates the low loss lines encountered
in Multi-Chip
Modules (MCM) and Printed Circuit
Boards (PCB). Although it is highly improbable that
the resistance of on-chip interconnects
will become
negligible in the near term. an LC analysis provides an
upper limit for analyrine inductance eiiects in VLSI
circuits. The behavior of an RLC transmission line can
thcreiore be bounded by analyzing the behavior of the
RC and the LC cases.
The focus oi this paper is the investigation
01
dynamic and short-circuit
power in CMOS
sates
driving LC transmission lines. The dynamic and shortcircuit power consumprion of a CMOS gate driving an
LC transmission lint is presented in x&on
II. The
analysis in section II is performed for the case where
the transition time of the signal at the input of the
CMOS gate driving a transmission line is smaller than
twice the time oi flight of the waves propagating across
the transmission
line. The short-circuit
to dynamic
power ratio for 3 losslcss transmission
line load is
cxamincd in section 111and compared to the same ratio
when the load is a simple capacitor or an KC lint.
Finally. some conclusions xc oficrcd in section IV.
II.
Dynamic and short-circuit
power
The dynamic power consumption
can bc derival
from analyzing the basic hchavior oi a Iransmission
lint interacting with n CMOS gate. This topic is
discussed in subsection ,A. It is shown that the dynamic
powcl- consumption
oi a CMOS :ate driving
il
transmission
lint is 11x wmc as the dynamic powx
consumption
of a gate driving a capacitor yual 10 the
total capacim.ncc ol’ the transmission line. In suhscction
B, the short-circuit power consumption
of a CMOS
gate driving a lossless rransmission line is investigaed
for the rcgimc whcrc r,<ZT, where f, is the rise time of
the input signal of the CMOS gate and T,, is the time
of flight of the signals across the transmission line.
A. Dynamic power
A MOS transistor driving a lossless transmission
lint launches an initial voltage wave with a value
V,=l,, Z, where I,YO,is the saturation current of the
CMOS gate and Z,, is the charactaistic
impedance of
the lint. This initial voltage signal propagates towards
the load and reaches the load at time T,,. Assuming the
load is open 01 is a small capacitor, a voltage wave
propagates hack towxds the transistor with a magnitude
V, and a current wave -I,,. This wave returns to the
MOS transistor at time ZT,. At that moment the
cul~ent of the two waves cancels and the voltage adds to
ZV,. For this period of time (from 0 to ZT,), a current
of V/Z, is drawn from the power supply. At r=ZT,,. a
new voltage wave is initiated with a value Vj=l(l’DD2V,-V,)Z,,. whel-e /(VDO-2VI-V21 is the current of the
transistor with V,,,,,=ZV,+V?. The cycle is repeated and a
current V-a,, is drawn from the supply for the period of
time fium ZT,, f~ 4T,. This cycle repeats until the
voltage at the output of the transistor reaches V,,. The
last voltage wave is assumed to he V,,, where II is the
number of traversals of the line required to reach steady
state. The number of iterations can in general be
infinite or only one in the perfectly matched case
(where the geometric width OS the driving transistors is
adjusted so that the output impedance of the CMOS
gate is equal to the characteristic impcdancc of rhe
transmission line). The output current as a function of
time 01. a PMOS transistor pulling up the output
voltage is shown in Fig. I.
v,+v,+...-l~,
(1)
=+.
where the final wltags
is V,,
once the transient
response reaches the steady state value. From rhis
analysis. rhe energy raken from the power supply for a
low to high transition is given by
Ed~,,lC\i.le=VDD.27,.(V,+V2
ZO
Using (I) and noting that T,&
+.._+I{,)-
(2)
is equal to C,. the total
capacitance of the line, (2) evaluates to
Em, / Cycle = C, V,,*
(3)
This energy is stored in the capacitance of the lint and
is passed to the ground in the following high to low
transition as the line is discharged. Thus, (3) represents
the energy per cycle of rhe output of the CMOS gate.
The dynamic power is therefore
P&,, = c,
VD”2.F
(4)
where f is the frequency of the signal at the output 01
the CMOS gate. This formula is the same as the
dynamic pawcr for a capacitor which equals the total
capacitance of the line.
B. Short-circuit
power
The other component of switching transient power
in CMOS circuits is the short-circuit power that occurs
when both the NMOS and the PMOS transistors
conduct current at the same time. This power is
consumed during the rise (fall) time of the input si,onal
when the input signal is between V,,+V,,
and V,
(where V, is the threshold voltage of the Nxhannel
device and V, is the threshold voltage of rhe P-channel
device and is ncpativc for an enhancement mode device).
The case considered here is when the rise time is less
than twice the propagation
delay across the line
(r,<ZT,,j. In this cast. the reflections do not affccr ihc
short-circuit power hccausc the sipnal returns to the
driver after the input signal has reached its final value.
Under this condition; the mmsmission line appears as a
rcsistancc with a value Z,,. The equivalent circuit oi a
CMOS inverta driving a IossIcss transmission
line for
rhe period of time 0 to ZT,, is shown in Fig. 2, where
C,, is the intrinsic drain capacitance of the CMOS
inserter. The differential equation descrihinp the KCL
for the ourput node is
1+ (“,>I>- “:1,/1
1
(3
0. -I,,) = c,, d( 16,>- ‘:1111
d,
ZS,
where I,,and I,, are the cuncnts of the NMOS transistor
and the PMOS transistor. respectively. Note that ihc
rcsistancc Z,, representins
the transmission
line is
conncctcd hctwccn V,,,> and V,,,,, hecause rhe line is
assumed to he char& to V,],, and that d(l:,,-V,,,,,i/dr=dil’,,,,,J/dr. The NMOS transistor is assumed to hc in the
saturation i-cgion during lhc rise time of lhc input
signal. This assumption is even more accurate in dq
suhmiclometcltechnologies
hecausc of the cariy
saturation phenomenon
1251. On the other hand, the
PMOS transistor starts in the linear region and then
enters the saturation region. Note that the shoti-circuil
current is the current through the PMOS transistor
during a rising input. The signal at the input of the
CMOS driver is
(61
!I//, =&:,=!!a,.
‘r
before the input reaches V,, (i.e., f < V,JkJ
v,,,
Fig. 2. Equivalent circuit of a CMOS driver driving a
lossless transmission line for Oct<ZT,.
Bxcd on the alpha power law, when the PMOS
transistor is in saturation the short-circuit current is
wha-c P, is a constant that characterizes rhe dke
current of the transistor in saturation, W and L are the
geometric width and length,
respectively,
of the
transistor, and a is a constant between one (stron:
velocity saturation) and two (weak velocity saturation)
[25]_ ,I indicates the PMOS transistor and n indicates
the NMOS transistor.
When the PMOS transistor
opcratcs in the linear region, the solution of (5) appears
intl-actahlc hecausc V,, is a function of V,,,,,. Therefore.
the cun’cnt from the output capacitor C, is assumed 10
he small comp~rcd to the current from the transmission
line.
This
assumption
is
accurate
in
d=p
suhmicromew
technologies,
because the transistors
have small parasitic capacitances and high current
levels. The magnitude of rhc drive current is relevant
hccausc smaller transistors are needed to match the
transmission line, implying a smaller C,. Also Z,, is
typically in the range of 30 to 60 ohms, which results
in large currents compared to the parasitic capacitance
C,,. Under this assumption and using the alpha poner
law model. the output voltage is
% ~p~ .!L(l,_,,
)‘“,
‘I (‘, rl
“,
(Si
L = ‘J,,,,
,+ ?.?.(V
,,,, 4,+,$z,,
iiv the time 0 < ii f, where f, < 2T,,. Noting that \JDDv,,,,, is 4, of the PMOS tmnsistor, the short&circuit
cun’cnt
of a CMOS
inverter driving an LC transmission
lint is
Z” p,. :
Cki V,”)‘”
I,, =
;;
~~(~,,,“-k,-ll:,.l)~!~+l’
(3
A CMOS gate driving a transmission
line can be
most efficiently characterized hy the matching factor k
When L =I, the transistor is optimally matched to the
transmission
line. If ;I is less than one.
the
transmission
lint is underdriven and the response
suffers from a slow output rise time. If J. is greater
than one; the transmission
line is overdriven and the
response suffers from overshoots and undershoots that
can cause rcliahility problems. If the overshoots
and
undershoots arc large enough, logical el~ors can occur.
Voltages higher than the supply voltage and lower than
ground create large electric fields that can deteriorate the
oxide and create hot electron effects. Also, out of rail
voltages can forward bias the junctions
between the
drain and source and the substrate, the n-well, or the pwell. When these junctions are fonvard biased, cuxnt
flows directly
into the wells or the substrate. This
hehaviol- is undesirable
hecausc it wastes current.
dissipating extra power. and can induce other reliability
problems within the substrate. Thus, the range defined
by 0.3 < ;i < I.6 is arbitrarily chosen to reprcsenr the
range of interest characterizing
practical
matching
conditions. The analytical solutions of (7) and (9) are
compared to AS/X [26] simulations in Fig. 3 assuming
r, = 100 11.5and using L as a parameter. The analytical
solution
shows good agreement
with the circuii
simuiaiions for n wide range of A-.
The short-circuit
energy per transition
can k
calculated from
E~c / Transifion = A’YUSC VDD3
(11)
where Area,, (in coulombs) is the area under the short&
circuit current curve. This area can be approximated by
a triangle
[21] whose base is given
by iv,>,,and height is given by I,_,,,~ (the
V,+ V,JvVm
maximum point on the short-circuit current curve).
Thus, the short-circuit energy per transition is
/?siuc/7,nruiiiou =+(\J,ID-V,,
-IV~p~),I)I,~K,~ (12)
where K, is a correction factor. Note in Fig. 3 that the
ailalytical solution deviates from the simulated results
in a consistent way af ihe point of intersection of the
saturated cuwe and the linear curve. This deviation is
due to the non-monotonic
nature of the alpha pwcr
law model used to chxactcrize the devices.
:
‘~,
quantilies in l,,,,c,Lthe effect oi the output
shape on the short-circuit current. Note that
K(?LJ saluratcs 10 an asynlptofic value. This behavior
can he explained by observing how the shape of the
output signal varies with L in Fig. 5. Note tha the
shape of the output voltage waveform depends heavily
on J. for small L and this dependence saturates as L
increases. The short-circuit current depends upon the
output voltage because rhe drain to source voltage
auoss the PMOS transistor is dependent on V,,,,,. The
pate to source voltage of the PMOS transistor depends
only on the input signal of the transistor (since the
source is connected to the power supply). Thus. the
biasing of the PMOS transistor depends only on 7,. The
current of the PMOS transistor depends on the bias
voltage and the geomeuic width. The AS/X circuit
simulator is used to quantify the accuracy of these
analytic equations, such as the comparison of (12) with
AS/X 1261 in Table 1. The analytical solution shows
good agreement (less than I% en’or for i. > I) wi~b the
circuit simulations for a wide range of ,I and exhibits a
maximum error of 117~ for small A.
‘1
K(lj
1
wavefirm
Table 1: AS/X simulations compared to analytical
solution for E&ansition
(in joules).
a=l.h
2.=1.8
Fig. 3. Analytical solution for short-circuit current Isc
(IIIA) in (7) and (9) compared to ASK simulations
[26] for x=0.4, 0.6, 1.0, 1.2, 1.4, 1.6, and 1.X.
Due to this consistent enor at the saturationilinem
region hrcakpoint, a constant correction factor K, is
used and calibrated at h=I. I,z,,c,kcan be calculated by
equating (7) and (9). Alternatively,
I,,er,k can bc
calculated as
I ,,eak = K(W,,.
(13)
where K(L)
is determined
from varying
calculating /,,c,t,I/W,r KC& is plotted in Fig. 4.
L
h
AS/X
Simulation
0.8
182.77
178.95
2.09
I
1.0
199.60
199.60
I 0.00
’
Analytical
XIO~”
i
%
~
~ En-or 1
1.2
212.55
212.30
~ 0.12
~
I .4
1.6
224.85
23 1.93
223.20
231.37
0.60
~ 0.24
i
1.X
239.6X
238.20
I 0.62
I
to dynamic
power
and
III.
Short-circuit
ratio
Assuming a symmerric
circuit power is
CMOS
gate. the short-
psc = ‘jw”~(“lxl~ iin - Ivip If) r/’
As dcscrihed orcviouslv. rhs dvnamic power is
(14)
Dividing (14) by (IS). lbc ma,onitude of rhc dynamic
power can hc compared to the magnitude of the \bol.icircuit nowcr. The rcsulunr ratlo is
20%
of the dynamic
power
[3].
RC
For
loads
the
P,JPp,,,, ratio is even greater because the voltage dmp
across the load resistance makes the .sourcc IO drain
voltage large once the transistor
hegins to switch.
As the rise time of the input signal i,~ increases.
shon-circuit
power
increases, since there is more
for the short-circuit
current
does not affect the dynamic
to flow.
power
The
of
dynamic
power.
Dynamic
increasing
T,, because the total capacitance
Thus, as
increases
linearly.
the short-circuit
power
power
linearly
which
increases
power
ratio
of
the
the
power decrease as r, is increased.
short-circuit
power
T,, as
by
rise
power
of the short circuit
is
of the line
input
dynamic
t,~
the
with
the dynamic
making
Fig. 6. Dependence
the
t,~
of the line
is not affected
long as T,, is greater than half
to
increases
Tt, increases, the capacitance
The short-circuit
rime
time
and thus increasing
increases the ratio
T,/z,
rise
the
time,
to
the
to dynamic
power ratio on /1.
IV. Conclusions
The dynamic
a CMOS
investigated.
CMOS
and shon-circuit
gate drivinp
power consumed
3 lossless
transmission
It is shon-n that the dynamic
fate driving
gate driving
to the
of
total
solution
capacitance
the
for the short-circuit
agrees with
circuit
line
A
is the
equal
closed
form
is prcscnted
within
I I%
power
that shows that the short-circuit
ratio
power
is below
7%
power
for L less than or equal to one.
short-circuit
power
Sor the case of
RLC
loads,
the shorr-circuit
greatcl- than the cast oiLC
<If I<(‘ loads.
of
The
LC loads is much
loads. In the cast
power
for
is prexntcd
the dynamic
Icss than that of the case of KC
that
el~or for a
factor- A. An expression
to dynamic
is
of a
a capacitor
line.
powcr
simulations
wide range of the matching
the short-circuit
pow’er
a IossIcss transmission
same as that of a CMOS
by
line
01
is in the middle,
loads but less than ths cast
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“Line-to-Ground
VLSI:
295
131
“Simple
and Three-Dimensional
SC-5
1”
l,aw
C\IOS
/Et% .loir,riii,
o/’
Nm 2. pp. 5X4
Corporation.
New York.