Download PowerPoint

CERN Technical Training 2005
ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics
Basic Analog Design
Giovanni Anelli
15 March 2005
Part I
ELEC 2005
Outline – Part I
• The MOS transistor: quick summary
 The MOS transistor
 DC characteristics
 Important formulas
• Basic analog building blocks
ELEC 2005
Giovanni Anelli - CERN
2
The (N)-MOS transistor
y
z
x
DRAIN
GATE
SUBSTRATE
SOURCE
ELEC 2005
iDS  gm  vGS
Transconductance
Giovanni Anelli - CERN
3
Linear and Saturation regions
S
G
n+
S
n+
ELEC 2005
D
n+
G
D
n+
LINEAR REGION (Low VDS):
Electrons (in light blue) are attracted to
the SiO2 – Si Interface. A conductive
channel is created between source and
drain. We have a Voltage Controlled
Resistor (VCR).
SATURATION REGION (High VDS):
When the drain voltage is high enough
the electrons near the drain are
insufficiently attracted by the gate, and
the channel is pinched off. We have a
Voltage Controlled Current Source
(VCCS).
Giovanni Anelli - CERN
4
Voltage and Current sources
RS
Vout
+
Voltage source. Ideal if RS = 0.
V
Iout
I
ELEC 2005
RS
Current source. Ideal if RS = ∞.
Giovanni Anelli - CERN
5
Drain current vs Drain voltage
This is a real device measurement !
3.0E-05
2.5E-05
IDS [ A ]
2.0E-05
Output conductance
1.5E-05
Saturation region (VCCS)
1.0E-05
@ three
different VGS
5.0E-06
Linear region (VCR)
0.0E+00
0.0
0.5
1.0
1.5
2.0
2.5
VDS [ V ]
ELEC 2005
Giovanni Anelli - CERN
6
Drain current vs Gate voltage
This is also a measurement, same device.
2.E-03
red
1.E-03
1.E-03
8.E-04
6.E-04
4.E-04
Linear region (green) and
saturation region (red)
Subthreshold
region
IDS [ A ]
1.E-03
High field
(vertical and
longitudinal)
effects
2.E-04
0.E+00
-0.4
green
0.0
0.4
0.8
1.2
1.6
2.0
2.4
VGS [ V ]
ELEC 2005
Giovanni Anelli - CERN
7
Log(IDS) vs VGS
Exactly same measurement as before, but semi log scale
1.E-02
red
1.E-03
green
1.E-04
IDS [ A ]
1.E-05
1.E-06
WEAK
INVERSION
THRESHOLD
VOLTAGE
1.E-07
STRONG
INVERSION
1.E-08
1.E-09
SUBTHRESHOLD
SLOPE
1.E-10
1.E-11
LEAKAGE
CURRENT
ELEC 2005
1.E-12
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
VGS [ V ]
Giovanni Anelli - CERN
8
A few equations in saturation
Weak Inversion
IDS  ID0
W
e
L
VGS
n t
IDS
IDS
gm 

VGS n t
Strong Inversion
IDS


( VGS  VT )2
2n
n
ELEC 2005
gm  gmb
 1.x
gm
gm 
gmb 
 IDS
 VBS
 IDS 

 ( VGS  VT )  2 IDS
 VGS n
n
   Cox
Giovanni Anelli - CERN
W
L
Cox 
 SiO2
t ox
9
Output conductance
3.0E-05
IDS
ID’
ID
2.5E-05
IDS [ A ]
2.0E-05
DV
Dashed lines:
ideal behavior
1.5E-05
1.0E-05
DI
5.0E-06
VD
0.0E+00
0.0
0.5
1.0
1.5
2.0
2.5
VDS [ V ]
S
Gout
G
D
n+
n+
DL
L
ELEC 2005
VD’
VDS
DI
ID
DL



DV D V L - DL
The non-zero output
conductance is related to a
phenomenon called
channel length modulation
Giovanni Anelli - CERN
10
Output conductance / resistance
Drain-to-source current in saturation
IDS


( VGS  VT )2 (1  VDS )  IDS _ SAT  (1  VDS )
2n
Output conductance
gout  gds
IDS

   IDS _ SAT
VDS
Remember:  is
proportional to 1/L
Output resistance
1
1
r0 

gds   IDS _ SAT
ELEC 2005
Giovanni Anelli - CERN
11
gm / ID vs log (ID / W)
30
Weak Inversion (W.I.)
25
W.I.
gm 
gm / I D
20
IDS
n t
gm
1

ID
n t
15
Strong Inversion (S.I.)
10
S.I.
5
0
1E-11
1E-09
1E-07
1E-05

gm  2 IDS
n
gm
 1
 2
ID
n IDS
1E-03
ID / W
Moderate Inversion (M.I.): No Equations
ELEC 2005
Giovanni Anelli - CERN
12
Outline – Part I
• The MOS transistor: quick summary
• Basic analog building blocks







ELEC 2005
Small-signal equivalent circuit
Common-Source Stage
Common-Gate Stage
Cascode Stage
Differential Pair
Current Mirrors
Differential Pair + Current Mirror
Giovanni Anelli - CERN
13
Our first circuit!
iDS 
VDD
VDD  VDS
RD
RD
VDS
VGS
For a small signal:
vds = -vgs*gm*RD
ELEC 2005
Giovanni Anelli - CERN
14
Small-signal equivalent circuit
G
D
gm v gs
Valid only at very
low frequencies
r0
No bulk effect
S
IDS


( VGS  VT )2 (1  VDS )
2n
ids  gm  v gs
ELEC 2005
This equation fixes the bias point
This equation defines the small signal behavior
Giovanni Anelli - CERN
15
Small-signal equivalent circuit
D
G
Cgd
gm v gs
Cgs
gmb vbs
Cgb
C sb
S
B
ELEC 2005
Giovanni Anelli - CERN
r0
Cdb
And we should also add the
series resistances…
16
Common-Source Stage (CSS)
VDD
DC characteristic
RD
Vout
Small signal gain G 
Vout
Vin
ro
Small signal gain
(with channel length
modulation)

 VDD  R D
( Vin  VT )2
2n
Vout

 R D ( Vin  VT )  gmR D
Vin
n
G  gm r0 // R D   gm
r0R D
r0  R D
Small signal model in saturation
The above results
could also have been
obtained directly from
the small signal model
ELEC 2005
G
D
+
Vin
gmVin
S
Giovanni Anelli - CERN
Vout
RD
ro
17
CSS Simulation - DC
3
2.5E-02
W = 100 m
2.5
Vout [ V ]
2
1.5E-02
1.5
1.0E-02
1
Vout
Ids
gm
0.5
5.0E-03
0
IDS [ A ], g m [ S ]
2.0E-02
L = 0.5 m
R = 100 W
The maximum
small signal
gain is only
–1.8!!!
0.0E+00
0
0.5
1
1.5
2
2.5
Vin [ V ]
ELEC 2005
Giovanni Anelli - CERN
18
CSS Simulation - DC
Increasing the value of the load resistor to 1 kW we have
3
1.2E-02
1.0E-02
2
8.0E-03
1.5
6.0E-03
1
4.0E-03
0.5
2.0E-03
0
0.0E+00
0
0.5
1
1.5
2
IDS [ A ], g m [ S ]
2.5
Vout [ V ]
W = 100 m
Vout
Ids
gm
L = 0.5 m
R = 1000 W
The maximum
small signal
gain is now
–9.6.
2.5
Vin [ V ]
ELEC 2005
Giovanni Anelli - CERN
19
0.905
1.774
0.903
1.772
1.77
0.901
1.768
0.899
1.766
0.897
1.764
0.895
1.762
0
2
4
6
8
R = 1000 W
Ids [ mA ]
Vin [ V ]
CSS Simulation – Small Signal
10
0.905
0.738
0.903
0.736
0.734
0.901
0.732
0.899
0.73
0.897
0.728
0.895
0.726
0
2
4
6
8
We inject at the input a
sinusoid with frequency 1 kHz,
peak to peak amplitude 1 mV
AND dc offset = 0.9 V.
The DC offset is important to
be in the right bias point.
V out [ V ]
Vin [ V ]
t [ ms ]
gm = 9.6 mS
The input voltage is converted
in a current by the transistor
and then in a voltage again by
the resistor.
10
t [ ms ]
ELEC 2005
Giovanni Anelli - CERN
20
CSS with Current Source load
To increase the gain, we can use the output resistance of a transistor.
T2 provides the DC current bias to T1, and has a high output
impedance. The bias current is determined by Vb.
VDD
Vb
r01  r02
1
Small signal G  g r // r   g 


g

m1 01
02
m1
m1
1
1
r01  r02
gain

r02 r01
T2
Vout
Vin
T1
This solution gives a much higher gain than the
other solutions and has a better DC output swing,
since Vout_max = VDD – VDS2_sat and Vout_min = VDS1_sat.
VDS _ sat 
VGS  VT
n
N.B. The DC output level here is not well defined, we will need a
feedback loop.
ELEC 2005
Giovanni Anelli - CERN
21
Diode-connected transistor
Impedance seen looking into the source.
VDD
G, D
ro
gmVGS
ix
S
+
vx
ix
gmbVBS
B
+
vx
v
ix  gm v x  x  gmb v x
r0
R
vx
1
1


1 gm  gmb
ix
gm  gmb 
r0
We have three resistances in parallel: 1/gm, 1/gmb and r0. This is true
also if the gate is connected to a fixed potential which is not VDD.
ELEC 2005
Giovanni Anelli - CERN
22
Common-Gate Stage (CGS)
In the Common-Source Stage the input signal is applied to the gate. We can also
apply it to the source, obtaining what is called a Common-Gate Stage (CGS)
Not considering channel length
modulation (r0) for the moment
VDD
RD
vout  (gm  gmb )  vin  RD
Vout
Vb
G
Vin
v out
 gm  gmb   R D  n  gm  R D
vin
The gain is slightly higher than the one of a CSS, since we apply the signal to
the source.
ELEC 2005
Giovanni Anelli - CERN
23
Common-Gate Stage (CGS)
Let’s now calculate the input impedance and the gain considering r0:
VDD
RD
With the small-signal equivalent
circuit we can easily obtain
1
z in 
RD
r0
gm  gmb 
1
r0
Vout
Vb
v out
vin

 RD
z in
v out R D
G

vin
z in
Vin
The input impedance of a CGS is relatively low, but this only if the load
impedance (RD) is low.
ELEC 2005
Giovanni Anelli - CERN
24
Cascode Stage (CascS)
The “cascade” of a Common-Source Stage (V-I converter) and of a
Common-Gate Stage is called a “Cascode”.
VDD
r01
v out   vin  gm1 
RD
Vout
1
r01 
 RD
RD
r02
gm2  gmb 2 
REMINDER
I
1
r02
R1
R2
T2
Vb
v out
G
 gm1R D
vin
r01
Vin
T1
ELEC 2005
I1 
R2
I
R1  R 2
The gain is practically the same as in the
case of a Common-Source Stage.
Giovanni Anelli - CERN
25
Cascode Stage Output Resistance
One nice property of the cascode stage can be discovered looking at the
resistance seen in the drain of T2.
Rout
With the small-signal equivalent circuit we can obtain
Vb
Vin
T2
R out _ CascS  r01  r02  gm2  gmb 2   r01r02  gm2  gmb 2   r01r02
T1
Compared to a Common-Source Stage, the output
impedance is “boosted” by a factor (gm2 + gmb2) r02.
The disadvantage of the cascode configuration is that the minimum
output voltage is now the sum of the saturation voltages of T1 and T2.
It must therefore be used with care in low voltage circuits.
ELEC 2005
Giovanni Anelli - CERN
26
CascS with current source load
To fully profit from the high output impedance of the cascode stage, it
seems natural to load it with a high impedance load, like a current source.
R out _ CascS  r01  r02  gm2  gmb 2   r01r02
VDD
Vb1
R out  R out _ CascS // r03
T3
Vout
Vb2
Vin
G  gm1R out
T2
T1
If r03 is not high enough, we can use the cascode
principle to boost the output impedance of the
current source as well.
N.B. Remember that the DC output level here is not
well defined, and that we will need a feedback loop.
ELEC 2005
Giovanni Anelli - CERN
27
Single-Ended vs Differential
A single-ended signal is defined as a signal measured with respect to a
fixed potential (usually, ground).
A differential signal is defined as a signal measured between two nodes
which have equal and opposite signal excursions. The “center” level in
differential signals is called the Common-Mode (CM) level.
The most important advantage of differential signals over single-ended
signals is the much higher immunity to “environmental” noise.
As an example, let’s suppose to have a disturbance on the power supply.
VDD
VDD
RD
Vout_SE
ELEC 2005
RD
Vout +
Giovanni Anelli - CERN
RD
Vout -
28
Single-Ended vs Differential
The Common-Mode disturbances disappear in the differential output.
Vdd
Vout_SE = Vout +
Vout Vout_diff
Vout _ diff  Vout   Vout 
ELEC 2005
Giovanni Anelli - CERN
29
Differential Pair (DP)
VDD
Vin1
RD
Vin,CM
RD
Vout1
Vin2
Vout2
Vout2
Vin1
Vin2
ISS
Vout,CM
Vout1
t
The current source has a very important function,
since it makes the sum of the currents in the two
ISS
v

V

R

branches (I1 + I2= ISS) independent from the input
out,CM
DD
D
2
common mode voltage.
The output common mode voltage is then given by:
ELEC 2005
Giovanni Anelli - CERN
30
Differential Pair (DP)
VDD
VDD
Vout1
RD
Vout2
RD
Vout1
Vout2
Vin1
VDD - RD ISS
Vin1 - Vin2
Vin2
Vout1 - Vout2
RD ISS
ISS
N.B. The small signal gain is
the slope of this plot
ELEC 2005
Giovanni Anelli - CERN
Vin1 - Vin2
- RD ISS
31
DP small signal gain
This circuit can be easily analyzed assuming that the point P is AC
grounded. In this case, we have 2 Common-Source Stages!
VDD
RD
Vout1
Vin1
vout2  gm  RD  vin2
Vout2
T1
Vb
ELEC 2005
vout1  gm  RD  vin1
RD
T2
P
T3
Vin2
vout1  vout2  gm  RD  vin1  vin2 
G  gmRD
Giovanni Anelli - CERN
32
Differential Pair with MOS loads
To analyze the two circuits we can now make use of the half-circuit
concept and profit from all the results obtained up to now.
 1

g
G   gmN 
// r0N // r0P    mN
gmP
 gmP

G   gmN r0N // r0P 
VDD
T3
VDD
T4
T1
T2
Vin2
Vin1
ISS
ELEC 2005
T3
T4
Vb
Vout2
Vout1
Vout2
Vout1
Vin1
Vb
T1
T2
Vin2
ISS
Giovanni Anelli - CERN
33
Cascode Differential Pair
And, of course, the gain can be boosted using common-gate stages.
VDD
Vb3
T7
T8
Vb3
Vb2
T5
T6
Vb2
Vout1
Vb1
Vin1
T3
T4
T1
T2
G   gm1gm3r03r01 // gm5r05r07 
Vout2
Cascode stages were used a
lot in the past, when the
supply voltages were
relatively high (few volts).
Vin2
In deep submicron
technologies they are used
with more care.
Vb1
ISS
ELEC 2005
Giovanni Anelli - CERN
34
Current mirror (CM)
We suppose that all the transistors have the same , Cox and VT.
 is the same if the transistors have the same L
VDD
IREF
I1
WR
LR
W1
L1
W1
1   1VDS1 
L
I1  IREF  1
WR
1   R VDSR 
LR
GND
To have an exact replica of the reference current, we have to make the
transistor identical AND they must have the same VDS. When this is not
possible, choosing long devices reduces the effect of .
Precise current ratios can be obtained playing with the ratio between
the transistor widths (not the lengths!).
ELEC 2005
Giovanni Anelli - CERN
35
Cascode current mirror (CCM)
VG3 must be fixed so that VD1 = VD2.
I3
VDD
IREF
VD3
W3
L3
VG3
VD1
VD2
W1
L1
W2
L2
Making L1 = L2 and therefore having 1 = 2,
we obtain that the current I3 practically does
not depend on the voltage VD3. Of course, all
the devices must be in saturation (the circuit
is not suitable for low voltage applications).
W2 / L2
I3  IREF 
W1 / L1
DVD2
DVD3

gm3  gmb 3   r03
GND
Important: L3 can be different from L1 and L2.
How do we fix VG3 so that VD1 = VD2 ?
ELEC 2005
Giovanni Anelli - CERN
36
Cascode current mirror (CCM)
VDD
Transistor 4 does the job here!
Transistors 1 & 2 decide the current ratio.
IREF
I3
Transistors 3 & 4 fix the bias VD1 = VD2.
VD3
W4
L4
W3
L3
VD1
VD2
W1
L1
W2
L2
GND
These results are valid even if transistors 3 &
4 suffer from body effect.
W2 / L2
I3  IREF 
W1 / L1
W2 / L2 W3 / L3

W1 / L1 W4 / L 4
The problem of this current mirror is that VD3 > VDS3 + VGS2.
ELEC 2005
Giovanni Anelli - CERN
37
Differential Pair + Active CM
Current mirrors can also process a signal, and they can therefore be used
as active elements. A differential pair with an active current mirror is also
called a differential pair with active load. The current mirror here has also
the important role to make a differential to single-end conversion!
VDD
Common Mode Analysis
T3
vin,CM _ min  VGS1  VDS _ SAT 5
T4
Vout
T2
T1
Vin
vin,CM _ max  min VDD  VGS 3  VT1 , VDD 
Maximum output excursion
vout _ min  VDS _ SAT 2  VDS _ SAT 5
Vb
ELEC 2005
T5
vout _ max  VDD  VDS _ SAT 4
Giovanni Anelli - CERN
38
Differential Pair + Active CM
Let’s now calculate the small-signal behavior, neglecting the bulk effect for
simplicity. The circuit is NOT symmetric, and therefore we can not use the halfcircuit principle here. As a first approximation, we can consider the common
sources of the input transistors as a virtual ground. The small-signal gain G can
be seen as the product of the total transconductance of the stage and of the
output resistance.
G  Gm  R out
VDD
T3
iout  gm1
T4
iout
Vout
+
v in
2
T1
T2

v in
2
iout
Gm 
 gm1,2
vin
R out  r02 // r04
G  gm1,2 r02 // r04 
ISS
ELEC 2005
vin 
v 
   gm2 in   gm1,2  vin
2 
2 
Giovanni Anelli - CERN
39
CERN Technical Training 2005
ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics
Basic Analog Design
Giovanni Anelli
15 March 2005
Part I
ELEC 2005