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CERN Technical Training 2005
ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics
Basic Analog Design
Giovanni Anelli
15 March 2005
Part II
ELEC 2005
Outline – Part II
•
•
•
•
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Noise in analog ICs
Matching in analog ICs
Operational Amplifier design examples
Analog design methodology
Giovanni Anelli - CERN
2
Thermal noise in passive components
Thermal noise is caused by the random thermally excited
vibration of the charge carriers in a conductor.
vn2
R
Power spectral density [ V 2 / Hz ]
vn2  4kTR  f
[ V2 ]
in2
4kT
i 
 f
R
2
n
R
[ A2 ]
There are no sources of noise in ideal capacitors or
inductors. In practice, real components have parasitic
resistance that does display thermal noise!
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Noise sources in MOS transistors
Channel thermal noise: due to the random thermal motion of the
carriers in the channel
1/f noise: due to the random trapping and detrapping of mobile
carriers in the traps located at the Si-SiO2 interface and within the
gate oxide.
Bulk resistance thermal noise: due to the distributed substrate
resistance.
Gate resistance thermal noise: due to the resistance of the
polysilicon gate and of the interconnections.
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Noise in circuits
To be independent from the gain of a given system, we use the concept
of input-referred noise. This allows comparing easily the noise
performance of different circuits (with different gains), and calculating
easily the Signal-to-Noise Ratio (SNR).
At the input of our linear two-port circuit, we use two noise generator
(one noise voltage source and one noise current source) to represent
the noise of the system regardless the impedance at the input of the
circuit and of the source driving the circuit.
v n2 ,in
Noisy
circuit
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v n2,out
in2 ,in
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Noiseless
circuit
v n2,out
5
Input-referred voltage noise
The MOS transistor is represented by its small-signal equivalent circuit.
We can refer the noise sources inside the MOS transistor to the input,
obtaining an input-referred voltage noise.
2
2
Ka
gmb
vin
1
1
 4kTng
 2
 4kTR G  4kT 2 RB

f
gm Cox WL f
gm
Channel thermal
noise
1/f noise
Gate resistance
thermal noise
Bulk resistance
thermal noise
g ideally varies from 1/2 (w.i.) to 2/3 (s.i.)
Ka = 1/f noise parameter, technology dependent
Usually, the first two terms are the most important
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N-channel noise spectra
W = 2 mm, IDS = 0.5 mA, VDS = 0.8 V, VBS = 0 V
1.E-07
L = 0.36um
L = 0.5um
Noise [ V/sqrt(Hz) ]
L = 0.64um
L = 0.78um
L = 1.2um
1.E-08
1.E-09
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency [ Hz ]
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Noise in a DP + Active CM
VDD
VDD
2I
2I
2
vin
2
vin
v 2tot
i2out
i2out
2
2
vload
vload
v 2tot
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2

 2
g
m _ load
2
  vload
 2  vin  2   2
 g

 m _ in 
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Noise in a DP + Active CM
VDD
v
2
tot _ 1 / f
2
1  K a _ load   load  Lin 
 2 2
  1
 f
2


Cox WinLin f 
K a _ in  in  Lload 
K a _ in
2I
v
2
tot
Make WinLin big and Lload  Lin
v 2tot _ th

W

load  
2

 L load
 4kTng 
 1
W
W
in  
2inCox in I 
 L in
Lin 



  f



W
W
Make     
 L in  L load
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Outline – Part II
•
•
•
•
ELEC 2005
Noise in analog ICs
Matching in analog ICs
Operational Amplifier design examples
Analog design methodology
Giovanni Anelli - CERN
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The importance of matching
Yield of an N-bit flash Analog-to-Digital converter as a function of the
comparator mismatch
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Relative & absolute mismatch
Mismatch occurs for all IC components (resistors,
capacitors, bipolar and MOS transistors)
D1
L1
D2
L2
L
L2  L1
 200 
[%]
L
L2  L1
D  D1  D2 [m]
Relative mismatch
Absolute mismatch
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Mismatch in MOS transistors
Mismatch in physical parameters (Na, , Tox) and layout dimensions (W, L)
gives origin to mismatch in electrical parameters (VT, b and therefore ID)
Mismatch in
Na, , Tox
+
Mismatch in
W and L
IDS1
VGS1
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IDS 
Parameter
mismatch
IDS2
b
( VGS  VT )2
2n
VGS2
Giovanni Anelli - CERN
I mismatch
and V offset
VT and
b
b
VGS and
ID
ID
13
The golden rule: Bigger is better!
Random effects “average out” better if the area is bigger. Therefore,
for a given parameter P, we expect something like
 ΔP 
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AP
WL
 ΔP
AP
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1/ WL [1/m]
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Expected mismatch
Usually in a pair of identical transistors the two most important
parameter subject to mismatch are the threshold voltage Vth and the
current factor b
 Vth 
A Vth
 b / b 
WL
AVth / tox ~ 1 mV·m / nm
Ab ~ 1 to 3 %·m
Ab
WL
From the
literature
Mismatch can be treated as another source of noise. As in the noise
case, different “mismatch” sources can be grouped into one adding
the variances (not the standard deviations)
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Differential pair mismatch
The two transistors have the same drain current
σ ΔVGS  
2
Vth
 I

 
 b / b 
 gm

2
22
σ VGS [mV ] 20
18
16
14
σ Δb/b  1.4 %
σ VT  4.5 mV
12
10
8
2I
σ VT
6
4
2
0
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
INVERSIONI.C.
COEFFICIENT
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Current mirror mismatch
The two transistors have the same gate voltage
σ ΔI/I  
σ ΔI/I [%]
2
b / b
 gm


 Vth 
 I

14
σ Δb/b  1.4 %
12
σ VT  4.5 mV
10
I
2
8
6
4
σ b / b
2
0
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
I.C.
INVERSION
COEFFICIENT
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Offset of a DP + Active CM
RANDOM OFFSET (WORST CASE)
VDD
v off  VT1,2 
2I
 b1,2 b3,4 gm3,4






V
T 3,4 

gm1,2  b1,2
b 3,4
I

I
SYSTEMATIC OFFSET
v off
Vin
T1
T2
Vout
T3
The difference in the drain voltages
of T1 and T2 gives origin a difference
in the DC currents in the two
branches.
“COMMON MODE” OFFSET
T4
Due to mismatches in the transistors,
a common mode signal at the input
gives a non zero output voltage
signal.
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Outline – Part II
• Noise in analog ICs
• Matching in analog ICs
• Operational Amplifier design examples





Op Amp application examples
Single-Stage Op Amps
Two-Stage Op Amps
Fully Differential Op Amps
Feedback and frequency compensation
• Analog design methodology
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The ideal op amp
An op amp is basically a voltage-controlled voltage source
Vin +
Rout
Rin
A0 (vin  vin )
Vout
Vin -
The op amp is ideal when
A0 = Rin = ∞, Rout = 0
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Op amp application examples
NONINVERTING
CONFIGURATION
INVERTING
CONFIGURATION
R2
Vin
Vout
Vin
Vout
R1
R2
R1
BUFFER
Vin
Vout = Vin
R2
G
R1
R
G  1 2
R1
G1
The above equations are valid only if the gain A0 of the op amp is very high!
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Single-stage Op Amp
VDD
T7
T8
T5
T6
Vout
Vb1
T3
T4
T1
T2
Vin
ISS
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Vb1
The differential pair + active current
mirror scheme we have already seen is a
single stage op amp. Several different
solutions can be adopted to make a
Single-stage amplifier. If high gains are
needed, we can use, for example,
cascode structures.
With single-stage amplifiers it is difficult
to obtain at the same time high gain and
voltage excursion, especially when
other characteristics are also required,
such as speed and/or precision.
Two-stage configurations in this sense
are better, since they decouple the gain
and voltage swing requirements.
Giovanni Anelli - CERN
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Two-stage Op Amp
G  gm2 (r02 // r04 )  gm5 (r05 // r08 )
VDD
T6
T7
T8
Vout
Vin -
T1
T2
Vin +
Rb
The second stage is
very often a CSS,
since this allows the
maximum voltage
swing.
The output voltage
swing in this case is
VDD - |2VDS_SAT|
T5
T3
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T4
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Two-stage Op Amp
G  gm1,2 (r01,2 // r03 ,4 )  gm6 (r06 // r08 )
VDD
T3
T4
T5
Vb
T1
T6
T2
Vin
Vout
ISS
T7
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In this case we kept the
differential behavior of
the first stage, and is the
current mirror T7-T8
which does the
differential-to-single
ended conversion. The
output is still a CSS.
T8
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Fully Differential Op Amp
G  gm1,2 (r01,2 // r03 ,4 )  gm5,6 (r05 ,6 // r07 ,8 )
VDD
T3
T4
T5
Vb1
T1
T6
T2
Vin
Vout1
Vout2
ISS
Vb2
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T7
T8
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Fully Differential Op Amp
G   gm1,2 (gm3,4  gmb 3,4 )r03 ,4r01,2 ) // (gm5,6  gmb 5,6 )r05 ,6r07 ,8 )  gm9,10 r09 ,10 // r011,12 
VDD
Vb3
T7
T8
Vb3
Vb2
T5
T6
Vb2
To increase the
gain, we can again
make use, in the
first stage, of
cascode structures.
T9
T10
Vb1
Vout1
T3
T4
T1
T2
Vb1
Vout2
Vin
Vb4
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T11
ISS
T12
Giovanni Anelli - CERN
Vb4
26
Feedback
Vin
+
e
Vout
A(s)
G(s) 
F(s)
vout (s)
A(s)
A(s)


vin (s) 1  A(s)F(s) 1  Gloop (s)
• A(s) is the open loop transfer function
• F(s) is the feedback network transfer function
• G(s) is the closed loop transfer function
• A(s)F(s) is the loop gain
• If the feedback is negative, the loop gain is negative
• For |Gloop(s)| >> 1, we have that
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G(s)  
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1
F(s)
27
Properties of negative feedback
Negative feedback reduces substantially the gain of a circuit, but it
improves several other characteristics:
• Gain desensitization: the open loop transfer function is generally
dependent on many varying quantities, given by the active components
in the circuit. Using a passive feedback network, we can reduce the
dependence of the gain variation on the variations of the open loop
transfer function.
dG dA
1

G
A 1  Gloop
• Reduction of nonlinear distortion
• Reduction or increase (depending on the feedback topology) of the
input and output impedances by a factor 1-Gloop.
• Increase of the bandwidth
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Bode diagrams
Many interesting properties of the frequency behavior of a given circuit can be
obtained plotting the module and the phase of the Transfer Function as a
function of the frequency. These plots are called Bode diagrams. In the general
case, a transfer function is given by the ratio between two polynomials. The
roots of the numerator polynomial are called zeros, the roots of the
denominator polynomials are called poles. For example, in the case of a
low-pass filter with RC = 1 ms, the Bode diagrams look like:
20
0
Phase [degrees]
20log 10 |H(s)| [dB]
-10
0
-20
-40
-20
-30
-40
-50
-60
-70
-80
-60
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
-90
1.E+00
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency [rad/s]
Frequency [rad/s]
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1.E+01
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Bandwidth increase with feedback
|G(s)|
Vin
+
A(s)
Vout
A ( s) 
A0
A0
s
1
w0
A0
1

1  fA 0 f
-f
w0
w
w0(1+fA0)
GBWP
A0
1  fA 0
A ( s)
G(s) 

s
1  f  A ( s) 1 
(1  fA 0 )w0
The gain-bandwidth product does not change with feedback!
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Stability Criteria
Vin
+
A(s)
Vout
|fA(s)|
GREEN: STABLE
RED: UNSTABLE
-f
G(s) 
A(s)
1  f  A(s)
w1
|fA(jw1)| = 1
w
 fA(s)
1  f  A(s)  0
Barkhausen’s Criteria
w1
w
- 90
- 180
 fA(jw1) = - 180
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Phase Margin
We have seen that to ensure stability |fA(s)| must be smaller than 1 before
 fA(s) reaches - 180. But, in fact, to avoid oscillation and ringing, we
must have a bit more margin.
We define phase margin (PM) the quantity 180 +  fA(w1), where w1 is the
gain crossover frequency. It can be shown that, to have a stable system
with no ringing (for small signals) we must have PM > 60. If we want to
have an amplifier which responds to a large input step without ringing,
PM must be even higher.
|fA(s)|
 fA(s)
w1
|fA(s)|
w
SMALL PM
w
 fA(s)
- 180
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w1
w
LARGE PM
w
- 180
Giovanni Anelli - CERN
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Frequency Compensation
Single-pole op-amps
|fA(s)|
would always be stable
(the phase does not go
below - 90). But a typical
op-amp circuit always
contains several poles
(and zeros!). These opamps can easily be
unstable, and they need
 fA(s)
therefore to be
compensated. This is
generally done lowering
the frequency of the
- 90
dominant pole.
- 180
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RED: BEFORE COMPENSATION
GREEN: AFTER COMPENSATION
Giovanni Anelli - CERN
w1
w1
33
Outline – Part II
•
•
•
•
ELEC 2005
Noise in analog ICs
Matching in analog ICs
Operational Amplifier design examples
Analog design methodology
Giovanni Anelli - CERN
34
Analog design methodology
Define specifications
Extract schematic from
layout
Choose architecture
Layout Versus Schematic
(LVS) check
Simulate schematic
Extracted schematic
simulations
Simulate schematic varying
T, VDD, process parameters
BLOCK DONE!
Masks layout
In a complex design,
this will be repeated
for every block of the
design hierarchy.
Design Rules Check (DRC)
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Analog design trade-offs
NOISE
LINEARITY
POWER
DISSIPATION
GAIN
ANALOG
DESIGN
OCTAGON
INPUT/OUTPUT
IMPEDANCE
VOLTAGE
SWINGS
SPEED
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SUPPLY
VOLTAGE
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Bibliography
Books:
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.
P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001.
R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.
R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990.
D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.
Y. Tsividis, Operation and Modeling of The MOS Transistor, 2nd edition, McGraw-Hill, 1999.
K. R. Laker and W. M. C. Sansen, Design of Analog Integrated Circuits and Systems, McGraw-Hill, 1994.
C. D. Motchenbacher and J. A. Connelly, Low Noise Electronic System Design, John Wiley and Sons, 1993.
A. L. McWhorter, Semiconductor Surface Physics, University Pennsylvania Press, 1956, pp. 207-227.
Z.Y. Chang and W.M.C. Sansen, Low-noise wide-band amplifiers in bipolar and CMOS technologies, Kluwer Academic Publishers, 1991.
Papers:
K. R. Lakshmikumar, R. A. Hadaway and M. A. Copeland, "Characterization and Modeling of Mismatch in MOS Transistors for Precision
Analog Design", IEEE Journal of Solid-State Circuits (JSSC), vol. 21, no. 6, December 1986, pp. 1057-1066.
Behzad Razavi, “CMOS Technology Characterization for Analog and RF Design", JSSC, vol. 34, no. 3, March 1999, p. 268.
M.J.M. Pelgrom et al., “Matching Properties of MOS Transistors”, IEEE JSSC, vol. 24, no. 10, 1989, p. 1433.
M.J.M. Pelgrom et al., “A 25-Ms/s 8-bit CMOS A/D Converter for Embedded Application”, IEEE JSSC, vol. 29, no. 8, Aug. 1994 , pp. 879-886.
R. W. Gregor, "On the Relationship Between Topography and Transistor Matching in an Analog CMOS Technology", IEEE Transactions on
Electron Devices, vol. 39, no. 2, February 1992, pp. 275-282.
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CERN Technical Training 2005
ELEC-2005
Electronics in High Energy Physics
Spring term: Integrated circuits and VLSI technology for physics
Basic Analog Design
Giovanni Anelli
15 March 2005
Part II
ELEC 2005