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International Journal of Review in Electronics & Communication Engineering (IJRECE)
Volume 2 - Issue 3 June 2014
REDUCTION OF POWER DISSIPATION &
PARAMETER VARIATION IN VLSI
CIRCUITS FOR SOC
A.Rajesh, Assoc. Prof.,ECE, ACE Engineering College,Hyd., [email protected]
Dr.B.L.Raju,Principal, ACE Engineering College,Hyd, [email protected]
Dr.K.Chenna Kesava Reddy,Ex-Principal, JNTU College Of Engineering, Jagityal,
Abstract — During the desktop PC design era VLSI
design efforts have focused primarily on optimizing
speed to realize computationally intensive real-time
functions such as video compression, gaming, graphics
etc. As a result, we have semiconductor ICs that
successfully integrated various complex signal
processing modules and graphical processing units to
meet our computation and entertainment demands.
While wireless devices are rapidly making their way to
the consumer electronics market, a key design
constraint for portable operation namely the total
power consumption of the device must be considered.
Reducing the total power consumption in such systems
is important since it is desirable to maximize the run
time with minimum requirements on size, battery life
and weight allocated to batteries. So the most
important factor to consider while designing SOC for
portable devices is 'low power design. The Power
dissipation affects are Performance, Reliability
Packaging, Cost, and Portability
Scaling of technology node increases power-density
more than expected. CMOS technology beyond 65nm
node represents a real challenge for any sort of voltage
and frequency scaling. Low cost always continues to
drive higher levels of integration. Modern System-onChip demand for more power. In both logic and
memory, Static power is growing really fast and
Dynamic power kind of grows. Overall power is
dramatically increasing. If the semiconductor
integration continue to follow Moore's Law, the power
density inside the chips will reach far higher than the
rocket nozzle.
Power dissipation is the main constrain when it
comes to Portability. The mobile device consumer
demands more features and extended battery life at a
lower cost. About 70% of users demand longer talk and
stand-by time as primary mobile phone feature. Top
3G requirement for operators is power efficiency.
Customers want smaller & sleeker mobile devices. This
requires high levels of Silicon integration in advanced
processes, but advanced processes have inherently
higher leakage current. So there is a need to bother
more on reducing leakage current to reduce power
consumption
This paper reviews various strategies and
methodologies for designing low power circuits and
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systems. It describes the many issues facing designers at
architectural, logic, circuit and device levels and presents some
of the techniques that have been proposed to overcome these
difficulties. The article concludes with the future challenges
that must be met to design low power, high performance
systems.
Keywords: Power dissipation, Dynamic power, Static
power, VLSI
I. INTRODUCTION
In the past, the major concerns of the VLSI designer were area,
performance, cost and reliability; power consideration was mostly
of only secondary importance. In recent years, however, this has
begun to change and, increasingly, power is being given
comparable weight to area and speed considerations. Perhaps the
primary driving factor has been the remarkable success and growth
of the class of personal computing devices (portable desktops,
audio- and video-based multimedia products) and wireless
communications systems (personal digital assistants and personal
communicators) which demand high-speed computation and
complex functionality with low power consumption .The
advantage of utilizing a combination of low-power components in
conjunction with low-power design techniques is more valuable
now than ever before. Requirements for lower power consumption
continue to increase significantly as components become batterypowered, smaller and require more functionality.
The motivations for reducing power consumption differ
application to application. In the class of micro-powered battery
operated portable applications such as cell phones, the goal is to
keep the battery lifetime and weight reasonable and packaging cost
low. For high performance portable computers such as laptop the
goal is to reduce the power dissipation of the electronics portion of
the system to a point which is about half of the total power
dissipation. Finally for the high performance non battery operated
system such as workstations the overall goal of power
minimization is to reduce the system cost while ensuring long term
device reliability. For such high performance systems, process
technology has driven power to the fore front to all factors in such
designs. At process nodes below 100 nm technology, power
consumption due to leakage has joined switching activity as a
primary power management concern. The basic low-power design
techniques, such as clock gating for reducing dynamic power, or
multiple voltage thresholds (multi-Vt) to decrease leakage current,
are well-established and supported by existing tools.
The need for low power has caused a major paradigm shift
where power dissipation has become as important a consideration
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as performance and area.
As these devices are battery operated, battery life
is of primary concern.
Commercial successes of these products depend
on weight, cost and battery life.
Low power design methodology is very important
to make them commercially viable.
II. SOURCES OF POWER DISSIPATION
The power dissipation in circuit can be classified into
three categories as described below.
Ptotal = Pdynamic+Pshort-circuit+Pleakage +Pstatic
1. Dynamic power consumption: Due to logic transitions
causing logic gates to charge/discharge load capacitance
.Dynamic (Switching) Power Consumption (Pdynamic):
Charging and discharging capacitors
2. Short-circuit current: In a CMOS logic P-branch and
N-branch are momentarily shorted as logic gate changes
state resulting in short circuit power dissipation.
Short Circuit Power Consumption (Pshort-circuit):
Short circuit path between supply rails during
switching
3. Leakage current: This is the power dissipation that
occurs when the system is in standby mode or not
powered. There are many sources of leakage current in
MOSFET. Diode leakages around transistors and n-wells,
Subthreshold Leakage, Gate Leakage, Tunnel Currents etc.
Increasing 20 times for each new fabrication technology.
Leakage Power Consumption
(Pleakage): Leaking diodes and
transistors
Static Power Consumption (Pstatic)
Dynamic power
Current flow from VDD to GND when logic
transition occurs
Static power
Current flow from VDD to GND regardless of
logic transition
Energy is ½ CV2 per transition
Short-Circuit Current (10-15% of active power)
When both p and n transistors turn on during signal
transition
Subthreshold Leakage (dominates wh en inactive)
Transistors don’t turn off completely
Diode Leakage (negligible)
Parasitic source and drain diodes leak to substrate
Dynamic power:
Switching power
Short-circuit
power
Glitch power
Static power DC
current
Leakage current
Weak inversion current
Drain-induced barrier lowering
Gate-induced drain leakage
Channel
punch-through
Oxide leakage tunneling Hot
carrier injection
Dynamic power is required to charge and disch arge load
capacitances when transistors switch.
One cycle involves a rising and falling output.
On rising output, charge Q = CVDD is r equired
On falling output, charge is dumped to GND
This repeats Tfsw timesover an interval of T
VDD iDD(t)
C
f
sw
Figure 2: CMOS Inverter
P
dynamic
1Ti
T0
VDD
VT
DD
( t )V dt
DD
T
iDD ( t )dt
DD
0
Tf sw CVDD T
CVDD2 fs w
Figure 1: CMOS Inverter driving another Inverter
Primary Components:
Capacitor Charging (85-90% of active power)
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Static power
Leakage power introduction
Short-channel effect
Leakage power components
(VDD-Vt) design space
Total power management
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Static Power
DC current
Pseudo NMOS logic
Figure 5: MOSFET Cross sectional View
Scaling makes the leakage power worse
Transistor scaling road map
Figure.3: Pseudo NMOS NOR & NAND gate
DC current
Steady current flow from VD D to GND
Either logic value is 0 or 1 dep ending on the
logic structure when the output is 0
Drain leakage increases as Vt decreases to meet frequency
demands leading to excessive leakage power
Figure 6: Graph for Drain Leakage Vs Vt
Figure 4: CMOS,NMOS Depletion/ Enhancement Inverter
Leakage current
A transistor switch is a resistiv e-capacitive network
between the power supply and GND
Non-ideal off-state characteristics (a finite resistance)
makes current draw even the n the transistor is in the cutoff state
Leakage Power Introduction:
Long channel (L>1um): negligible
leakage Short channel (L>180nm,
Tox>30Å):
subthresholdleakage
Very
short
channel
(L>90nm,
Tox>20Å): subthreshold+gateleakage
Nanoscaled
(L<90nm,
Tox<20Å):
subthreshold+gate+BTBTleakage
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Short-Channel Effect:
Vtroll-off
Vtis reduced with decreasing L
Increasing dependence of Vton L threaten the future
technology scaling due to variations
WID D2D
Novel device techniques:
Overcome the drawback of the short-channel
MOSFET
Super-halo doping
Multiple gate device
Planar devices’Lmin= 10nm
Silicon-on-insulator (SOI) device
Leakage Power Components:
Reverse bias PN junction leakage
Minority carrier diffusion/drift near the edge of the
depletion region Election-hole pair generation in the
depletion region of the reverse bias junction
Subthresholdleakage current:
Weak inversion current
The most significant leakage in DSM technologies
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A MOSFET operates in the weak inversion
(subthreshold) region when VGS< Vt
Source to drain current conduction is primarily
due to diffusion of the carriers
Ioff is when VGS= 0, is affected by the Vt, W, L,
depletion width beneath the channel area,
channel/surface doping profiles, drain/source
junction depths, gate oxide thickness, VDD, and
junction temperature.
Drain-induced barrier lowering (DIBL):
The depth of the junction depletion layer increases
as the reverse bias voltage across the drain-tobody PN junction increases
Increased drain-to-body reverse bias voltage
enhances the short-channel effects and lowers Vt
A significant portion of the subthresholdleakage
current of a DSM MOSFET can be due to DIBL
at high reverse bias voltage across the drain-tobody PN junction
Oxide leakage tunneling:
_When the gate of an NMOS (PMOS) device is positively
(negatively) biased, the electrons (holes) in the inverted
channel can tunnel to the poly gate
concerns
a) Packaging and Cooling costs.
b)Digital noise immunity,
c)Battery life (in portable systems)
d)Environmental concerns
Power minimization in both active and standby modes
Dynamic power in active mode
Subthresholdleakage power in standby mode
Glitch Power Dissipation:
•
Glitches are temporary changes in the value of the
output – unnecessary transitions
• They are caused due to the skew in the input signals to
a gate
• Glitch power dissipation accounts for 15% – 20 % of
the global power
• Basic contributes of hazards to power dissipation are
– Hazard generation
– Hazard propagation
Reducing Power
Switching power activity*½ CV2*frequency
o
Figure7: CMOS Inverter driving another Inverter
(VDD-Vt) Design Space:
Two key transistor scaling schemes
CE (Constant electric field) scaling
All the horizontal and vertical dimensions are
scaled with the power supply to maintain
constant electric fields throughout the device
Standard scaling methodology in industry in a
30% reduction (1/S=0.7) of all dimensions per
generation Supply and threshold voltages are
scaled down by the
factor of 1/S
Current, gate capacitances, and delay also
scaled by 1/S
Results in 50% improvement in frequency
Improvement gradually degrades due to
interconnect dominant delay
CV (Constant voltage) scaling
Maintains a constant power supply
Gradually scales the gate oxide thickness to
slow down the growth of fields in the oxide
Total Power Management
Power Management matter in System on Chip due to following
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(Ignoring short-circuit and leakage
currents)
Reduce activity
o
Clock and function gating
o Reduce spurious logic glitches
Reduce switched capacitance C
Different logic styles (logic, pass
transistor, dynamic)
o Careful transistor sizing
o Tighter layout
o Segmented structures
Reduce supply voltage V
o Quadratic savings in energy per transition
– BIG effect
o
o But circuit delay is reduced
Reduce frequency
o Doesn’t save energy just reduces rate at
which it is consumed
o Some saving in battery life from reduction
in current draw
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Low-Power Design Circuits:
MTCMOS
Dual Vt
Dual Vt domino logic
Adaptive Body Bias
Transistor stacking
Figure 8: Combinational Circuit
P = 1/2 .CL.Vdd . (Vdd – Vmin) ;
o Vmin : min voltage swing at the output
Glitch power dissipation is dependent on
Output load
Input pattern
Input slope
Hazard generation can be reduced by gate sizing and
path balancing techniques
Hazard propagation can be reduced by using less number
of inverters which tend to amplify and propagate glitches
III. THE VARIOUS WAYS OF LOW POWER

DESIGN
Reduce dynamic power
– a: clock gating, sleep mode
– C: small transistors (esp. on clock), short
wires
– VDD: lowest suitable voltage
– f: lowest suitable frequency

–Selectively use ratioed circuits
– Selectively use low Vt devices
– Leakage reduction: stacked devices, body
bias, low temperature
Reducing Power
Dynamic Power Suppression
Dynamic/Switching power is due to charging and discharging
of load capacitors driven by the circuit. Supply voltage scaling has
been the most adopted approach to power optimization, since it
normally yields considerable power savings due to the quadratic
dependence of switching/dynamic power PSwitching on supply
voltage VDD. However lowering the supply voltage affects circuit
speed which is the major short-coming of this approach. So both
design and technological solutions must be applied to compensate
the decrease in circuit performance introduced by reduced voltage.
Some of the techniques often used to reduce dynamic power are
described below.
Adiabatic Circuits
In adiabatic circuits instead of dissipating the power is reused.
By externally controlling the length and shape of signal transitions
energy spent to flip a bit can be reduced to very small values. Since
diodes are thermodynamically irreversiblethey are not used in the
design of Adiabatic Logic. MOSFETs should not be turned ON
when there is significant potential difference between source and
drain. And should not be turnoffthen there is a significant current
flowing through the Device. In the adiabatic circuit shown above
initially, f and /f at Vdd/2, P at Gnd, and /P at Vdd. On valid input,
the pass gate is turned on by gradually swinging P and /P. Rails f
and /f "split", gradually swinging to Vdd and Gnd.
2
Switching power activity*½ CV *frequency
o (Ignoring short-circuit and leakage
currents)
Reduce activity
o Clock and function gating
o Reduce spurious logic glitches
Reduce switched capacitance C
o Different logic styles (logic, pass
transistor, dynamic)
o Careful transistor sizing
o Tighter layout
o Segmented structures
Reduce supply voltage V
o Quadratic savings in energy per transition
– BIG effect
o But circuit delay is reduced
Reduce frequency
o Doesn’t save energy just reduces rate at
which it is consumed
o Some saving in battery life from reduction
in current draw
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Figure 9: .Charge Recovery Logic
As soon as output is sampled, pass gate is turned off. Internal
node is restored by gradually swinging f and /f back to Vdd/2.Once
the device is on energy transfer takes place in a controlled manner
so that there is no potential drop across the device.
IV. LOGIC DESIGN FOR LOW POWER
Choices between static versus dynamic topologies,
conventional CMOS versus pass-transistor logic styles and
synchronous versus asynchronous timing styles have to be made
during the design of a circuit. In static CMOS circuits, the
component of power due to short circuit current is about the 10%
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of the total power consumption. However, in dynamic
circuits we don't come across this problem, since there is
no any direct dc path from supply voltage to ground. Only
in domino-logic circuits there is such a path, in order to
reduce sharing, hence there is a small amount of shortcircuit power dissipation.
Figure 12: Logic Remapping for Low Power
Standby Mode Leakage Suppression:Static/Leakage power, originates from substrate currents and
subthreshold leakages. For technologies 1 µm and above ,
PSwitching was predominant. However for deep-submicron
processes below 180nm, PLeakage becomes dominant factor.
Leakage power is a major concern in recent technologies, as it
impacts battery lifetime. CMOS technology has been extremely
power-efficient when transistors are not switching or in stand-by
mode, and system designers expect low leakage from CMOS
chips.
To meet leakage power constraints, multiple-threshold and
variable threshold circuit techniques are often used. In multiplethreshold CMOS, the process provides two different threshold
transitors. Low-threshold are employed on speed-critical subcircuits and ther are fast and leaky. High-threshold transistors are
slower but exhibit low sub-threshold leakage, and they are
employed in noncritical/slow paths of the chip. As more transistors
become timing-critical multiple-threshold techniques tend to lose
effectiveness.
Figure 10: Static NOR & Dynamic NOR circuits
Similarly we can use pass transsitor logic to exploit
reduced swing to lower power (e.g., reduced bit-line swing
in memory).
Logic Level Power Optimization:During logic optimization for low power, technology
parameters such as supply voltage are fixed, and the
degrees of freedom are in selecting the functionality and
sizing the gates.Path equalization with buffer insertion is
one of the techniques which ensures that signal
propagation from inputs to outputs of a logic network
follows paths of similar length to overcome glitches. When
paths are equalized, most gates have aligned transitions at
their inputs, thereby minimizing spurious switching
activity/glitches (which is created by misaligned input
transitions
Variable Body Biasing:
Variable-threshold circuits dynamically control the threshold
voltage of transistors through substrate biasing and hence
overcome shortcoming associated with multi-threshold design.
When a variable-threshold circuit is in standby, the substrate of
NMOS transistors is negatively biased, and their threshold
increases because of the body-bias effect. Similarly the substrate of
PMOS transistors is biased by positive body bias to increase their
Vt in stand-by.
Variable-threshold circuits can, in principle, solve the
quiescent/static leakage problem, but they require control circuits
that modulate substrate voltage in stand-by. Fast and accurate
body-bias control with control circuit is quite challenging, and
requires carefully designed closed-loop control. When the circuit is
in standby mode the bulk/body of
both PMOS and NMOS are biased by third supply voltage to
increase the Vt of the MOSFET as shown in the Figure. However
during normal operation they are switched back to reduce the Vt.
Figure.13: Variable Body Biasing
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Sleep Transistors:
Sleep Transistors are High Vt transistors connected in
series with low Vt logic as shown below .When the main
circuit consisting of Low Vt devices are ON the sleep
transistors are also ON resulting in normal operation of the
circuit. When the circuit is in Standby mode even High Vt
transistors are OFF. Since High Vt devices appear in series
with Low Vt circuit the leakage current is determined by
High Vt devices and is very low. So the net static power
dissipation is reduced.
Figure 14: Circuit Design with Sleep Transistors
Dynamic Threshold MOS:
In dynamic threshold CMOS (DTMOS), the threshold
voltage is altered dynamically to suit the operating state of
the circuit. A high threshold voltage in the standby mode
gives low leakage current, while a low threshold voltage
allows for higher current drives in the active mode of
operation. Dynamic threshold CMOS can be achieved by
tying the gate and body together. The supply voltage of
DTMOS is limited by the diode built-in potential in bulk
silicon technology. The pn diode between source and body
should be reverse biased. Hence, this technique is only
suitable for ultralow voltage (0.6V and below) circuits in
bulk CMOS.
Figure 15: DTMOS Circuit
Short Circuit Power Suppression
Short-circuit power, is caused by the short circuit
currents that arise when pairs of PMOS/NMOS transistors
are conducting simultaneously. In static CMOS circuits,
short-circuit path exists for direct current flow from VDD
to ground, when VTn< Vin< VDD-|VTp|
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Figure .12 Short Circuit Power in CMOS Circuits
One way to reduce short circuit power is to keep the input and
output rise/fall times the same. If Vdd < Vtn + |Vtp| then shortcircuit power can be eliminated. If the load capacitance is very
large, the output fall time is larger than the input rise time.
The drain-source voltage of the PMOS transistor is 0.Hence the
short-circuit power will be 0. If the load capacitance is very
small,the output fall time is smaller than the input rise time. The
drain-source voltage of the PMOS transistor is close to VDD
during most of the transition period. Hence the short-circuit power
will be very large.
REFERENCES
[1] Strategies & Methodologies for Low Power VLSI Designs: A
Review at International Journal of Advances in Engineering &
Technology, May 2011.©IJAET ISSN: 2231-1963
[2] A Report on Low Power VLSI Circuit Design at International
journal of Engineering Research Management Technology
ISSN:2348-4039& Volume-1,Issue-1
[3] Low Power System Design Jan. 2007 Naehyuck
Chan,EECS/CSE Seoul National University
[4] Design Technologies for Low Power VLSI-Massoud Pedram
,Department of EE-Systems- University of Southern
California.,Los Angeles , CA 90089
[5] POWER REDUCTION IN MODERN VLSI CIRCUITS – A
REVIEW at International Journal of Students Research in
Technology & Management .Vol 1 (04), August 2013, ISSN
2321-2543, pg 361-369
[6] Website: http://vlsicad.ucsd.edu/courses/ece260b-w05-power
Consumption.
[7] Krste
Asanovic
[email protected]
http://www.cag.lcs.mit.edu/6.893-f2000/
[8] www.nlc-nc.ca/obj/s4/f2/dsk1/tape4/PQDD_0016/NQ5348
3.pdf
9.users.ece.utexas.edu/~adnan/vlsi-05backup/lec18LowPowe r.ppt
[9] vada.skku.ac.kr/Research/project/lp-pedram.pdf
[10] www.cpdee.ufmg.br/~frank/lectures/SillowPower2.
[11] www.cmosvlsi.com/lect18.pdf
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