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Group 2 ECE 164.02 Introduction and Mid-semester report on the Electronic Design Project: Gpbs Optoelectronic Link A Report Presented to Dr. Brooke and Dr. Jokerst By Tyler Helble Ungtae Lee Ian Phillipi Andrew Tupper March 26, 2004 Duke University Department of Electrical and Computer Engineering 1 Table of Contents page # 1. Abstract ________________________________________________________3 2. Introduction _____________________________________________________4 2.1 General Background ________________________________________4 2.2 Board Elements ___________________________________________5 2.3 Project Overview __________________________________________6 2.4 Division of Labor __________________________________________7 2.5 Time Management _________________________________________8 3. Optical Link Budget ______________________________________________8 3.1 General Idea ______________________________________________8 3.2 Initial Power Calculations ____________________________________9 3.3 VCSEL Calculations _______________________________________ 10 3.4 Four Corners Analysis ______________________________________ 11 3.5 Fiber Attenuation Calculations _______________________________ 12 3.6 Photodetector calculations & “four corners” analysis ______________ 12 3.7 Final Optical Link Budget___________________________________ 13 4. Financial Budget _________________________________________________15 5. Board Layout & Design ___________________________________________16 5.1 Design Tools ______________________________________________16 5.2 Transceiver Schematic ______________________________________16 5.3 Receiver Schematic _________________________________________17 5.4 PCB Layout _______________________________________________18 6. Delays and Problems______________________________________________21 7. Receiver Test Board Results _______________________________________23 8. Conclusion and Future Plans ______________________________________ 25 8. References ______________________________________________________26 2 1. Abstract As modern communication demands become increasingly dependent on the rate and quality of data transfer, engineers have invested interest in developing reliable high speed data communication. This design class tries to meet these demands by developing a Gigabit Ethernet optoelectronic link that will operate at a frequency of 1.25 GHz. In addition, the device should be suitable for long range communication by working well under attenuation. In order to develop Gbps Ethernet, a transceiver board was designed that can both send data (using VCSEL laser technology) and receive optical data (using photodiode technology). The design process involved calculating the laser bias currents necessary to drive the device while filtering and shielding circuits in order to reduce noise to the system. In addition, the design had to be laid out in a compact way in order to reduce the chance of creating transmission lines that could ruin the sensitive signals. The completed design was ordered on a PCB board and the system components were soldered to the board. Eventually the board will be tested under attenuation and with varying design layouts, revealing the importance of component placement, shielding, and filtering in the overall success of the optoelectronic link. 3 2. Introduction 2.1 General Background Gbps Ethernet is the most recent type of network based on a long standing history of previous Ethernet standards dating back to 1973 [1]. In 1973 Xerox Corporation’s Research Center in Palo Alto developed a bus topology LAN. As the technology developed, Xerox built a 2.94Mbps CSMA/CD system in 1976 that connected 100 personal workstations on a 1 kilometer cable [2]. As the need for this technology became more demanding, Xerox teamed with Digital Equipment Corporation and Intel in 1980 to develop a standard for 10Mbps Ethernet [2]. This technology was dubbed DIX Ethernet (representing the initials of all three companies involved). DIX was the basis for the current standard IEEE 802.3 Ethernet. As transfer speeds increased, approvals were set for 10Base5 (1983), 10Base2 (1986), 10BaseT (1991), 10BaseF (1994), 100 Mbps (1995), and finally the current standard of Gigabit Ethernet in 1998 [1]. Although the type of cable has changed over the years for transferring high speed data, Ethernet has retained its name from ether, the single coaxial cable used in Xerox’s original Ethernet system. [1] The IEEE 802.3z standard is the current standard for 1.25Gbps Ethernet [6]. The design of our optoelectronic link will follow the IEEE 802.3z standard. The basic architecture of this standard can be seen in the figure below. 802.3z standard Gbps Ethernet Arcitecture [5] (Fig 2.1.1) In order to design, build, and test our optoelectronic link in compliance with 802.3z standards, several important limitations must be taken into account. The laser 4 may transmit at either 850 nm or 1300 nm wavelengths. In addition, two types of fibers are supported in the standard: single-mode optical fiber (SMF) with 10μm core diameter or multimode optical fiber (MMF) with 50μm core diameter or 62.5μm core diameter [6]. Furthermore, we have been asked that our optoelectronic link contain a single power supply, meet spacing for use of an Asante duplex connector, and meet the eye safety spec [6]. 2.2 Board Elements The optoelectronic board is essentially the Physical Media Dependent (PMD) component of the 802.3z architecture. The main active components of the board are the Vertical Cavity Surface Emitting Laser (VCSEL) used to transmit data and the Photodiode (PD) used to receive data. The VCSEL is driven by the Maxim MAX3287 Transmitter, which takes a differential input and converts the signal into a current. The current from the MAX3287 allows the VCSEL to produce high and low powerpulses of 850nm light. The light from the TX board is transmitted to the RX board via optical fiber. The Photo Diode on the TX board detects the incoming light and generates small current signals. The MAX 3266 Trans-impedance Amplifier (TIA) chip creates a differential voltage from the incoming PD current. The MAX 3264 creates a digital signal from the incoming analog voltage signal of the TIA by converting the signal to ones and zeroes (high and low voltages). The VCSEL is composed of layers of mirrors that are a result of semiconductors sandwiched with varying composition. The mirrors are arranged in a way to reflect light back into a central cavity. Since the mirrors only reflect a narrow range of wavelengths, the combined mirrors ensure only one wavelength of light is emitted from the VCSEL. This light leaves the VCSEL vertically in a cylindrical beam from the fabricated wafer [3]. The Standard Optek VSCEL [13] (Fig.2.2.1) VCSEL has certain advantages over edge-emitting lasers, and in general the VCSEL has cheap production costs, low threshold currents, minimum 5 temperature sensitivity, and the ability to switch from high to low light at high speeds [3]. VCSELs come packaged as connectorized and unconnectorized. Connectorized VCSELs are embedded in a casing that protects the laser and ensures proper alignment with the optical fiber. There are several important parameters associated with the performance of a VCSEL. Slope Efficiency reveals the ratio of outgoing light power to incoming current (MicroWatts/mA). The threshold current is the minimum current necessary to drive the laser “on”. In general, VCSELs with high slope efficiencies and low threshold currents are suited best for our needs [3]. The Photodiode (PD) receives the incoming light generated from the VCSEL. Since considerable light energy is lost through the transmission fiber, it is essential for the PD to recognize low power pulses of light. The responsivity value reveals the amps of current generated from the input of light power (in watts). In addition, it is important to note the capacitance of the PD and the receiver area. The capacitance influences the response time necessary to detect high and low light, which is essential to note for high speed communication [4]. The receiver area is the area that the PD is able to detect light over. A larger receiver area means that your alignment does not have to be perfect for the PD to work. The ideal PD for the optoelectronic link has a high responsivity, low capacitance, and a large receiver area [4]. Photodiodes are fabricated using P-type Typical Photodiodes [7] (Fig 2.2.2) and N-type semiconductors sandwiched together with an intrinsic layer between them. For this reason they are usually referred to as PIN semiconductors. 2.3 Project Overview The purpose of this project is to design, fabricate and test an optoelectronic link that complies with the Optical Gigabit Ethernet standard IEEE 802.3z. Over the course of five months, a team of four students will generate and follow a project management plan, subdividing tasks according to expertise and resource management. Gantt charts will be used for time management purposes and weekly presentations will keep the group up to date and on schedule. The design and fabrication must be completed on a $350 budget provided by the Duke ECE department in conjunction with the ECE 164 design 6 course. Ideally the team will formulate a Bill of Materials (BOM) that uses the minimum expenditures in order to simulate the design techniques of mass producing a product. In order to familiarize the group with the techniques of design and fabrication, a transceiver board without optical technology was constructed by the group. Using this as a basis, the group was able to gain the knowledge necessary to integrate optics into the system. The design of the optoelectronic link was initially designed and laid out using PCB Express software. After critiquing the design several times, the board was ordered through PCB Express. After soldering the components to the board and testing, a second design is scheduled to try and eliminate design errors found in the group’s initial design. The group will use the Agilent Infinium oscilloscope for visual inspection of the eye with and without attenuation. The oscilloscope will also be used on conjunction with the probe to troubleshoot our transceiver board. The Tektronix GTS1250 pattern generator and Tektronix gigaBERT 1400 will be used to check the Bit Error Rate with several data patterns. The group should have a working optoelectronic transceiver that complies with 802.3z standards by April 13, 2004. 2.4 Division of Labor In order to ensure each project task is completed successfully, we organized our group so that each member heads a division. Each member is expected to be responsible for the timely completion of their division, in addition to ensuring that all members gain experience by contributing resources to their division. In this way, all group members will become familiar with the many disciplines of the optoelectronic project, while those with the matching skills can make sure each subproject is completed on time. The table below shows our division of labor: Group Member Duties Andrew Tupper Transmitter/Receiver PCB design, Practice Board Testing Ian Transmitter/Receiver schematic design, Optical Link Budget Tyler Helble Parts/Vendor Management, Webmaster, Soldering Ungtae Lee Report Editor, Testing optoelectronic transceiver Division of Labor (Table 2.4.1) 7 2.5 Time Management A Gantt chart was created in order to subdivide tasks and keep the project organized and on schedule. The project steps were organized in a way to maximize working time by limiting the amount of downtime when parts and PCBs are on order. To date, the project is on track for the final report to be completed by April 21st. Our main hang-ups have been waiting for supplies to arrive (more detail in section 6. Delays and Problems). The evaluation board testing ran over due to the fact that a needed etching tool was delivered late. Our biggest set back has been locating and ordering VCSELs, a crucial element necessary for the completed design. Aside from soldering the VCSEL, our first transceiver board has been constructed, and our receiver should be fully tested by March 26th. 3. The Optical Link Budget 3.1 General Idea There are a number of things to be considered when designing a Gbps Ethernet compliant IEEE 802.3 optical link. The most important of these is selecting the correct parts, including the VCSEL, photodiode, and potentiometers. An optical link budget is a set of calculations based upon important parameters of the VCSEL and photodiode (for example slope efficiency or responsivity) that allow us to tell if the parts we have chosen will function properly in our circuit before they are actually installed. Below is a schematic diagram of all the dynamic parts involved in building the Gbps Ethernet device. 8 Schematic Diagram of the Optical Link Budget [5] (Fig 3.1.1) The MAX3287 laser driver drives the VCSEL above a threshold current. The VCSEL then outputs laser light through a fiber into the photodetector. The photodetector receives the optical power in the form of laser light and converts it to current. This current drives the MAX3266 TIA. The TIA is a transimpedance amplifier, which means that it converts current to voltage. The TIA takes the current and converts it into differential output voltage. Then the MAX3264 limiting amplifier converts the signal into a digital signal which can be processed by a computer. The laser driver, TIA, and limiting amplifier have been chosen for us, so our job is to determine the best VCSEL/photodiode combination for our system. 3.2 Initial Power Calculations To begin with we need to know what value of Pmax we want the VCSEL to output. Our value of Pmax will be determined from the Eye Safe limit [6], which is defined as the maximum amount of laser light that the VCSEL can output and still be safe to the eye. We will use 1 mW as the maximum [5]. The next step in creating our link budget is to compute the value of Pmin. To compute Pmin we use the following equation: Pmin = (Pmax)(10-(ER/10)) 9 (Eq. 3.2.1) Where Pmax is 1 mW and ER (extinction ratio) is 9 dB. These values can be obtained from the 802.3 standard on page 1038 [8]. Plugging in these values, we compute Pmin to be 0.1259 mW. 3.3 VCSEL Calculations The graph on the next page is the VCSEL output power vs. input current (L-I) characteristic. This curve shows how a VCSEL’s output power will respond to changes in input current. From this curve we determine all equations necessary to run the four corners analysis, which will give us the operating current range of a VCSEL. Since the VCSEL L-I curve is roughly a straight line with a slope η (slope efficiency) and an xintercept of Ith, the drive currents of the VCSEL is calculated from the optical output power using the equation of a straight line: I = [P/ η] + Ith (Eq. 3.3.1) VSCEL output power vs. input current curve [5] (Fig 3.3.1) In order to operate at speed the VCSEL must be biased above threshold. To calculate the maximum VCSEL drive current we use the equation: Imax = [Pmax / η] + Ith 10 (Eq. 3.3.2) To calculate the minimum VCSEL current we use a similar equation, but simply replace Pmax with Pmin. Imin = [Pmin / η] + Ith (Eq. 3.3.3) From the values of Imin and Imax, values for the bias current, Ibias, and the modulation current, Imod, of the VCSEL can be determined. The bias current is the current that lies halfway between Pmax and Pmin. The modulation current swings between Imin and Imax. Ibias = (Imax + Imin )/2 (Eq. 3.3.4) Imod = (Imax - Imin ) (Eq. 3.3.5) 3.4 Four Corners Analysis The VCSEL parameters generally have values that are min, typical, and max. A four corners analysis is performed using the max value. This is to assure that the VCSEL will function under the worst case scenario. Only one VCSEL, Lasermate TLC-P85A416 is used. Below are the parameters and four corners analysis of the Lasermate VCSEL. Lasermate TLC-P85A416-3 VCSEL Parameters Parameter Threshold Current (mA) Slope Efficiency (mW/mA) TLC-P85A416-3 parameters [10] (Table 3.4.1) Symbol Ith η MIN 1.80 0.03 TYP 1.80 0.11 MAX 2.60 0.15 Four corners analysis VCSEL Current Requirements I_th (mA) eta (mW/mA) I_tot,MAX (mA) 1.80 0.03 35.1333 1.80 0.15 8.4667 2.60 0.03 35.9333 2.60 0.15 9.2667 Four corner analysis on Lasermate VCSEL [10] (Table 3.4.2) 11 I_tot,MIN (mA) 5.9964 2.6393 6.7964 3.4393 I_bias (mA) 20.5649 5.5530 21.3649 6.3530 I_mod (mA) 29.1369 5.8274 29.1369 5.8274 3.5 Fiber Attenuation Calculations The VCSEL outputs laser light into the fiber which is connected to the PD. Unfortunately, as the laser light travels through the fiber it attenuates (loses power) so that the actual amount of laser light that reaches the PD is only a fraction of what the VCSEL actually output. In order to perform a proper four corners analysis of our photodiodes we need to know the full range of powers that will reach the PD. To calculate this range we use the following equation: (Eq. 6) Pat PD = (PVCSELout)(10-(fiber loss/10)) Where Pmax and Pmin will both separately be plugged into PVCSELout and the value for fiber loss, 7.5 dB, is obtained from the 802.3 specification on page 1039 [8]. Plugging in the values of Pmax = 1mW and Pmin = 0.1259 mW into Equation 6, we compute a range of 0.02240 - .1778 mW. 3.6 Photodetector calculations & “four corners” analysis The input power to the PD is multiplied by the PD responsivity to calculate the output current from the PD into the TIA. (Eq. 7) IPD = R * (Pat PD) In most cases PDs have maximum and minimum values of responsivity so a four corners analysis must be undertaken to assure that at no point the PD is overdriving or underdriving the TIA. In our case though both the photodetectors that we chose have only a typical value for responsivity. So a full four corners analysis is unavailable. Hamamatsu S7912 Photodetector Parameters Parameter Responsivity (A/W) Capacitance (pF) Aperture Size (mm) Dark Current (pA) Hamamatsu PD parameters [9] (Table 3.6.1) MIN 12 TYP 0.47 0.85 0.20 1.00 MAX 100.00 OSI – FCI-125G006HR Photodetector Parameters Parameter Responsivity (A/W) Capacitance (pF) Aperture Size (mm) Dark Current (pA) OSI PD parameters [11] (Table 3.6.2) MIN TYP 0.36 0.66 0.15 30.00 MAX 500.00 Four corners analysis OSI Photodetector Output Currents R (A/W) I_o,MAX (mA) I_o, MIN (mA) 0.36 0.064018059 0.008059396 0.36 0.064018059 0.008059396 OSI Four Corners (Table 3.6.3) Hamamatsu Photodetector Output Currents R (A/W) I_o,MAX (mA) I_o, MIN (mA) 0.47 0.083579132 0.010521989 0.47 0.083579132 0.010521989 Hamamatsu Four Corners (Table 3.6.4) Finally, capacitance is an important parameter to check when picking a photodiode. The capacitance determines the time delay of the signal and it should be minimized to produce high speed signals. Based on the specifications for the MAX3266 TIA [12], a typical good capacitance value is around 0.85 pF or lower. 3.7 Final Optical Link Budget Ith (mA) DC Bias of laser (mA) Slope Efficiency (mW/mA) Modulation Current of Tx (mA) Range of Power Output (mW) Range of Power Output (w/Loss) (mW) Responsivity of OSI PD (A/W) Responsivity of Hamamatsu PD (A/W) Range of Current from OSI PD (uA) Range of Current from Hamamatsu PD (uA) Hamamatsu connectorized? (y/n) OSI connectorized? (y/n) Lasermate TLC - P85A416-3 1.8 21.3649 0.11 29.1369 0.1259 - 1.0 0.02240 - .1778 0.36 0.47 8.1 - 64.0 10.5 - 83.6 No Yes Optical Link Budget (Table 3.7.1) 13 Based upon our optical link budget and the limited availability of products we use the lasermate VCSEL. For the photodiode, we use the Hamamatsu PD, because that is the only PD available to us. Based on the optical link budget we determine that both PDs work in our circuit. In addition, we decide to order the connectorized OSI PD for implementation in our circuit. Group 2 Gantt Chart - 1 Gbps Optical Ethernet Jan Project Steps: 1-10 11-20 Feb 21-31 1-10 11-20 background research (Jan 8 - Apr 13) test eval board (Feb 5 - Feb 11) Optical link budget (Feb 10 - Feb 19) Choose parts (Feb 11 - Feb 19) Order VCSEL/PD's (Feb 19 -Feb 25) Build test board (Feb 13 - Feb 20) Design Schematic (Feb 15 - Feb 22) Board design (Feb 19 - March 2) Design review (Feb 26 - March 4) Order PCB's (March 5- March 14) Spring Break (March 5 - March 14) Construct Board (March 14 - March 21) Testing/Troubleshooting (March 21 - March 28) Design Modifications (April 1 - April 7) Build second board (April 7 - April 13) Final report (April13 - April 21) Test (Feb 5) Midterm Report (March 19) Final Report (April 21) Event Projected Time Completed Overdue Gantt Chart (Table 3.7.2) 14 M arch 21-29 1-10 11-20 April 21-31 1-10 11-20 21-30 4. Financial Budget Each group is allocated $350.00 for the entire project. At this point, we have spent a total of $174.27. This included all resistors, capacitors, Potentiometers, PCB Board, PD’s and the VSCEL. We expect to buy more VSCELs, SMA connectors, and power connectors in the near future and expect the total cost of the budget to approach the maximum. The table below shows the breakdown of our financial budget. Financial Budget Part # Part Description Vendor Cost/ piece Quanitiy Total Cost PCB Board 311-100CCTND 311-115CCTND 311-24.9CCTND 399-1158-1ND PCB Board RES 100 OHM 1/8W 1% 0805 SMD RES 115 OHM 1/8W 1% 0805 SMD RES 24.9 OHM 1/8W 1% 0805 SMD CAP 10000PF 50V CERMAIC X7R 0805 POT 50K 6MM CERM SQ ST TOP POT 2K 6MM CERM SQ ST TOP Digi-Key $51.00 1 $51.00 Digi-Key $0.10 10 $1.00 Digi-Key $0.10 10 $1.00 Digi-Key $0.10 10 $1.00 Digi-Key $0.05 10 $0.50 Digi-Key $0.84 5 $4.20 Digi-Key $0.99 5 $4.95 Lasermate Hamamatsu $53.00 $21.31 1 2 $53.00 $42.62 $15.00 $174.27 CT6P503-ND CT6R202-ND TLCP85A416-3 Lasermate VSCEL S7912 Hamamatsu PD Shipping Total Financial Budget (Table 4.1) 15 5. Board Layout & Design 5.1 Design Tools Both circuit design and printed circuit board layout was performed using a free CAD software package available for download at www.expresspcb.com. While this software is not nearly as sophisticated as some of the more advanced design tools available, expresspcb.com offers a quick turnaround and very reasonable prices. This comprehensive package includes two key software tools; ExpressSCH version 4.1.2 and ExpressPCB version 4.1.2. ExpressSCH is a relatively simple schematic design program that made the process of designing the transmitter and receiver schematics, as well as reviewing and editing them, a relatively simple one. ExpressPCB is a printed circuit board layout program that shares a similarly simple interface with ExpressSCH. ExpressPCB includes some very useful features that significantly streamline the process of laying out a board. Probably the most useful feature is the ability to link a PCB layout to a schematic diagram. Once the schematics for the transmitter and receiver had been completed and checked for errors, they could be linked to the PCB layout so that ExpressPCB could automatically check to make sure that the nodes in the schematic lined up with the board layout. The actual designs will be discussed below. 5.2 Transmitter Schematic The transmitter and receiver schematics, which can be seen in the figures below, were designed independently of each other in order to simplify and expedite the process. The transmitter consists of the MAX3287 LAN laser driver, a Lasermate VCSEL and a number of passive components. This transmitter schematic was essentially derived from the schematic included in the Maxim MAX3287 Evaluation Kit. The final schematic was created by omitting a feedback loop photodiode, as well as a bias adjustment PNP transistor that were present in the evaluation design. The filter observed in the transmitter schematic was added in an attempt to eliminate some of the interference problems that arise with the use of a noisy power supply. Potentiometers were also added so that fine adjustments could be made to the operating region of the VCSEL. It should 16 be noted that, while the transmitter and receiver schematics were drawn separately, they Transmitter Schematic (Fig. 5.2.1) are actually two parts of the same circuit, as they share a common power supply and their ground plains are inductively coupled. 5.3 Receiver Schematic The receiver circuit consists of the Maxim MAX3266 transimpedance amplifier, the Maxim MAX3264 limiting amplifier, a Hamamatsu photodiode and a number of passive components. The receiver schematic was derived by making a few minor modifications to the schematic used to construct the test receiver board. Because the test board was electrical instead of optical, the electrical inputs were replaced by the photodiode. A power filter was also added to the original design, again in an attempt to eliminate interference on the power supply lines. Once more, while the two schematics are shown separately here, they are in fact two parts to the same circuit. The V CC pin in these schematics refers the same 5V power supply. While the two circuits do have their own ground plane, the ground planes are inductively coupled. Separate ground planes were created as another effort to eliminate cross talk between the transmitter and receiver. 17 Receiver Schematic (Fig. 5.3.1) 5.4 PCB Layout Once the transmitter and receiver schematic diagrams had been completed and checked for errors, they were linked to a printed circuit board layout in ExpressPCB 4.1.2. Unfortunately designing a PCB in this case is not as simple as just trying to fit all of the components onto the board. The goal of the transceiver is to be able to send a digital signal at the rate of 1 gigabyte per second. A 1 Gbps data signal requires about a 500MHz square wave. In order to send a decent square wave it’s generally a good idea to include the first five harmonics, meaning that in order to send a good 1 Gbps data signal, it’s necessary to deal with frequencies in the 2.5GHz range. At this frequency traces should be kept less than 4mm in length in order to prevent the traces from acting as transmission lines. Furthermore, significant effort was spent attempting to make the designs for the transmitter and receiver as symmetric as possible, particularly when dealing with differential signals. By keeping differential signals in close proximity and contained within symmetric traces, any interference picked up on those traces should be common to both sides of the differential pair, thus making it relatively easy to eliminate this noise when the signal is processed. Finally, 90 degree turns were avoided at all costs in high frequency traces, in order to prevent signal reflection. 18 The transceiver (transmitter and receiver) PCB ended up being very compact, not only because of the desire to shorten traces to prevent transmission line problems, but also because it enabled two separate layouts to be included on each board. This made it possible to attempt two different designs on the same board. The first design, which can be seen in the figure below, is the primary layout. It should be noticed that all traces except the power supply turn in only 45 degree angles. Hopefully this will prevent any signal reflection in the high frequency connections. Also notice the large red line Primary PCB layout (Fig. 5.4.1) surrounding the bulk of the receiver. This large copper trace is expected to act as a shield to absorb some of the transmissions emanating from the transmitter and dispersing the noise to ground via an inductor. One major problem with this design is that the spacing between the VCSEL and the photodiode does not meet the specification for a Duplex SC connector, the type that would typically be used for such an application. This is the reason for the second, aggressive PCB layout, which can be seen in the following figure. In this layout the photodiode has been moved closer to the VCSEL, and some of the passive components that sat in-between the diodes in the primary design have been moved out of the way. This is considered a more aggressive design because, while it does achieve proper spacing, the extension of the wires connecting the photodiode to the MAX3266 chip make it much more likely that a significant amount of interference or 19 cross-talk will be observed. However, if this design does work, it will be a significant achievement, especially considering that this board is essentially a first draft. While care was taken to use the shortest traces possible in high frequency signal parts of the board, it was extremely difficult, and in some cases simply impossible to Aggressive PCB Layout (Fig. 5.4.2) keep all traces under 4mm in length. At this point, determining the effectiveness of the layout will have to wait until the coming weeks when the boards are completely assembled and tested. It will be interesting to see how much noise is observed and to determine whether or not the receiver shield has any positive (or negative) effects. It may be necessary to assemble a second copy of the board so that the transmitter and receiver can be tested independently of one another. 20 6. Delays and Problems The single most prominent problem of the Gbps Optoelectronic link was the availability of 1000BASE-SX short wave VCSEL’s and PD’s. The 850nm VCSELs and PD’s are in such low demand that many companies are no longer producing these products. Some companies that were operating just a year ago are now completely out of business. Progress was stalled for couple of weeks while the parts were unavailable. Fortunately by collaborating with the other group and with the help of our lab TA, a Hamamatsu PD and Lasermate VSCEL were located and acquired. But as a result of such limited selection, other combination of PD’s and VSCEL’s on future board designs will not be possible. There were two minor problems with the test board. First, the power connections were faulty and did not drive the chips. We replaced these faulty power connections and solved this issue. Faulty power connection (Fig 6.1) Waveform result of faulty power connection (Fig. 6.2) 21 Second was a layout problem. The two output SMA connectors on the transmitter were shorted to ground and needed to be etched with an engraver to complete the assembly. A few days of testing were lost due to this small problem but it was quickly solved with the engraver. Below are the pictures of the ground planes of SMA connectors of the Test board. Before etching (Fig 6.3) After etching (Fig. 6.4) 22 In addition, there was some trouble triggering on the oscilloscope. A lot of tweaking had to be done before a clean eye could be displayed. Fortunately, the use of the BER allowed a secondary measurement of error, this time without running into problems of triggering. BER (Fig. 6.5) 7. Receiver Test board results Receiver Test Board (Fig 7.1) 23 The following are wave forms of PRBS7 at 2 sec persistence: 0 dB attenuation (Fig 7.2) 10 dB attenuation (Fig 7.3) 20 dB attenuation (Fig 7.4) 30 dB attenuation (Fig 7.5) 40 dB attenuation (Fig 7.6) 50 dB attenuation (Fig 7.7) At 0 dB attenuation, the pattern generator is overdriving the Maxim chip. This results in a poor eye diagram with a BER of 2.8 E-08 over 1min. Attenuation between 10dB and 42 dB produces an acceptable eye diagram with a BER of 0.0E-9 over 1 min. Beyond 42 dB attenuation, the signal is lost. 24 Conclusion and Future Plans We successfully tested the evaluation board and implemented and verified the operation of the test board. We successfully designed our first Gb Ethernet Optical Transceiver printed circuit board with the optical devices on-board. Using the ExpressPCB software, we then drew the layout and submitted the design for fabrication. We also successfully ordered our passives and VCSELs and PDs. Now, the next step in the project is to electrically and optically test the first transceiver board. Once we verify that the transmitter and receiver are working independently, an optical and electrical loop-back test will be performed to verify simultaneous operation of the transmitter and receiver. Then alignment tolerance tests will be performed on the transceiver board. Once this is finished, our goal is to design a second board with improvements. This board will fix mistakes on the first board design, optimize costs and display a more aggressive design that uses minimum area. Finally, we will analyze all the test results from the first and second transceiver boards and compare the measurements to theoretical estimates. 25 8. References [1] Tutorial: how optical Ethernet is disrupting the network marketplace: understanding the causes, trends, and implications. Thatcher, J. Optical Fiber Communication Conference and Exhibit, 2002. OFC 2002 , 17-22 Mar 2002. Pages:528 [2] Gigabit Ethernet. Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on , 6-9 May 2001. Pages:9.4.1 - 9.4.16 [3] VCSEL research, development and applications at Honeywell. Morgan, R.A. Vertical-Cavity Lasers, Technologies for a Global Information Infrastructure, WDM Components Technology, Advanced Semiconductor Lasers ..., Gallium Nitride Materials, Processing, ..., 1997 Digest of the IEEE/LEOS Summer Topical Meetings , 11-15 Aug. 1997. Pages:5 – 6 [4] The influence of photodiode design on receiver sensitivity. MacBean, M.D.A. Optical Detectors, IEE Colloquium on , 19 Jan 1990. Pages:7/1 - 7/4 [5] Blackboard Courses, “Course Documents/ Lecture Materials,” [Online document], 2004 March 20, Available HTTP: https://courses.duke.edu [6] IEEE, “802.3 IEEE Standard” [Online document], 2004 March 26, Available HTTP: http://standards.ieee.org/ [7] Optek Technology, Inc. Website. Accessed March 20th 2004 http://www.optekinc.com. [8] IEEXPLORE http://ieeexplore.ieee.org/iel4/5830/15560/00720570.pdf?isNumber=15560&prod=STD& arnumber=720570&arSt=&ared=&arAuthor= [9] Hamamatsu Data Sheet http://www.hpk.co.jp/Eng/products/ssd/pdf/s7911_s7912_kpin1041e02.pdf [10] Lasermate Data Sheet http://www.lasermate.com/tlcp85a4x6-3.html [11] OSI Data Sheet http://www.osifibercomm.com/data/silicon/850nm-1.25Gbps.pdf [12] Maxim Data Sheet http://pdfserv.maxim-ic.com/en/ds/MAX3266-MAX3267.pdf [13] VCSEL picture www.root.cz/clanek/1420 26