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ISSCC 2007 / SESSION 2 / OPTICAL COMMUNICATIONS / 2.2
2.2
A 90nm CMOS 16Gb/s Transceiver for Optical
and phase samplers are generated by an adaptive bandwidth frequency-synthesis PLL [4], while a secondary phase loop selects 2
of the PLL phases to interpolate between in order to provide the
optimal receiver sampling position. The interpolated phase, 1, is
Samuel
Paem,AiaEaiNysaa,used as the feedback clock for the frequency synthesis PLL,
allowing for the simultaneous shifting of all VCO phases with
'Stanford University, Stanford, CA
only one interpolator, instead of 5, normally required in a 1-to-5
2Columbia University, New York, NY
demultiplexing receiver. Because the interpolator is in the feedAs I/O bit rates have increased in order to accommodate growing back path, any glitches due to interpolator switching are filtered
on-chip aggregate bandwidth, the disparity between optical and by the PLL. Also, the delay from the VCO to the samplers is minelectrical channels at the board and box level has risen. This imized, resulting in reduced jitter accumulation. While the freincreases electrical link equalization complexity and leads quency synthesis PLL and secondary phase loops are coupled, the
designers to consider optical interconnects in order to meet I/O implementation can be treated as an effective dual-loop system if
power-budget and density requirements. A dense low-power full the loop bandwidths are set appropriately. The frequency-syntheoptical transceiver cell capable of 16Gb/s operation is developed sis loop bandwidth is set relatively high (40MHz for 16Gb/s operto explore the potential of optical interconnects to meet growing ation) to filter phase noise from the ring oscillator and allow the
PLL to track the CDR updates, while the secondary phase loop
chip-to-chip bandwidth requirements.
bandwidth is set low (<4MHz) to filter out phase errors caused by
The transceiver architecture is shown in Fig. 2.2.1. In order to low input SNR for the phase samplers.
enable short bit periods without consuming excessive area and
power in clock generation and distribution, a multiple clock Precise phase spacing of the recovered clocks is essential for good
phase multiplexing architecture is used at both the transmitter sensitivity, because any phase error will result in a reduced douand the receiver. In the frequency-synthesis PLL of the transmit- ble-sampled differential voltage at the receiver. Clock buffers
ter, a 5-stage coupled pseudo-differential ring oscillator provides with digitally-adjustable capacitive loads are used to tune out
5 sets of complementary clock phases spaced a bit-period apart. mismatches in the VCO and clock distribution network, such that
These phases are used to switch a 5-to-1 multiplexer to produce a initial phase errors in the range of +12% of a bit period are
serial data stream. The multiplexer serial output is buffered by reduced to <2%. Since there is a static path from the VCO to the
the VCSEL driver output stage, described in detail in [1]; it con- receiver samplers (due to the phase interpolator being in the PLL
sists of a 4-tap current-mode FIR filter that equalizes the VCSEL feedback path), these phase errors can be tuned with a low bandresponse at high data rates. At the receiver side, a low-voltage width control loop
integrating and double-sampling front-end performs demultiplexing dilrectly at the input node using 5 uniform clock phases The optical transceiver is fabricated in a 90nm standard CMAOS
process. Both the 850nm VCSEL and photodetector are attached
from the dual-loop clock-recovery systemn.
with short wirebonds, as shown in Fig. 2.2.7. The optical eye diaThe integrating and double-sampling receiver front-end, shown grams of Fig. 2.2.4 show how the equalizing transmitter provides
in Fig. 2.2.2, demultiplexes the incoming data stream with 5 par- a 45% increase in vertical eye opening and enables the lOGb/s
allel segments that include a pair of input samplers, a buffer, and class VCSEL to operate at 16Gb/s with 6.2mA average current
a sense-amplifier. Two current sources at the receiver input node, and 3dB extinction ratio. The transceiver performance is summathe photodiode current and a current source that is feedback rized in Fig. 2.2.5. Recovered clock jitter is 19psrms (Fig. 2.2.6)
biased to the average photodiode current, supply and deplete while the optical receiver sensitivity with BER=10-10 is -9.6dBm
charge from the receiver input capacitance respectively. For data average optical power at lOGb/s and -5.4dBm at 16Gb/s. Using
encoded to ensure DC balance, the input voltage will integrate up the photodiode responsivity of 0.5mA/mW at 850nm and the
or down due to the mismatch in these currents. A differential measured 440fF input capacitance, this converts to an input voltvoltage, AVb, is developed in each receiver segment by sampling age swing of 12.5mV at lOGb/s and 20.2mV at 16Gb/s. It is worth
at the beginning and end of a bit period defined by the rising edge noting that the wirebond connection to the photodetector adds
of the recovered clocks cP[n] and cP[n+1], respectively. While in a extra parasitics and superior sensitivity numbers (less optical
previous implementation [2] Avb was applied directly to an offset- power for a given input voltage swing) could be achieved with a
more integrated
approach, such as flip-chip bonding. The transc
corrected StrongArm latch used as a sense-amplifier for data c
su
meV
VCSEL oupu tae fora ta
mption of
regeneration, the reduced supply voltage that comes with scaling thes2
t
technologies causes the integrating input to exceed the senseamp input range. In order to fix the sense-amp common-mode 129mW or S.lmW/(Gb/s). The total transceiver area is 0, 105mm2,
input level and buffer the sensitive sample nodes from kickback Acknowledgments:
charge, a differential buffer is inserted between the samplers and The authors would like to acknowledge the help and support of D. Patil, B.
the sense-amp. The power penalty of the additional buffer is quite Nezamfar, P. Chiang, and B. Gupta, CMP and STMicroelectronics for chip
small (250!rW per segment), as buffer gain is low to avoid sense- fabrication, ULM photonics for VCSELs, Albis Optoelectronics for photodiamp offset saturation and bandwidth requirements are relaxed odes, and MARCO-IFC for funding. S. Palermo thanks Sh. Palermo for
due to input demultiplexing. The use of PMOS samplers provides constant help and support.
a receiver input range from 0.6 to 1.lV. Demultiplexing directly References:
at the input gives the sense amp sufficient time (5 times the bit [11 S. Palermo and M. Horowitz, "High-Speed Transmitters in 90nm CMOS
period) for data regeneration and precharging, thus eliminating for High-Density Optical Interconnects," Proc. ESSCIRC, pp. 508-511, Sep.
2006
the requirement for a TIA operating at the bit rate.
[2] A. Emami-Neyestanak et al., "CMOS Transceiver with Baud Rate Clock
Clock recovery is implemented with the dual-loop architecture Recovery for Optical Interconnects," Symp. VLSI Circuits, pp. 410-413,
shown in Fig. 2 2.3. It expands the worTknpresented in [3] to mul- June 2004,
1 se of^ reciverseg- ~~~~[31P. Larsson, "A 2-1600MHz CMOS Clock Recovery PLL with Low-Vdd
.
* I 1 I 1 AA addtionl
tiplecloc phae
opratin.
IEEE J. Solid-State Circuits, vol. 34, no, 12, pp. 1951-1960,
to a baud -rate phzase Dec. 1999.
information
binary
es
phnase
meatvs provid
detector [2] which, when compalred to a common 2x overcsampling [41 5. Sidiropoulos et: at,, "Adaptive Bandwidth DLLs and PLLs usinlg
scheme, saves power and area by reducinLg the number of distlrib- Regulated Supply CMOS Buffers," Symzp. VLSI Circuits, pp. 124-127, June
uted clock phases by7 a factolr of 2. The clock phases folr the data 2000.
Interconnects
Capability,"'
44
I 2007 IEEE International Solid-State Clircits Conference
1-4244-0852-0/07/$25.00 ©2007 IEEE1
ISSCC 2007 1 February 12,j 2007 / 2:00 PM
LVdd
-----V----------
VCSEL
3.2GHz
~~~~ITb
V.
v
~~~~~~~~~~PDBias
AVb
T~ ~
Photodiode
DtimeO
l~~~~~~~~~~~~~~~~~~pdr v0
V
0
I
D[4:0]
800MHz'
TX
VCSEL Driver
Ref Clk
Generation
--
Photodiode
Dt
C-Z1
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ci
ici
R DBiaaDRx[4:0]
Pin Dbiata
d4f
10
t
Data
Verifier
a
<
/
C
L40
/
(6bs
Pass
a,,vg 4
PaaeiV
00]T0
~~~~~Offset[9:0]
V
Ref
Clk--*
Synthesis
OOL[.]
OPLL
b,
bi,+CP
segment
Buffer
Figure 2.2.2: Integrating and double-sampling receiver tront-end.
Figure 2.21: Optical transceiver architecture.
Frequency
~~~~~~~~~Double-S ampler
CDR
PD
Unequalized Eye
I80H
IRef Clk
[.](2H)
_E~~~~~~~~~~~~~
~~~1.4mW
-sXgcoupled0VCO
SupplyVoltage
VddlV, LVdd2.8V~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~EqaizdEe
Data Rate
5-16Gb/s~~~~~~~~~~~~~~~
ER
3dB~~~~~~~~~~~~~~~~~~~ntroao
Avrae ptca Lunh owr
.lBmRcoerd lok iterRXSesiivt
TX6GClock
Rite
25pii
Baub dn1.Os,p=4.p
-12~~~~~~~~~~~~~~ery
Area
RXn Frn-Ed0.2mmlataattGea
PowRaerDisiptinGb16b/
RX Front-End
23mW
Totals
1285mW,(8.mAWIGbWI)
Fiur622.
brascie petomacesu
mary
9.dlrn
Figurm2.26:6C9 andrecever prtorance
TX Clock Jitter
Cotne>nPg
~~~~~16Gb/DIGET=OFTECHICALpPAE1S
*p4
8
ISSCC 2007 PAPER CONTINUATIONS
Figure 2.2.7: Micrograph of optical transmitter with bonded VCSEL and optical
receiver with bonded photodiode.
5861
200
IEEE11 International Solid-State Circuits Conference
1-4244-0852-O/07/$25100 ©2007 IEEE1