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Optical Gigabit Ethernet Transmitter & Receiver
Group 4
ECE 4006B
Professors: Dr. Brooke & Dr. Jokerst
October 24, 2002
Project Members:
David Abramson
Christopher Durkin
Cesar Lugo
Samir Mowla
Jacob Neal
Ashley Sanchez
Georgia Institute of Technology
College of Engineering
School of Electrical and Computer Engineering
Table of Contents
Overview
1
Selection of Optoelectronic Components
2
Optical Link Budget
5
Receiver Board
11
Transmitter Board
13
Issues and Problems
15
Progress and Outlook
16
Conclusion
22
2
Overview
With the growth of high-speed computers, the need for economically viable high
bandwidth computer networks has greatly increased. This demand has resulted in the
creation of the IEEE 802.3z Gigabit Ethernet standard. The Gigabit Ethernet standard is
an evolution of the original Ethernet standard developed by the Xerox Corporation in the
1970s, with the two standards being identical from the data link layer on up [1]. The
original Ethernet standard has a speed of 10Mbps while Gigabit Ethernet runs at
1000Mbps or 1Gbps. The increased transmission speed places a requirement that all
transmissions of over 25 meters be sent via optical fiber thus introducing optoelectronic
circuitry into the Gigabit Ethernet infrastructure. Optoelectronic circuitry has resulted in
an increase in costs when creating gigabit bandwidth networks. Therefore, it is the
purpose of this project to create a low cost optical Gigabit Ethernet compliant transmitter
and receiver board.
The IEEE 802.3z is the specific optical Gigabit Ethernet standard, and as such, the
design of the transmitter and receiver must conform to the specifications laid out by the
standard. The design had added constraints placed on it because of the materials used.
For example, 62.5µm multimode fiber resulted in the use of the 1000BASE-SX
specifications found in the IEEE 802.3z standard. These constraints help shape the
schematic design of both the transmitter and receiver boards. Upon completion of the
design, development of the printed circuit board layout commences, ensuring proper trace
length given the high-speed nature of the signals. The final steps of the project are to
complete the board build and test for compliance with the IEEE 802.3z optical Gigabit
Ethernet standard using eye diagrams.
This paper describes the process of designing an IEEE 802.3z compliant
transmitter and receiver board. It illustrates the design process, technical issues,
schematic design, board layout, and finally the results achieved to date.
1
Selection of Optoelectronic Components
The selection of optoelectronic components was the first step of the actual design
process. The reason for this was that the optical component specifications would
determine the optical link budget, which in turn would determine the actual circuit design
for both the transmitter and receiver board. The optoelectronic components were
comprised of a Vertical Cavity Surface Emitting Laser (VCSEL) for the transmitter board
and a photodiode (PD) for the receiver board. This section will illustrate the process of
selecting the optical components for the optical Gigabit Ethernet transmitter and receiver
boards.
Optoelectronic components provide a conversion from electric signals to optical
signals and back again. This is necessary as data flows, in an electronic form, from a data
source to an optical Gigabit Ethernet card before converting the electronic data into light
and transmitting it over optical fiber. A VCSEL is used to convert a electronic signal to
an optical signal. For this project, the IEEE 802.3z standard, along with the
specifications on the MAXIM 3297 laser driver, defined the type of VCSEL required.
The most important characteristics that a VCSEL had to possess were a wavelength () of
around 850nm, a typical slope efficiency (η) of 0.04mW/mA, and a common cathode
configuration. With these requirements, it was determined that Honeywell VCSEL
models HFE 4080-321 and HFE 4381-521 would be suitable. The specifications of these
two VCSELs are on the following page in Table 1.
With the project involving measuring the alignment tolerance for both the optical
Gigabit Ethernet transmitter and receiver boards, it was necessary to purchase both
connectorized and unconnectorized VCSELs. Unconnectorized VCSELs allowed for
alignment tolerance testing while connectorized VCSELs remove alignment uncertainty
when testing the board. The connectorized VCSEL package includes a power monitor
diode that allows the user to control the maximum optical power level of the laser
through a feedback circuit. Despite the ability to use the feature, the group made the
decision to neglect it to keep the design simple.
An issue that arose was the major difference in slope efficiencies for the
connectorized and unconnectorized VCSELs. This difference is due to the attenuated
slope efficiency feature included in the connectorized VCSEL. The product
2
specifications of the HFE 4381-521 describe the risk of jitter due to off-state bounce.
Since the VCSEL has a multi-transverse mode structure, it is found that the modes are
spatially separated and surrounded by regions that are forward-biased, but not lasing.
This results in a charge carrier gradient that draws carriers from the surrounding material,
producing a small bounce after the pulse falling edge. This bounce may be separated
from the falling edge or may blend with it causing an increase in the fall time τf. This offstate bounce effect can be minimized by increasing the modulation current. However, if
the modulation current is increased it is necessary to make sure that it does not raise the
average power to unacceptable levels. For this reason, the connectorized VCSEL is
designed with an attenuated package to reduce the slope efficiency. The optical power
link budget took into account both slope efficiencies in the calculations.
Honeywell VCSELHFE 4080-321 (unconnectorized)
VCSEL Parameters
Peak Operating Current
Threshold Current
Slope Efficiency Po =1.3mW
Laser Forward Voltage
Laser Reverse Voltage
Rise and Fall Times Pre-bias
Above
Beam Divergence
Symbol
Ipeak
Ith
η
VF
BVRLD
τr
τf
θ
Min.
1.5
0.1
1.6
5
5
Typ.
12
3.5
0.25
1.8
10
100
200
15
Max.
20
6
0.4
2.2
Typ.
12
3.5
0.04
1.8
10
150
200
15
Max.
300
300
20
Units
mA
mA
mW
/mA
V
V
ps
Degrees
Honeywell VCSEL HFE 4381-521 (connectorized)
VCSEL Parameters
Peak Operating Current
Threshold Current
Slope Efficiency
Laser Forward Voltage
Laser Reverse Voltage
Rise and Fall Times Pre-bias
Above
Beam Divergence
Symbol
Ipeak
Ith
η
VF
BVRLD
τr
τf
θ
Min.
0.02
1.6
5
5
6
0.1
2.2
300
300
20
Units
mA
mA
mW
/mA
V
V
ps
Degrees
Table 1. Specifications of the two VCSELs selected for use in the TX board.
The purpose of the photodiode is to receive the optical signal produced by the
VCSEL and convert it back into an electrical signal. To select an appropriate photodiode,
the characteristics considered were the sensing area, responsivity, sensitivity, dark current,
3
and capacitance. A large sensing area was vital to increasing alignment tolerance as it
would allow for a greater range of alignment with the fiber, while still being able to
detect a signal. The responsivity was important in determining the amount of power
required from the fiber to provide the minimum signal strength needed by the
transimpedance amplifier (TIA). The larger the responsivity, the larger the electrical
signal produced by the photodiode becomes for a given input power. A large
responsivity would allow for a greater alignment tolerance of the fiber, as it would help
keep the signal current to the transimpedance amplifier above the minimum requirement.
In addition, the requirements of a maximum input to the fiber of 1mW, as per the eye
safety standards, and a maximum loss of 7.5dB over the length of the fiber helped in the
comparison of photodiodes at working conditions. Table 2 shows the specifications of
the selected connectorized and unconnectorized photodiodes.
OSI
Responsivity Cap.
FCI-125G-006HR
FCI-125G-006HR/SC
0.36 A/W
0.36 A/W
0.66pF
0.66pF
Sensing Area Sensitivity
150 um Diam.
150 um Diam.
Notes:
Not stated Flat window
Not stated SC connectorized
Table 2. Specifications of the two photodiodes selected for use in the RX board.
The initial field of potential photodiodes had candidates from Honeywell, OSI,
and Lasermate. It was determined that the Honeywell photodiodes were not suitable as
their responsivity was well below the rest of the photodiodes. The Lasermate and OSI
photodiodes were similar in most respects, with the exception that the Lasermate
photodiode contained a transimpedance amplifier chip already built into the photodiode.
With the transimpedance amplifier chip already provided for our design, the redesign
effort required to accommodate the Lasermate photodiode with the built in
transimpedance amplifier would have been considerable. Thus, it was determined the
OSI photodiode would be best suited for this project.
Following the selection of optoelectronic components, the next step was to create
an optical link budget that aids in the circuit design of the transmitter and receiver boards.
4
Optical Link Budget
The optical link budget is a method of determining the amount of propagation loss
that an optical signal can tolerate when transmitted across a fiber optic medium, yet still
comply with IEEE 802.3z standards, which specify characteristics of an optical Gigabit
Ethernet data communication link. These standards not only specify the data transfer rate,
but also set standards for optical transmitters and receivers, both of which are dependent
upon the type of fiber optic cable and the wavelength of the optical signal [2]. When
calculating the optical link budget, there is an underlying assumption that the design
complies with the 1000BASE-SX standards when transmitting an 850nm wavelength
over 62.5μm multimode fiber. Of the requirements found in the standard, the laser safety
specifications [5], extinction ratio [6], and worst-case link power budget [7] are the most
important in calculating the optical link budget. Using the requirements set forth in the
standard, the link budget is also used to determine the range of bias currents for the
VCSEL, IBIAS, the modulation current of the transmitted signal, IMOD, and the output
current of the photodiode, IPD,OUT.
The optical link budget for the connectorized and unconnectorized VCSELs is
shown in Tables 3 and 4 respectively.
Connectorized VCSEL HFE 4381-521
ITH,RANGE = 3.5mA to 6mA
ηRange = 0.02 to 0.1mW/mA
IBIAS
IMOD
ITOTAL,RANGE
ηRange
PVCSEL,OUT,RANGE
Connector &
Fiber Loss
ITH,MAX = 6.0mA
ηMAX = 0.1mW/mA
11.6294mA
4.3705mA
7.259 - 16mA
0.04 - 0.1mW/mA
0.1259 - 1.0mW
ITH,MAX = 6.0mA
ηMIN = 0.02mW/mA
34.148mA
21.852mA
12.295 - 56mA
0.02 - 0.1mW/mA
0.1259 - 1.0mW
ITH,MIN = 3.5mA
ηMAX = 0.1mW/mA
9.1295mA
4.3705mA
4.759 - 13.5mA
0.02 - 0.1mW/mA
0.1259 - 1.0mW
ITH,MIN = 3.5mA
ηMIN = 0.02mW/mA
31.648mA
21.852mA
9.795 to 53.5mA
0.02 - 0.1mW/mA
0.1259 - 1.0mW
7.5 dB
7.5 dB
7.5 dB
7.5 dB
PD FCI-125G-006HR/SC
Rλ TYPICAL = 0.36A/W
PPD,IN,RANGE
0.02238
0.1778mW
Rλ TYPICAL
IPD,OUT,RANGE
ITIA INPUT,RANGE
8.0594 64.018μW
30μA to 1mA
0.02238 0.1778mW
0.02238 0.1778mW
0.36A/W
8.0594 8.0594 64.018μW
64.018μW
30μA to 1mA
30μA to 1mA
0.02238 0.1778mW
8.0594 64.018μW
30μA to 1mA
Table 3. Optical link budget for connectorized VCSEL and photodiode.
5
Unconnectorized VCSEL HFE 4080-321
ITH,RANGE = 1.5mA to 6mA
ηRange = 0.1 to 0.4mW/mA
IBIAS
IMOD
ITOTAL,RANGE
η
PVCSEL,OUT,RANGE
Connector &
Fiber Loss
ITH,MAX = 6.0mA
ηMAX = 0.4mW/mA
7.4074mA
1.0926mA
6.3147 - 8.5mA
0.4mW/mA
0.1259 - 1.0mW
ITH,MAX = 6.0mA
ηMIN = 0.1mW/mA
11.6294mA
4.371mA
7.2589 - 16mA
0.1mW/mA
0.1259 - 1.0mW
ITH,MIN = 1.5mA
ηMAX = 0.4mW/mA
2.9074mA
1.0926mA
1.8147 - 4mA
0.4mW/mA
0.1259 - 1.0mW
ITH,MIN = 1.5mA
ηMIN = 0.1mW/mA
7.129mA
4.371mA
2.7589 - 11.5mA
0.1mW/mA
0.1259 - 1.0mW
7.5 dB
7.5 dB
7.5 dB
7.5 dB
PD FCI-125G-006HR
Rλ TYPICAL = 0.36A/W
PPD,IN,RANGE
0.02238
0.1778mW
Rλ TYPICAL
IPD,OUT,RANGE
ITIA,INPUT,RANGE
8.0594 64.018μW
30μA – 1mA
0.02238 0.1778mW
0.02238 0.1778mW
0.36A/W
8.0594 8.0594 64.018μW
64.018μW
30μA - 1mA
30μA - 1mA
0.02238 0.1778mW
8.0594 64.018μW
30μA - 1mA
Table 4. Optical link budget for unconnectorized VCSEL and photodiode.
The data compiled in the tables can be referenced in the Honeywell specification sheets
for the connectorized [8] and unconnectorized VCSELs [9], the MAXIM transimpedance
amplifier data sheets [10], and the OSI Fibercomm photodiode reference sheets [11].
Although the maximum threshold current was identical for both VCSELs, only a
minimum value was specified for the unconnectorized VCSEL; therefore, the typical
value was used in the link budget calculations for the connectorized VCSEL. The
connectorized VCSEL’s slope efficiency, η, is much lower than the unconnectorized laser
for reasons discussed in the selection of the VCSEL. When the value of η differs, both
the bias and modulation currents differ; however, if η remains constant as ITH is varied,
the bias current still changes, but the modulation current is unaffected. Equation 1 shows
the mathematical relationship among ITH, η, the total current, ITOTAL, and the VCSEL
output power, PVCSEL.
I TOTAL  I TH 
PVCSEL

Eq. (1)
6
Inputting each individual combination of minimum and maximum values for ITH , η, and
PVCSEL into Equation 1 results in four different ranges of output currents. These represent
the four extremes, or worst-case currents that could result if the VCSEL exhibits
characteristics that vary widely from its typical values.
In order to calculate ITOTAL, 1mW was used as the maximum power that the
VCSEL could output and still fall within the laser safety standards [12]. IEEE 802.3z
mandates the maximum output power of the VCSEL should be the lesser of 1mW and the
output power calculated following the IEC 60825-1, Amendment 2 laser safety standards.
Because a free copy of the IEC standard was unavailable, and the IEEE standard specifies
the use of 1mW may be appropriate, 1mW was selected as the maximum power output.
The minimum output power was determined according to a 9dB extinction ratio [13].
This is not a concrete number set by the standards, but is selected in order to achieve the
best optical eye diagram considering optical jitter, eye width, eye height, power penalty,
and overall system bit error rate (BER) [14]. The power penalty can be represented by an
exponential curve in the first quadrant. Ideally, the extinction ratio is infinite because the
minimum power is zero. Realistically, it is not, and the power must be increased as the
extinction ratio decreases in order to maintain a constant BER. The extinction ratio can
be decreased to approximately 9dB before the power penalty begins to increase
exponentially. The 9dB standard was selected because as the ratio decreases below 9dB,
the power penalty increases by about 10% per dB [15]. Greater values can also hinder
performance because if its value is too large, the compliance margin of the eye diagram
decreases as the standard mask is increased. This can be interpreted as meaning that the
tolerance of the output decreases if the extinction ratio is too great. Therefore, 9dB is an
optimal value and the value chosen by IEEE 802.3z when determining the receiver
sensitivity standard [16]. In essence, this ratio describes the maximum optical power
output that corresponds to a binary 1 with the minimum optical power output that
corresponds to a binary 0 [17]. The minimum power is 0.1259mW, which is 9dB less
than the 1mW maximum. By using these two values in conjunction with Equation 2,
IBIAS was determined. Equation 3 was used to determine the positive and negative
modulation current that carries the signal.
7
I BIAS 
I
TOTAL, MAX
 I TOTAL, MIN 
2
 I MOD  I MAX  I BIAS
Eq. (2)
Eq. (3)
This calculation was repeated for each combination of the connectorized and
unconnectorized VCSELs. Because only one photodiode was used, the values in the
lower half of both tables are identical. The minimum current for each column is simply
the bias current less the modulation current, which is always greater than the threshold
current. This insures that the VCSEL will remain on, and not drop below the threshold
current as the modulation current reaches its minimum value.
In addition, the standards specify that a flat 7.5dB of loss should be used in the
optical link budget calculation despite the ease with which the actual connector and
insertion loss could be calculated. This 7.5dB is much greater than the actual loss;
however, this guarantees that the photodiode receives enough light to detect a signal. The
typical dark current for the OSI Fiberomm photodiode is 30pA, which is easily supplied
despite the added loss.
Clearly, Tables 3 and 4 contain worst-case values using the extreme ranges of ITH
and η for those calculations except the aforementioned typical value of ITH used for the
connectorized VCSEL. It is likely that both VCSELS will have a threshold current of
approximately 3.5mA. The slope efficiencies differ for the two parts, but each will likely
display an average value; therefore, an expected value for the unconnectorized part is
0.25mW/mA and the connectorized part will likely have a slope efficiency of
0.04mW/mA. Figures 1 and 2 show the calculations using these typical values for the
unconnectorized and connectorized parts.
8
ITH  3.5
  0.25
PVCSELMIN  0.1259
PVCSELMAX
ITOTALMAX  ITH 

ITOTALMAX  7.5
ITOTALMIN  ITH 
PVCSELMIN

ITOTALMIN  4.004
ITOTALMAX
IBIAS 
PVCSELMAX  1
 ITOTALMIN 
2
IMOD  ITOTALMAX  IBIAS
IBIAS  5.752
IMOD  1.748
+/-
 is in mW/mA
All currents in mA, power is in mW, and
Figure 1. Calculations of typical bias and modulation currents for the
unconnectorized VCSEL.
ITH  3.5
  0.04
PVCSELMAX  1
PVCSELMIN  0.1259

ITOTALMAX  ITH 
PVCSELMAX

ITOTALMAX  28.5
IBIAS 
ITOTALMIN  ITH 
PVCSELMIN

ITOTALMIN  6.6473
ITOTALMAX
 ITOTALMIN 
2
IMOD  ITOTALMAX  IBIAS
IBIAS  17.5737
+/-
IMOD  10.9263
All currents in mA, power is in mW, and
 is in mW/mA
Figure 2. Calculations of typical bias and modulation currents for the
connectorized VCSEL.
These bias and modulation currents should be closer to the experimental values than
those listed in Tables 3 and 4. The modulation current is greater which should result in
an improved BER because it will be easier to distinguish between high and low outputs.
This is expected because the output data is shaped by the modulation current. Figures 1
9
and 2, and Tables 3 and 4 demonstrate how the modulation current is determined by η,
and is not a random number. It is only dependent on the slope efficiency of the VCSEL,
whereas the bias current is dependent upon the threshold current and the modulation
current. Although the greater modulation current creates a larger output signal, making it
easier to distinguish between a binary 1 and 0, there is a trade-off in that a higher the
modulation current results in a higher bias current, increasing the total current. As these
two increase, the VCSEL runs hotter meaning more current is necessary to produce the
same output power. This increased current makes the VCSEL run even hotter, further
lowering the output and requiring additional current. This cycle can shorten the life of
the VCSEL. The need for a balance makes the extinction ratio more meaningful. By
separating the input and output power by 9dB, less data interpretation errors occur
because the high and low values have a greater separation, making the range of values
which may be misinterpreted smaller, yet the current is not increased so much as to
overheat the VCSEL and shorten its life.
Although the optical link budget is actually an account of the gains and losses of
the signal as it is traced from its input to output, it is really used as a design tool in
determining the proper level at which to bias the laser driver, and the approximate
modulation current level. Further, it had an impact on the passive components selected
for the board layout. It was necessary to select values of resistors and potentiometers so
that even the extreme cases listed in Tables 3 and 4 could be realized if necessary. It
confirmed that the minimum value of the input current to the transimpedance amplifier
exceeded the 30μA [18] needed to produce a clear eye diagram with minimal jitter.
Therefore, it played an important role in both the design and the verification that the
design has the power throughput necessary to produce a Gigabit Ethernet compliant result.
10
Receiver Board
The design for the receiver board is shown below in Figure 3.
Figure 3. Receiver board schematic diagram.
The receiver board uses two MAXIM chips, the 3266 and the 3264. The MAXIM 3266
is a transimpedance amplifier that converts the current input from the photodiode to an
output voltage. The MAXIM 3264 is a limiting amplifier that amplifies the output of the
transimpedance amplifier to the point of clipping. This produces a pseudo-digital output
from the limiting amplifier. The two chips both use 5V power supplies.
A large portion of the design for the receiver board was designing for biasing and
decoupling. Capacitors C1, C5, and C6 were included for power supply decoupling. The
1nF capacitors were used because they have the lowest resistance at the frequencies
which need to be removed, 500MHz to 1GHz. Capacitors C3, C4, C7, and C8 were used
for AC coupling. In other words, they are used to keep the DC biasing from passing
through them. The 0.01F capacitors were used because they allow the desired
frequencies to pass through but exhibit a large enough resistance to the lower frequencies
they are meant to block.
The remaining circuit elements are the functional part of the receiver board. The
photodiode sources current to pin 3 of the transimpedance amplifier. Capacitor C2 was
included for noise reduction reasons. Its purpose is to reduce the noise current entering
the input of the transimpedance amplifier. A 400pF capacitor was chosen to reduce the
11
amount of noise to which the circuit is subjected. Pins 5 and 8 are both grounds for the
transimpedance amplifier. Pins 6 and 7 are the inverting and non-inverting output
respectively. The differential output created by them is then used as the input for the
limiting amp. Pins 4 and 5 of the limiting amplifier are the non-inverting and inverting
inputs respectively. The pseudo-digital output is on pins 12 and 13. Resistors R1 and R2
are used to terminate the output leads and to produce a DC bias current in those leads.
The limiting amplifier also has two grounds, pins 3 and 6.
The receiver board layout was taken almost completely from the layout provided
by Dr. Brooke. The only changes necessary to the board were the addition of the
photodiode and its associated filter capacitor. The photodiode was placed as close as
possible to the transimpedance amplifier to avoid loss and transmission line effects in the
low-level, high-frequency signals that are received. As the original design had two
different power supplies to avoid crosstalk between the two ICs, a provision was added to
avoid this inconvenience. Both supply connectors were included, but the two nets could
be tied together with an inductor. This would reduce noise transmission between the ICs
while having only one supply connected. If this is not feasible, it is easy to revert to the
original design with two supplies. The resulting receiver board layout is shown below in
Figure 4.
Figure 4. Receiver board layout.
12
Transmitter Board
The design of the transmitter board is shown in Figure 5.
Figure 5. Transmitter board schematic diagram.
The transmitter design uses the MAXIM 3297, a laser driver chip that takes a differential
input signal and produces the modulation current needed to drive the VCSEL. As with
the receiver board, a large portion of the design was decoupling and biasing. Capacitors
C1, C4, C5, and C8 are used for power supply decoupling. Capacitors C2, C3, C6, and
C7 are used for AC coupling. Furthermore, inductors L1, L2, and L3 are used for DC
coupling. The purpose of the DC coupling is so that the high-frequency signal does not
propagate through any of the bias circuitry. The laser driver is grounded at pins 1 and 6.
Pin 2 is the power-on reset pin and MAXIM suggests a 0.01 F capacitor be used to
connect it to ground. However, testing has proven that the circuit will not work unless
pin 2 is connected to ground or power. Pins 4 and 5 make up the differential input to the
laser driver. Resistor R1 is used to terminate the 50  input transmission lines. The
output from the laser driver is also differential; the non-inverting output is pin 12 and the
inverting output is pin 13. The inverting output is used as the return path for the current
output on pin 12. The resistance of R4, which terminates the lead on pin 13, should be
matched to that of pin 12, the resistance of the VCSEL.
13
The VCSEL requires both a DC bias current and the modulation current produced
by the laser driver. The resistor, R6, and potentiometer, R5, are combined in series to
limit the DC bias current. The resistor is placed in series with the potentiometer so that
when the potentiometer is set to 0, the current does not become too high. The value of
the resistor and potentiometer were chosen such that the DC bias current can be adjusted
from the threshold current of the VCSEL to a much higher value. The modulation
current that carries the signal is produced by the laser driver, which is controlled by the
resistor, R2, attached to pin 15. By using a 20k potentiometer as R2, the modulation
current can be roughly varied from 0mA to 30mA, the maximum output of the laser
driver. Although the laser driver outputs a positive current, there is an AC coupling
capacitor, C7, that the modulation current must go through causing it to be centered at
0mA. The potentiometers must be adjusted so that the total current, which consists of the
DC bias current plus the modulation current, does not fall below the threshold current of
the VCSEL. In addition, the output power from the VCSEL must be kept below the eye
safety standard of 1mW.
The major design goals in the transmitter board layout were to keep all traces as
short and straight as possible while keeping component placement tight and orderly. All
signal traces were routed on the component side to avoid any major discontinuities in the
ground plane. Every effort was made to avoid acute or right angles in any traces, as such
angles are prone to fringing electric fields as well as undesired impedances in the signal
path. Decoupling capacitors were used at each power supply pin, with separate power
traces to each capacitor to minimize noise coupling. The power supply traces were
necessarily long and winding in order to keep them on the component side, which also
served to increase inductance, and therefore decrease noise on these lines. The first
revision of the transmitter board layout can be seen on the following page in Figure 6.
Two separate transmit designs reside on a single board. The upper left trace was the
initial draft of our transmit board. After reviewing the design with Dr. Brooke, the lower
right design was added in order to reduce potential feedback by linearizing the design.
This revision of the first transmitter board as shown in the lower right part of the board
was built and future revisions are planned based upon this design.
14
Several changes are planned for the second transmitter board revision. The
VCSEL will be placed closer to the matched load resistor to shorten the current return
path. The EMI filter inductors will be placed further away from each other and at right
angles to reduce coupling. Some of the grounded pins that were connected directly to the
plane will be only partially connected to the ground plane by traces to make part
soldering and desoldering easier. The AC coupling capacitors and load resistor will be
moved to the component side to avoid using vias in the input signal path.
Figure 6. Transmitter board layout.
Issues and Problems
The progress to date has not been without some minor problems. The single
biggest problem encountered has been obtaining the photodiodes from OSI Fibercomm.
The initial order that was placed was confused with an order placed by another group.
This resulted in only half of the original order being received. After the mistake was
found and corrected, the remaining parts were shipped. The two parts that were shipped
late were packaged with another group’s order where they remained lost until Monday,
October 21. As the parts missing were the unconnectorized photodiode and the SC
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connectorized photodiode, there has been a delay of a week in the construction of the
receiver board. Overall, this delay should have a minimal impact on the project timeline
as the schedule was designed to accommodate for unforeseen issues or problems.
Progress and Outlook
The overall project schedule can be seen in the Gantt chart for the project is
shown in Figure 7.
Figure 7. The project Gantt chart.
The initial plan for the division of labor was subdivided into committees with half the
group working on the receiver board, and the other half working on the transmitter board.
However, the actual labor division did not occur this way, as often the requirements of
both boards would overlap. This overlap was the result of components common to both
boards, the dependency between the VCSEL and photodiode selection, and multiple
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layouts on the same board. Thus, responsibilities came to rest on those that were best
suited to the individual task immediately at hand.
Ashley was responsible for research and optical budget calculations. Jacob
worked on optical budget calculations, photodiode selection, and parts acquisition. Cesar
selected the VCSEL and participated in operational tests. David produced the board
schematics, assisted with layout, and performed board tests. Samir was responsible for
all website related tasks and coordination of the written report, as well as board soldering.
Chris produced the management plan, designed the board layout, soldered the boards, and
assisted with lab testing. After the division of labor was solidified, the timeline for the
semester was determined.
The project plan was divided into four distinct periods: background research, parts
acquisition, design and construction of the first board revision, and design and
construction of the second board revision. Upon completion of the board layout the parts
were selected and ordered. Although the board design and layout took a bit longer than
expected, testing still began on schedule by putting extra effort into board construction.
The first transmitter board has been built and successfully tested. Figures 8, 9, 10,
and 11 show the first transmitter board at various stages of the build phase. Figures 12,
13, 14, and 15 show the successful eye diagrams from the transmitter board test
.
Figure 8. The printed circuit board with the transmitter (left) and receiver (right).
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Figure 9. The reverse side of the printed circuit board.
Figure 10. The stuffed transmitter board.
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Figure 11. The reverse side of the stuffed transmitter board.
Figure 12. Eye diagram using K-28.5 through the patch cable.
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Figure 13. Eye diagram using K-28.5 through the 100m cable.
Figure 14. Eye diagram using PRBS7 through the patch cable.
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Figure 15. Eye diagram using PRBS7 through the 100m cable.
As was stated previously, the delay in shipment of the photodiodes has delayed
the construction of the receiver board. Thus, to stay on schedule according to the Gantt
chart, the receiver board must be completed by October 27, which gives ample time to
build and test the board. The upcoming weeks will see the current transmitter and
receiver board layouts revised, submitted for manufacturing, built, tested, and analyzed.
Sixty percent of the allocated budget has been used towards the current board builds. A
detailed budgetary analysis for the project will be undertaken to determine how best to
lower cost per board and to guide us in future board revisions. Both the board and project
budgets will be included in the final paper.
Conclusion
The project is on schedule despite the aforementioned delays. Even though the
transmitter and receiver boards are functioning properly, further revisions are anticipated
to reduce costs and improve performance after reviewing the budget and current project
plan.
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References
[1] CISCO “Gigabit Ethernet Technology Brief,” [Online Document] July 2000, Available HTTP:
http://www.cisco.com/warp/public/cc/techno/media/lan/gig/tech/gigbt_tc.htm
[2] IEEE 803.2z-2002, Section Three, §38.3.1-2, Transmitter Optical Specifications, Receive Optical
Specifications, pp. 106-107
[3] Data Sheet: “FCI-125G-006HR: 850nm,1.25Gbps Large Active Area and High Speed Silicon
Photodiodes” – OSI Fibercomm.
[4] Data Sheet: “MAX3266: 1.25Gbps/2.5Gbps, +3V to +5.5V, Low-Noise Transimpedance Preamplifiers
for LANS.” – MAXIM Integrated Products, June 2000.
[5] IEEE 803.2z-2002, Section Three, §38.7.2, Laser Safety, p.116
[6] IEEE 803.2z-2002, Section Three, §38.3.1-2, Transmitter Optical Specifications, Receive Optical
Specifications, pp. 106-107
[7] IEEE 803.2z-2002, Section Three, §38.3.3, Worst-case 1000BASE-SX link power budget and penalties
(informative), p.107
[8] Data Sheet: “HFE438x-521: Fiber Optic LAN Components, SC Connectorized High Speed VCSEL
1.25 Gbps.” – Honeywell, 2002
[9] Data Sheet: “HFE4080-321: VCSEL Components, Data Communications, TO-45,Unattenuate optics,
no back monitor photodiode.” – Honeywell, 2002
[10] Data Sheet: “MAX3266: 1.25Gbps/2.5Gbps, +3V to +5.5V, Low-Noise Transimpedance
Preamplifiers for LANS.” – MAXIMIntegrated Products, June 2000.
[11] Data Sheet: “FCI-125G-006HR: 850nm,1.25Gbps Large Active Area and High Speed Silicon
Photodiodes.” – OSI Fibercomm.
[12] IEEE 802.3z-2002, Section Three, §38.3.1, Table 38-3, 1000BASE-SX transmit characteristics, p.106.
[13] IEEE 802.3z-2002, Section Three §38.3.1 Table 38-8, 1000BASE-SX Transmit Characteristics, p. 106.
[14] Application Note: “Maintaining Average Power and Extinction Ratio, Part 1 Slope Efficiency and
Threshold Current.” – HFAN-2.3.1, Maxim Integrated Products, June 2002.
[15] Application Note: “Extinction Ratio and Power Penalty.” – HFAN-2.2.0, Maxim Integrated Products,
May 2001.
[16] IEEE 803.2z, §38.3.2, Table 38-4-1000BASE-SX receive characteristics, p. 107.
[17] Application Note: “Maintaining the Extinction Ratio of Optical Transmitters Using K-Factor*
Control.” – HFAN-2.2.1, Maxim Integrated Products, June 2002.
[18] Data Sheet: “MAX3266: 1.25Gbps/2.5Gbps, +3V to +5.5V, Low-Noise Transimpedance
Preamplifiers for LANS.” – Maxim Integrated Products, June 2000.
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