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Group 2 ECE 164.02
Introduction and Final report on the
Electronic Design Project: Gbps Optoelectronic Link
A Report
Presented to
Dr. Brooke and Dr. Jokerst
By
Tyler Helble
Ungtae Lee
Ian Phillipi
Andrew Tupper
April 26, 2004
Duke University
Department of Electrical and Computer Engineering
Table of Contents
1. Abstract ________________________________________________________3
2. Introduction _____________________________________________________3
2.1 General Background ________________________________________3
2.2 Board Elements ____________________________________________4
3. Group Management Plan __________________________________________5
3.1 Division of Labor __________________________________________5
3.2 Time Management and Gantt Chart ____________________________6
3.3 Financial Budget ___________________________________________7
3.4 Bill of Materials ___________________________________________7
4. Getting started on the project ______________________________________8
4.1 Evaluation Board setup and testing_____________________________8
4.2 Test Board setup and testing __________________________________9
5. Optical Link Budget ______________________________________________12
5.1 General Idea ______________________________________________12
5.2 Initial Power Calculations ____________________________________13
5.3 VCSEL Calculations _______________________________________ 13
5.4 Four Corners Analysis ______________________________________ 14
5.5 Fiber Attenuation Calculations _______________________________ 16
5.6 Photodetector calculations & “four corners” analysis ______________ 16
6. Transceiver Design _______________________________________________17
6.1 Design Tools ______________________________________________17
6.2 Transceiver Schematic ______________________________________18
6.3 Receiver Schematic _________________________________________19
6.4 PCB Layout _______________________________________________19
7. Assembly _______________________________________________________22
7.1 Non-aggressive primary design _______________________________22
7.2 Aggressive design __________________________________________25
8. Testing and Results _______________________________________________26
8.1 Optical Baseline Testing _____________________________________26
8.2 Loopback Testing __________________________________________27
9. Alignment Tolerance _____________________________________________28
10. Cross Talk Testing ______________________________________________29
11. Conclusion ____________________________________________________29
12. References _____________________________________________________31
2
1. Abstract
As modern communication demands become increasingly dependent on the rate
and quality of data transfer, engineers have invested interest in developing reliable high
speed data communication. This design class tries to meet these demands by developing
a short range 1000BASE-SX Gigabit Ethernet optoelectronic link that will operate at a
frequency of 1.25 GHz. In order to develop Gbps Ethernet, a transceiver board was
designed that can both send optical data (using VCSEL laser technology) and receive
optical data (using photodiode technology). The design process involved calculating the
laser bias currents necessary to drive the device while filtering and shielding circuits in
order to reduce noise to the system. In addition, the design had to be laid out in a
compact way in order to reduce the chance of creating transmission lines that could ruin
the sensitive signals. The completed design was ordered on a PCB board and the system
components were soldered to the board. The complete transceiver board was tested with
loop-back under varying attenuation. This report provides a thorough analysis of the
results and several debugging issues.
2. Introduction
2.1 General Background
Gbps Ethernet is a recent type of network based on a long standing history of
previous Ethernet standards dating back to 1973 [1]. In 1973 Xerox Corporation’s
Research Center in Palo Alto developed a bus topology LAN.
As the technology
developed, Xerox built a 2.94Mbps CSMA/CD system in 1976 that connected 100
personal workstations on a 1 kilometer cable [2]. As the need for this technology became
more demanding, Xerox teamed with Digital Equipment Corporation and Intel in 1980 to
develop a standard for 10Mbps Ethernet [2]. This technology was dubbed DIX Ethernet
(representing the initials of all three companies involved). DIX was the basis for the
current standard IEEE 802.3 Ethernet. As transfer speeds increased, approvals were set
for 10Base5 (1983), 10Base2 (1986), 10BaseT (1991), 10BaseF (1994), 100 Mbps
(1995), and finally the standard of Gigabit Ethernet in 1998 [1]. Although the type of
cable has changed over the years for transferring high speed data, Ethernet has retained
3
its name from ether, the single coaxial
cable used in Xerox’s original Ethernet
system. [1] The IEEE 802.3 standard is
the current standard for 1.25Gbps
Ethernet [6].
The design of our
optoelectronic link will follow the
IEEE 802.3 standard.
The basic
architecture of this standard can be
seen in Figure 2.1.1.
Basic architecture [5]
(Figure 2.1.1)
2.2 Board Elements
The optoelectronic board is essentially the Physical Media Dependent (PMD)
component of the 802.3z architecture. The main active components of the board are the
Vertical Cavity Surface Emitting Laser (VCSEL) used to transmit data and the
Photodiode (PD) used to receive data. The VCSEL is driven by the Maxim MAX3287
Laser Driver which takes a differential input and converts the signal into a current. The
current from the MAX3287 allows the VCSEL to produce high and low energy pulses of
850nm light. The light from the TX board is transmitted to the RX board via optical
fiber. The Photo Diode on the Rx board detects the incoming light and generates small
current signals.
The MAX 3266 Trans-impedance Amplifier (TIA) chip creates a
differential voltage from the incoming PD current. The MAX 3264 creates a digital
signal from the incoming analog voltage signal of the TIA by converting the signal to
ones and zeroes (high and low voltages).
The VCSEL is composed of layers of mirrors that are a result of semiconductors
sandwiched with varying composition. The mirrors are arranged
in a way to reflect light back into a central cavity. Since the
mirrors only reflect a narrow range of wavelengths, the
combined mirrors ensure only one wavelength of light is emitted
from the VCSEL. This light leaves the VCSEL vertically in a
cylindrical beam from the fabricated wafer [3].
4
Optek VSCEL [13] (Fig.2.2.1)
The Photodiode (PD) receives the incoming light
generated from the VCSEL. Since considerable light energy can
be lost through the transmission fiber, it is essential for the PD to
detect low power pulses of light. The responsivity value reveals
the amps of current generated from the input of light power (in
watts). In addition, it is important to note the capacitance of the
Typical Photodiodes [7]
(Fig 2.2.2)
PD and detector aperture. The capacitance influences the
response time necessary to detect high and low light, which is essential to note for high
speed communication [4]. The detector aperture is the area that the PD is able to detect
light over. A larger area means that your alignment does not have to be perfect for the
PD to work. The ideal PD for the optoelectronic link has a high responsivity, low
capacitance, and a large detector aperture [4]. Photodiodes are fabricated using P-type
and N-type semiconductors sandwiched together with an intrinsic layer between them.
For this reason they are usually referred to as PIN semiconductors.
3. Group Management Plan
3.1 Division of Labor
In order to ensure each project task is completed successfully, we organized our
group so that each member heads a division. Each member is expected to be responsible
for the timely completion of their division, in addition to ensuring that all members gain
experience by contributing resources to their division. In this way, all group members
will become familiar with the many disciplines of the optoelectronic project, while those
with the matching skills can make sure each subproject is completed on time. Table 2.4.1
shows our division of labor:
Group Member
Duties
Andrew Tupper
Transmitter/Receiver PCB design, Practice Board Testing
Ian
Transmitter/Receiver schematic design, Optical Link Budget
Tyler Helble
Parts/Vendor Management, Webmaster, Soldering
Ungtae Lee
Report Editor, Testing optoelectronic transceiver
Division of Labor (Table 2.4.1)
5
3.2 Time Management
A Gantt chart was created in order to subdivide tasks and keep the project
organized and on schedule. The project steps were organized in a way to maximize
working time by limiting the amount of downtime when parts and PCBs are waiting to be
delivered.
Our main problems have been waiting for supplies to arrive. First, the
evaluation board testing was delayed because we had to wait for an etching tool. Second,
the loop back test was delayed because we ran out of SMA connectors. But our biggest
problem in our project has been locating and ordering VCSELs. Aside from designing a
second design layout, our entire project was completed by our March 26th deadline.
Group 2 Gantt Chart - 1 Gbps Optical Ethernet
Jan
Project Steps:
1-10
11-20
Feb
21-31
1-10
11-20
M arch
21-29
background research (Jan 8 - Apr 13)
test eval board (Feb 5 - Feb 11)
Optical link budget (Feb 10 - Feb 19)
Choose parts (Feb 11 - Feb 19)
Order VCSEL/PD's (Feb 19 -Feb 25)
Build test board (Feb 13 - Feb 20)
Design Schematic (Feb 15 - Feb 22)
Board design (Feb 19 - March 2)
Design review (Feb 26 - March 4)
Order PCB's (March 5- March 14)
Spring Break (March 5 - March 14)
Construct Board (March 14 - March 21)
Testing/Troubleshooting (March 21 - March 28)
Design Modifications (April 1 - April 7)
Build second board (April 7 - April 13)
Final report (April13 - April 21)
Test (Feb 5)
Midterm Report (March 19)
Final Report (April 21)
Event
Projected Time
On time Progress
Overdue
6
1-10
11-20
April
21-31
1-10
11-20
21-30
3.3 Financial Budget
Each group is allocated $350.00 for the entire project. At this point, we have spent
a total of $238.47. This included all resistors, capacitors, Potentiometers, PCB Board,
PD’s and the VSCEL. While additional PD’s and VCSEL’s were purchased, they were
not included in the financial budget since they will be passed on to next year’s ECE 164
class.
Vendor
Digikey
Item Number
393-1158-1-ND
Shipped
100
Digikey
311-100CCT-ND
10
Digikey
311-115CCT-ND
10
Digikey
RR12Q24DCT-ND
10
Digikey
3296W-102-ND
5
Digikey
3296W-253-ND
5
Express PCB
Lasermate
Hamamatsu
Maxim IC’s
Maxim IC’s
Maxim IC’s
Jameco
Digikey
Murata
PCB Board
TLC-P85A416-3
S5973
MAX3287
MAX3264
MAX3266
145373
CP-002AHPJ-ND
BLM11HA102SG
3
2
2
1
1
1
4
1
50
Description
CAP 10000PF 50V
Ceramic
RES 100 OHM
1/8W SMD
RES 115 OHM
1/8W SMD
RES 24 OHM
1/10W SMD
POT 1.0K OHM
3/8” SQ
POT 25K OHM
3/8” SQ
PCB Board
VCSEL
Photodiode
Laser Driver
Limiting Amp
TIA
SMA Connectors
Power Connector
Murata Inductors
Unit Price
.0293
Amount $
2.93
.08
0.80
.08
0.80
.151
1.51
2.5
12.50
2.5
12.50
19.99
59.95
60.00
36.40
6.59
6.59
5.37
26.60
0.702
5.50
$238.47
$18.20
6.59
6.59
5.37
6.65
0.702
.11
Total
Financial Budget (Table 3.3.1)
3.4 Bill of Materials (BOM)
The Bill of Materials consists of all components necessary to fabricate a single
optical 1 Gbps Tx/Rx based on a 10,000 purchase order. The Maxim chips and PCB
board were based on a smaller order since precise large quantity ordering information
was unavailable. Overall, the precise of a single board turned out to be quite costly. The
majority of the expense can be attributed to the price of the VCSEL and PD.
Additionally, the SMA connectors from Jameco remained high in price despite the higher
quantity order.
7
Vendor
Digikey
Item Number
393-1158-1-ND
Used
18
Digikey
311-100CCT-ND
2
Digikey
311-115CCT-ND
2
Digikey
RR12Q24DCT-ND
1
Digikey
3296W-102-ND
1
Digikey
3296W-253-ND
1
Express PCB
Lasermate
Hamamatsu
Maxim IC’s
Maxim IC’s
Maxim IC’s
Jameco
Digikey
Murata
PCB Board
TLC-P85A416-3
S5973
MAX3287
MAX3264
MAX3266
145373
CP-002AHPJ-ND
BLM11HA102SG
1
1
1
1
1
1
4
1
9
Description
CAP 10000PF 50V
Ceramic
RES 100 OHM
1/8W SMD
RES 115 OHM
1/8W SMD
RES 24 OHM
1/10W SMD
POT 1.0K OHM
3/8” SQ
POT 25K OHM
3/8” SQ
PCB Board
VCSEL
Photodiode
Laser Driver
Limiting Amp
TIA
SMA Connectors
Power Connector
Murata Inductors
Unit Price
.014
0.252
.01682
0.03364
.01682
0.03364
.03190
0.0319
1.092
1.092
1.092
19.99
18.50
6.50
6.59
6.59
5.37
5.39
0.43
.045
TOTAL
1.092
19.99
18.50
6.50
6.59
6.59
5.37
21.56
0.43
0.405
$88.47
* two Tx/Rx can be fabricated on one PCB board. (Table 3.4.1)
4. Getting Started on the Project
4.1 Evaluation Board setup and testing
In order to become familiar with the lab equipment and better understand how an
electrical transmitter and receiver work, we first tested the Maxim 3287 evaluation board
(Figure 4.1.1). The SMA connector inputs were fed a PRBS7 signal from the GTS1250
signal generator.
The output was examined with the oscilloscope to ensure the
transmitter was working.
Next, the transmitter was connected in loop-back to the
receiver, and the output was connected to
the oscilloscope. A clean eye was observed
on the oscilloscope. Attenuation was added
in increments while the eye was observed on
the Tektronix oscilloscope.
The eye
diagrams are shown at 0, 40, and 50dB of
attenuation in Figure 4.1.2.
Maxim evaluation Board (Figure 4.1.1)
8
Loop back test with 0, 40, and 50dB attenuation (Figure 4.1.2)
Once we knew that the Tx/Rx worked under attenuation, we analyzed the bit error
rate by connecting the receiver to the Tektronix gigaBERT 1400 Analyzer. Our results
are shown in table 4.1.1.
Attenuation
BER
0-36 dB
0 E-9
37 dB
2E-8
40 dB
5.4 E-5 (failure)
50 dB
1.6 E-1 (total loss of signal)
BER for Evaluation Board under Attenuation (Table 4.1.1)
4.2 Test Board setup and testing
Before any consideration was given to designing the optoelectronic transceiver,
an all-electrical test board was built in order to
obtain a better understanding of how unit would
work.
This board had two main purposes; it
functioned as a reference layout, greatly facilitating
the design and debugging processes involved in
deriving the final transceiver; and it also served as an
introduction to the techniques of surface mount
soldering.
The electrical receiver was assembled first.
It was quickly discovered that the MAXIM chips
Completed electrical
Transceiver (Figure 4.2.1)
should be installed before any of the other
components, due to the multitude of extremely small
9
connections required to mount each integrated circuit.
When working with surface
mount components it is generally a good rule of thumb to mount them in decreasing order
of the precision required to mount each component. A photograph of the completed
electrical transceiver can be seen in figure 4.2.1.
The electrical receiver closely
resembles the receiver in the optical design, but with an SMA connector in place of the
photodiode. For testing, this SMA connector was fed a PRBS7 from the GTS1250 and
the output was examined on the oscilloscope. No detectable signal was present at the
output during initial testing of the receiver. Probing the board and comparing signals to
those on the evaluation board indicated that the MAXIM chips were simply not receiving
power. It was discovered that the power connectors that were installed were not the
compatible with the board design. They were removed and replaced with the correct
connectors and the board was retested. This time an eye was clearly present at the output.
The resultant eye was examined while the input to the receiver was progressively
attenuated electrically, starting at 0dB and increasing in 10dB increments until the signal
was lost. The scope was set to 2 seconds of persistence. The corresponding waveforms
can be seen in figure 4.2.2. It is interesting to note how bad the eye diagram looks for
0dB of attenuation (figure 4.2.2(a)). In fact, the eye looks much better in figure 4.2.2(b),
where the input is subjected to 10dB of attenuation. This is an indication that the receiver
is actually being overdriven. This is a result of the fact that the receiver is actually
designed to work with a certain level of fiber loss. Once the overdriving problem
disappears, the eye does not change significantly until the input is attenuated by
approximately 40dB, as in figure 4.2.2(e). At 50dB of attenuation the eye closes as the
signal is lost, as in figure 4.2.2(f). The bit error rate tester was used to determine exactly
when the signal received became so erroneous that it no longer met the specification in
the 802.3 standard. This error rate is indirectly set by the standard’s requirement that the
signal to noise ratio be 12, translating into a maximum error rate of 10-9. This error rate
was exceeded at and above 42dB of attenuation.
10
(a) 0dB of Attenuation
(d) 30dB of Attenuation
(b) 10dB of Attenuation
(e) 40dB of Attenuation
(c) 20dB of Attenuation
(f) 50dB of Attenuation
Electrical receiver output at varying attenuations (Figure 4.2.2)
Test Transmitter
Following the successful testing of the electrical receiver, assembly began on the
electrical transmitter, as seen on the right half of the board in figure 4.2.3. Unfortunately,
assembly was delayed due to an error in the transmitter side of the printed circuit board;
the output was shorted to ground. A picture of this serious error can be seen in figure
4.2.3(a). An engraver tool had to be used to separate the center pin from ground at both
the SMA outputs of the electrical transmitter. This caused significant delays, as the
11
testing could not be continued until the engraver was purchased. The correction can be
seen in figure 4.2.3(b).
(a)
(b)
Electric Transmitter PCB (a)error and (b)correction (Figure 4.2.3)
Once the engraving tool was used to separate output from ground on the electrical
transmitter, it was tested in much the same way as the electric receiver, with the
exception that the transmitter was supplied with differential inputs by the GTS1250.
While the transmitter did appear to be working, the
eye detected at its output was not very clean. The
oscilloscope seemed to be having trouble triggering
properly, as can be seen by the excessive amount of
jitter present in the waveform in figure 4.2.4.
Different attenuations were tried on the input to the
Electrical transmitter output with
0dB of attenuation (Figure 4.2.4)
receiver, but nothing seemed to help. However, when
the output of the electrical transmitter was connected
to the input of the receiver, and the receiver output is monitored by the scope, the eye
looks very clean. This seems to indicate that the test transmitter was, in fact, working
properly, and that the poor eye diagram is due to triggering problems with the scope. The
bit error rate for this loop back setup was also within the limitations set by the 802.3
standard.
This was considered to be acceptable evidence that the electrical test
transceiver did, indeed, work properly.
12
5. The Optical Link Budget
5.1 General Idea
There are a number of things to be considered when designing a Gbps Ethernet
compliant IEEE 802.3 optical link. The most important of these is selecting the correct
parts, including the VCSEL, photodiode, and potentiometers. An optical link budget is a
set of calculations based upon important parameters of the VCSEL and photodiode (for
example slope efficiency or responsivity) that allow us to tell if the parts we have chosen
will function properly in our circuit before they are actually installed.
Below is a
schematic diagram of all the dynamic parts involved in building the Gbps Ethernet
device.
Schematic Diagram of the Optical Link Budget [5] (Fig 5.1.1)
The MAX3287 laser driver drives the VCSEL with a DC bias current and AC
modulation current. The bias point lies halfway between Imax and Imin, and the
modulation current swings between Imax and Imin. The VCSEL then outputs laser light
through a fiber into the photodetector. The photodetector receives the optical power in
the form of laser light and converts it to current. This current drives the MAX3266 TIA.
The TIA is a transimpedance amplifier, which means that it converts current to voltage.
The TIA takes the current and converts it into differential output voltage. Then the
MAX3264 limiting amplifier converts the signal into a digital signal which can be
processed by a computer. The laser driver, TIA, and limiting amplifier have been chosen
for us, so our job is to determine the best VCSEL/photodiode combination for our
system.
13
5.2 Initial Power Calculations
To begin with we need to know what value of Pmax we want the VCSEL to output.
The eye safety spec is referenced in section 38.7.2 of the IEEE 802.3 standard [6]. It
refers to the maximum amount of laser light that the VCSEL can output and still be safe
to the eye. In this project we will use 1 mW as the maximum power. The next step in
creating our link budget is to compute the value of Pmin. To compute Pmin we use the
following equation:
Pmin = (Pmax)(10-(ER/10))
(Eq. 5.2.1)
Where Pmax is 1 mW and ER (extinction ratio) is 9 dB. These values can be obtained
from the 802.3 standard on page 1038 [8]. Plugging in these values, we compute Pmin to
be 0.1259 mW.
5.3 VCSEL Calculations
Figure 5.3.1 shows the VCSEL output power vs. input current (L-I) characteristic.
This curve shows how a VCSEL’s output power
will respond to changes in input current. From this
curve we determine all equations necessary to run
the four corners analysis, which will give us the
operating current range of a VCSEL. Since the
VCSEL L-I curve is roughly a straight line with a
slope η (slope efficiency) and an x-intercept of Ith,
the drive currents of the VCSEL is calculated from
VSCEL output power vs. input current
curve [5] (Fig 5.3.1)
the optical output power using the equation of a
straight line:
I = [P/ η] + Ith
14
(Eq. 5.3.1)
In order to operate at speed the VCSEL must be biased above threshold. To
calculate the maximum VCSEL drive current we use the equation:
Imax = [Pmax / η] + Ith
(Eq. 5.3.2)
To calculate the minimum VCSEL current we use a similar equation, but simply replace
Pmax with Pmin.
Imin = [Pmin / η] + Ith
(Eq. 5.3.3)
From the values of Imin and Imax, values for the bias current, Ibias, and the
modulation current, Imod, of the VCSEL can be determined. The bias current is the
current that lies halfway between Pmax and Pmin. The modulation current swings between
Imin and Imax.
Ibias = (Imax + Imin )/2
(Eq. 5.3.4)
Imod = (Imax - Imin )
(Eq. 5.3.5)
5.4 Four Corners Analysis
The VCSEL parameters generally have values that are min, typical, and max. A
four corners analysis is performed using the max value. This is to assure that the VCSEL
will function under the worst case scenario. Only one VCSEL, Lasermate TLC-P85A416
is used. Below are the parameters and four corners analysis of the Lasermate VCSEL.
Lasermate TLC-P85A416-3 VCSEL
Parameters
Parameter
Threshold Current (mA)
Slope Efficiency (mW/mA)
TLC-P85A416-3 parameters [10] (Table 5.4.1)
Symbol
Ith
η
VCSEL Current Requirements
I_th (mA)
eta (mW/mA)
I_tot,MAX (mA)
1.80
0.03
35.1333
1.80
0.15
8.4667
2.60
0.03
35.9333
2.60
0.15
9.2667
Four corner analysis on Lasermate VCSEL [10] (Table 5.4.2)
15
MIN
1.80
0.03
TYP
1.80
0.11
I_tot,MIN (mA)
5.9964
2.6393
6.7964
3.4393
MAX
2.60
0.15
I_bias (mA)
20.5649
5.5530
21.3649
6.3530
I_mod (mA)
29.1369
5.8274
29.1369
5.8274
5.5 Fiber Attenuation Calculations
The VCSEL outputs laser light into the fiber which is connected to the PD.
Unfortunately, as the laser light travels through the fiber it attenuates (loses power) so
that the actual amount of laser light that reaches the PD is only a fraction of what the
VCSEL actually output. In order to perform a proper four corners analysis of our
photodiodes we need to know the full range of powers that will reach the PD. To
calculate this range we use the following equation:
(Eq. 5.5.1)
Pat PD = (PVCSELout)(10-(fiber loss/10))
Where Pmax and Pmin will both separately be plugged into PVCSELout and the value
for fiber loss, 7.5 dB, is obtained from the 802.3 specification on page 1039 [8]. Plugging
in the values of Pmax = 1mW and Pmin = 0.1259 mW into Equation 5.5.1, we compute a
range of 0.02240 - .1778 mW.
5.6 Photodetector calculations & “four corners” analysis
The input power to the PD is multiplied by the PD responsivity to calculate the
output current from the PD into the TIA.
IPD = R * (Pat PD)
(Eq. 5.5.2)
In most cases PDs have maximum and minimum values of responsivity so a four
corners analysis must be undertaken to assure that at no point the PD is overdriving or
underdriving the TIA. The Hamamatsu photo detectors that we chose have only a typical
value for responsivity. So a full four corners analysis is unavailable.
Hamamatsu S7912 Photodetector
Parameters
Parameter
Responsivity (A/W)
Capacitance (pF)
Aperture Size (mm)
Dark Current (pA)
Hamamatsu PD parameters [9] (Table 5.6.1)
MIN
16
TYP
0.47
0.85
0.20
1.00
MAX
100.00
Hamamatsu Photodetector Output Currents
R (A/W)
I_o,MAX (mA)
0.47
0.083579132
0.47
0.083579132
Hamamatsu Four Corners (Table 5.6.4)
I_o, MIN (mA)
0.010521989
0.010521989
Finally, capacitance is an important parameter to check when picking a
photodiode. The capacitance determines the time delay of the signal and it should be
minimized to produce high speed signals. Based on the specifications for the MAX3266
TIA [12], a typical good capacitance value is around 0.85 pF or lower.
The point of calculating the four corner analysis is to choose the best VSCEL and
PD for our optoelectric transceiver. Unfortunately, we are limited to only the Hamamatsu
PD and Lasermate VSCEL. We have been unable to locate more 850nm VSCEL and
PD’s because many vendors have stopped producing these products.
6. Transceiver Design
6.1 Design Tools
Both circuit design and printed circuit board layout was performed using a free
CAD software package available for download at www.expresspcb.com. While this
software is not nearly as sophisticated as some of the more advanced design tools
available, expresspcb.com offers a quick turnaround and very reasonable prices. This
comprehensive package includes two key software tools; ExpressSCH version 4.1.2 and
ExpressPCB version 4.1.2. ExpressSCH is a relatively simple schematic design program
that made the process of designing the transmitter and receiver schematics, as well as
reviewing and editing them, a relatively simple one. ExpressPCB is a printed circuit
board layout program that shares a similarly simple interface with ExpressSCH.
ExpressPCB includes some very useful features that significantly streamline the process
of laying out a board. Probably the most useful feature is the ability to link a PCB layout
to a schematic diagram. Once the schematics for the transmitter and receiver had been
completed and checked for errors, they could be linked to the PCB layout so that
ExpressPCB could automatically check to make sure that the nodes in the schematic lined
up with the board layout. The actual designs will be discussed below.
17
6.2 Transmitter Schematic
The transmitter and receiver schematics, which can be seen in the figures below,
were designed independently of each other in order to simplify and expedite the process.
The transmitter consists of the MAX3287 LAN laser driver, a Lasermate VCSEL and a
number of passive components. This transmitter schematic was essentially derived from
the schematic included in the Maxim MAX3287 Evaluation Kit. The final schematic was
created by omitting a feedback loop photodiode, as well as a bias adjustment PNP
transistor that were present in the evaluation design.
The filter observed in the
transmitter schematic was added in an attempt to eliminate some of the interference
problems that arise with the use of a noisy power supply. Potentiometers were also added
so that fine adjustments could be made to the operating region of the VCSEL. It should
be noted that, while the transmitter and receiver schematics were drawn separately, they
are actually two parts of the same circuit, as they share a common power supply and their
ground plains are inductively coupled.
Transmitter Schematic (Fig. 6.2.1)
18
6.3 Receiver Schematic
The receiver circuit consists of the Maxim MAX3266 transimpedance amplifier,
the Maxim MAX3264 limiting amplifier, a Hamamatsu photodiode and a number of
passive components.
The receiver schematic was derived by making a few minor
modifications to the schematic used to construct the test receiver board. Because the test
board was electrical instead of optical, the electrical inputs were replaced by the
photodiode. A power filter was also added to the original design, again in an attempt to
eliminate interference on the power supply lines. Once more, while the two schematics
are shown separately here, they are in fact two parts to the same circuit. The V CC pin in
these schematics refers the same 5V power supply. While the two circuits do have their
own ground plane, the ground planes are inductively coupled. Separate ground planes
were created as another effort to eliminate cross talk between the transmitter and receiver.
Receiver Schematic (Fig. 6.3.1)
6.4 PCB Layout
Once the transmitter and receiver schematic diagrams had been completed and
checked for errors, they were linked to a printed circuit board layout in ExpressPCB.
19
Unfortunately designing a PCB in this case is not as simple as just trying to fit all of the
components onto the board. The goal of the transceiver is to be able to send a digital
signal at the rate of 1 gigabyte per second. A 1 Gbps data signal requires about a
500MHz square wave. In order to send a decent square wave it’s generally a good idea to
include the first five harmonics, meaning that in order to send a good 1 Gbps data signal,
it’s necessary to deal with frequencies in the 2.5GHz range. At this frequency traces
should be kept less than 4mm in length in order to prevent the traces from acting as
transmission lines. Furthermore, significant effort was spent attempting to make the
designs for the transmitter and receiver as symmetric as possible, particularly when
dealing with differential signals. By keeping differential signals in close proximity and
contained within symmetric traces, any interference picked up on those traces should be
common to both sides of the differential pair, thus making it relatively easy to eliminate
this noise when the signal is processed. Finally, 90 degree turns were avoided at all costs
in high frequency traces, in order to prevent signal reflection.
The transceiver (transmitter and receiver) PCB ended up being very compact, not
only because of the desire to shorten traces to prevent transmission line problems, but
also because it enabled two separate layouts to be included on each board. This made it
possible to attempt two different designs on the same board. The first design, which can
be seen in the figure below, is the primary layout. It should be noticed that all traces
except the power supply turn in only 45 degree angles. Hopefully this will prevent any
signal reflection in the high frequency connections.
20
Primary PCB layout (Fig. 6.4.1)
Also notice the large red line
surrounding the bulk of the receiver. This large copper trace is expected to act as a shield
to absorb some of the transmissions emanating from the transmitter and dispersing the
noise to ground via an inductor. One major problem with this design is that the spacing
between the VCSEL and the photodiode does not meet the specification for a Duplex SC
connector, the type that would typically be used for such an application. This is the
reason for the second, aggressive PCB layout, which can be seen in the following figure.
In this layout the photodiode has been moved closer to the VCSEL, and some of the
passive components that sat in-between the diodes in the primary design have been
moved out of the way. This is considered a more aggressive design because, while it
does achieve proper spacing, the extension of the wires connecting the photodiode to the
MAX3266 chip make it much more likely that a significant amount of interference or
cross-talk will be observed. However, if this design does work, it will be a significant
achievement, especially considering that this board is essentially a first draft.
While care was taken to use the shortest traces possible in high frequency signal
parts of the board, it was extremely difficult, and in some cases simply impossible to
keep all traces under 4mm in length. At this point, determining the effectiveness of the
Aggressive PCB Layout (Fig. 6.4.2)
21
layout will have to wait until the coming weeks when the boards are completely
assembled and tested. It will be interesting to see how much noise is observed and to
determine whether or not the receiver shield has any positive (or negative) effects. It may
be necessary to assemble a second copy of the board so that the transmitter and receiver
can be tested independently of one another.
7. Assembly
7.1 Non-aggressive primary design
After submitting the design layout online to ExpressPCB, we received the
fabricated board in just three days.
First we soldered the passives, Maxim
chips, and the VSCEL onto the nonaggressive, primary board. From an
Shorted Primary Design (Figure 7.1.2)
initial point of view, we made sure all
parts were soldered correctly and the
leads were touching at all points.
When we first powered up our
receiver, it did not work. Immediately
Initial Fabricated Board (Figure 7.1.1)
we
checked
and
re-checked
our
connections both to the signal inputs and the power supply, but after determining that our
connections were in order we moved on to examining the layout of the board itself for
errors. Our first intuition was to compare our receiver to that of the fully functioning
Maxim test board that we had assembled to hone our soldering skills. But before we even
got to this stage, we were able to locate a problem
When disconnecting our receiver from the DC power supply in order to connect
the Maxim board we noticed that the board was quite warm in the area adjacent to the
power supply (Figure 7.1.2). We then reconnected the DC power supply to the board and
confirmed (by physically touching the hot board) that one of the lines running off of the
power supply got quite hot when the board was powered up (Figure 7.1.2). A quick
22
inspection of the bottom of the board revealed that one of
our power lines running on the underside of the board
that was supposed to be isolated from the ground plane
was in fact connected directly to the ground plane. This
board error was due to a mistake in our schematic, where
we had placed the line closer to the ground plane than
was specified by PCB express.
Correcting the first board error was a simple
matter of using the etching tool, to separate the line from
the ground plane. The etching tool was a small tool that
acted like a tiny jackhammer, and it was used to
physically remove the metal of the ground plane, that
Shorted Primary Design (Figure 7.1.2)
connected the line to the ground plane, from the board.
Unfortunately,
even though the problem of the short to ground had
been fixed the receiver still did not function properly.
After again confirming the board was connected
Etching ground plane (Figure 7.1.3)
correctly we decided to go back to our original
troubleshooting idea and power up our MAXIM test board and compare the signals from
the boards at each node. To do this we connected both boards to a power supply, and
input signals into both of them. From that point we used the high frequency probe
connected to the oscilloscope to trace the power and signal connections on each board.
To trace the connections we had to probe
a node on the working MAXIM test
board, look at the signal on the
oscilloscope,
and
then
probe
the
analogous node on our receiver board
and compare that signal with the one we
got from the test board. We began by
tracing the line running from the power
supply of both boards to the power
Test output using the probe (Figure 7.1.4)
23
connections of both chips. The signal we got going from the power supply into each chip
was exactly the same in both boards. When we next moved on to the output side of the
MAXIM 3264 limiting amp we discovered that although the signal that we got on the test
board was a good eye, the signal that we got from our receiver was exactly the same as
the power supply signal that we were inputting into the board. In addition, we noticed
that the board in that area was again heating up whenever the power was connected.
We concluded that our problem had something to do with the output of the
MAXIM 3264 chip. Again, we physically touched our board to figure out exactly where
it was heating up. After several tries we eventually figured out that the MAXIM chip
itself, and the two decoupling capacitors directly to the right and left of it were the only
parts that heated up when the board was power up. As a result we began an intense
inspection of our soldering job and of the ground plane connections of our board around
those three parts. After more than an hour of looking for any sort of problem we had not
found a single solder bridge on our chip pins, physical connection to the ground plane, or
any other sort of identifiable error. Our next step was to take one of our unsoldered
receiver boards and one of the unsoldered MAXIM receiver boards and compare the two
to see if there were any differences that we could detect. Our logic was that our board
was already very similar to the MAXIM board, and
the MAXIM board worked, so any connection
differences between the two would probably lead us
to our error. We quickly discovered two very small,
but very significant differences in the boards.
On our board we had connected two pins,
numbers 15 and 7, to ground that were simply left
unconnected on the MAXIM board. Referring to
the MAXIM data sheet from the 3264 [14] chip we
soon discovered that pin 7 was the output current
level pin and that when pin 7 was left unconnected
the CML output current is approximately 16 mA,
but that when it is connected the CML output is
Showing removed pins 15 and 7
(Figure 7.1.5)
approximately 20 mA. Also, we learned that pin 15
24
was the squelch input, and that when disconnected the squelch is disabled, but when
connected to a high TTL level and LOS is asserted it forces the data outputs to static
levels. According to the data sheet pin 15 is also internally connected to Vcc. We
formed a theory that because pin 15 was internally connected to Vcc, and we had
connected pin 15 to ground that that connection was the source of our short. We also
figured that the chip will function properly when both pins are left unconnected, so we
decided to attempt to eliminate our unnecessary connections. But even after using the
etching tool to remove the pins from the chip, it did not solve our problem. We knew
then that the MAXIM 3264 must have been damaged by the initial short and was
nonfunctional.
7.2 Aggressive Design
Removing the MAXIM 3264 chip from our board and replacing it would have been
too tedious so we decided to move to our
aggressive design. Fortunately, this design
did not have the underside connection
grounded to the board like our primary
design.
We soldered only the passive
components on the aggressive design,
Initial Aggressive Design Board assembly
(Figure 7.2.1)
remembering to remove the leads that
connected pins 15 and 7 to ground. Once
powered, the aggressive design board did not heat up, so we knew there was no short.
Initial electrical testing of the transmitter showed promising results, so we completed the
transmitter assembly by soldering the VSCEL onto the board.
Next, we soldered all the passives and the PD on the receiver board. We connected it
to a power supply and used the pattern generator to input an optical signal. Unfortunately,
we did not get an eye using the oscilloscope. We knew there were no abnormal hot spots
on our aggressive design. So we went back to our comparison of the two boards, and
discovered that no recognizable signal was going into the MAXIM 3266 from the PD. A
quick inspection of the PD and the data sheet revealed that we had connected our PD
25
backwards. We had incorrectly assumed the
data sheet was a top view of the PD. Using the
solder sucker and a copious amount of solder
wick, we were finally able to dislodge our PD
and connect it properly. This turned out to be
the final correction that needed to be made to
our board.
Completed Design Board
(Figure 7.2.2)
8. Testing and Results
8.1 Optical Baseline testing
The following figures show results from Rx and Tx baseline testing. The Rx
board is receiving an optical signal from the pattern generator and transmitting an
electrical output into the oscilloscope. The Tx is receiving an electrical signal from the
pattern generator and transmitting an optical signal into the oscilloscope via the
transceiver module in the pattern generator.
(a) Tx Baseline without attenuation
(b) Tx Baseline with 5dB attenuation
(c) Rx Baseline without attenuation
(d) Rx Baseline with 5dB attenuation
Baseline testing at 2 sec persistence; PRBS7 data
(Figure 8.1.1)
26
8.2 Loop back testing
The loop back testing consists of connecting the optical output from our own
transmitter with the optical input from our own
receiver. Simply passing this test without optical
attenuation verifies that our transceiver is fully
functional. Figure 8.2.1 shows the setup of our
transceiver module. Notice the orange fiber output
from the connectorized VSCEL and the long fiber
input into the PD. Figures 8.2.2 (a)-(d) show the
results from the loop back tests under varying
Loop back testing setup (Figure 8.2.1)
power attenuation. Although the loop back testing
should work under 7.5dB of power attenuation, our transceiver failed at 5dB of
attenuation. It was unfortunate that we could not build a second transceiver design with
variations on spacing and a different combination of VSCEL and PD. We would be able
to compare results from a different board design and different manufacture of VSCELs
and PDs and possibly achieve better results.
(a) 0 dB optical attenuation
(b) 2 dB optical attenuation
(c) 3 dB optical attenuation
(d) 4 dB optical attenuation
Loop back testing at 2 sec persistence; PRBS7 data
(Figure 8.2.2)
27
At 0dB to -3dB, the Tektronix BER detector showed zero errors with a BER of
0.0 E-10 when configured to measure the error over one minute. At -4dB, the BER was
0.2 E-10, which still falls within the standards. At -5dB the BER detector could not detect
the signal from our transceiver. We see that jitter increases as optical attenuation is
increased. Although at -4dB there seems to be tremendous amount of jitter and a closed
eye, the BER still falls within the standards.
Throughout our measurements, we’ve set the optical output of our VSCEL
constant at 1mV. The optical power was measured using an optical power detector that
was in the lab. If we increased our optical output above 1mV, our transceiver would work
under higher attenuation.
9. Alignment Tolerance
Once we had established that our transmitter and receiver worked in conjunction
by doing the loop back tests (with and without attenuation), the next step was to perform
alignment tolerance tests. The purpose of the alignment tolerance test was to determine
how accurately a fiber had to be aligned with the detector aperture of the PD to get a
valid signal. Alignment tolerance testing was necessary because we had unconnectorized
PDs.
The first step in performing an alignment tolerance test was to connect the board
in loop back between our receiver board and transmitter board. The VCSEL was
connectorized so the optical fiber simply snaps onto it. The PD has a visible detector
aperture in which the laser light could be transmitted. In order to properly align the fiber
output to the detector aperture of the PD, we placed the fiber in the XYZ stage. Using the
oscilloscope, we positioned the fiber over the PD so that the maximum signal was
obtained. We determined that the max signal was located at x-value 6.70μ and y-value
3.70μ. From there we first tested the tolerance in the y-direction by moving the stage
both in the positive and negative y-direction until we lost the signal. We found the ydirection range to be between 3.35μ and 4.05μ. Next we moved the stage back to the
maximum point, and performed the exact same procedure in the x-direction to get the xdirection range between 6.40μ and 7.05μ. The final step in the alignment tolerance
28
testing was to obtain absolute x and y coordinates ranges. The tolerance in the ydirection was 0.70μ and the tolerance in the x-direction was 0.65μ.
There were two problems associated with our alignment tolerance testing, the first
of which was the excessive length of the fiber. Because the connectorized VCSEL and
PD were designed so closed together, the VSCEL connector was in the way of the XYZ
stage. We were forced to extend the length of the fiber that down from the XYZ stage to
overcome this problem. Unfortunately the excessive fiber length made it incredibly
sensitive to the smallest movement of the board or even a slight breeze. Any of these
changes could knock it out of alignment and give bad results. Even more distressing was
the fact that there was no visible scale on the XYZ stage. We estimated that one turn of
the knob on the stage corresponded to half a micron of movement. But upon discussion
with Professors Brooke and Jokerst, we realized how wrong our estimate was and that the
scale was probably closer to a twentieth or a half of a millimeter per turn. We were off by
several orders of magnitude.
As a result, we found the x and y tolerance to be
approximately 70μ and 65μ, respectively.
10. Crosstalk
Aluminum foil was inserted between the receiver and the transmitter during loop
back on the aggressive design to see if it stopped some crosstalk. We saw very little
difference in the output of the receiver whether or not the foil was present. Next, to verify
that the receiver was not getting crosstalk signal from the raw PRBS7 data, we tested the
output of the receiver with the transmitter operating and then with the transmitter not
operating. We found was no noticeable difference. Unfortunately, no quantitative testing
for cross talk could be performed with our transceiver; only visual comparisons could be
performed. Our visual evidence indicates minimal levels of crosstalk, which could be an
indication of effective integrated shielding.
11. Conclusion
We successfully tested the evaluation board and implemented and verified the
operation of the test board. We successfully designed our first Gbps Ethernet Optical
Transceiver printed circuit board with optical devices on-board and a shared power
29
supply. Using the ExpressPCB software, we then drew the layout and submitted the
design for fabrication. We also successfully ordered our passives and obtained VCSELs
and PDs. Once we received the PCB, we soldered a complete transceiver and tested it
under varying optical attenuation. We verified simultaneous operation of the transmitter
and receiver by performing loop back tests. Alignment tolerance tests were also
performed on PD of the receiver board. Unfortunately, we did not have enough time to
design a second board with improvements to fix mistakes on the first board design. We
could not try to optimize costs or design a more aggressive board that uses minimum area
and produce better results.
Achieving these goals and our getting results was a tremendous learning
experience. Debugging many of the problems was especially rewarding and we were able
to gain a deeper understanding of basic electrical engineering principals. Not only did we
learn the technical side of a design project, but we learned many other parts of designing
a project. These included interacting and ordering parts from vendors, communicating
between group members, dealing with management issues, meeting project deadlines,
presenting the project status, and most importantly, learning that something always goes
wrong. While this class has allowed us to gain hands-on knowledge of theoretical
concepts of engineering, producing our product from start to finish has also given us a
glimpse of the engineering industry.
30
12. References
[1] Tutorial: how optical Ethernet is disrupting the network marketplace: understanding
the causes, trends, and implications. Thatcher, J. Optical Fiber Communication
Conference and Exhibit, 2002. OFC 2002 , 17-22 Mar 2002. Pages:528
[2] Gigabit Ethernet. Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE
International Symposium on , 6-9 May 2001. Pages:9.4.1 - 9.4.16
[3] VCSEL research, development and applications at Honeywell. Morgan, R.A.
Vertical-Cavity Lasers, Technologies for a Global Information Infrastructure, WDM
Components Technology, Advanced Semiconductor Lasers ..., Gallium Nitride Materials,
Processing, ..., 1997 Digest of the IEEE/LEOS Summer Topical Meetings , 11-15 Aug.
1997. Pages:5 – 6
[4] The influence of photodiode design on receiver sensitivity. MacBean, M.D.A. Optical
Detectors, IEE Colloquium on , 19 Jan 1990. Pages:7/1 - 7/4
[5] Class notes. Handed out in class 2004 January
[6] IEEE, “802.3 IEEE Standard” [Online document], 2004 March 26, Available HTTP:
http://standards.ieee.org/
[7] Optek Technology, Inc. Website. Accessed March 20th 2004
http://www.optekinc.com.
[8] IEEXPLORE
http://ieeexplore.ieee.org/iel4/5830/15560/00720570.pdf?isNumber=15560&prod=STD&
arnumber=720570&arSt=&ared=&arAuthor= (Page 108)
[9] Hamamatsu Data Sheet
http://www.hpk.co.jp/Eng/products/ssd/pdf/s7911_s7912_kpin1041e02.pdf
[10] Lasermate Data Sheet http://www.lasermate.com/tlcp85a4x6-3.html
[11] OSI Data Sheet http://www.osifibercomm.com/data/silicon/850nm-1.25Gbps.pdf
[12] Maxim Data Sheet http://pdfserv.maxim-ic.com/en/ds/MAX3266-MAX3267.pdf
[13] VCSEL picture www.root.cz/clanek/1420
[14] Maxim Data Sheet http://pdfserv.maxim-ic.com/en/ds/MAX3264-MAX3765.pdf
31