Download Power electronic interface developed to manage power flows and

Power electronic interface developed to manage power flows and inefficiencies in
Smart Grid Applications
J.C. Alfonso-Gil1, H. Beltran1, E. Pérez1 and C. Ariño1
1
Dpt. Industrial Systems Engineering and Design
E.S.T.C.E. - Universitat Jaume I
Av. Sos Baynat s/n, E-12071 Castelló de la Plana (Spain)
Phone/Fax number: +0034 964 728178, e-mail: [email protected]
Energy storage systems, Buck and Boost converter, smart
grids, renewable production planning.
1. Introduction
Due to the huge deployment of new electric
generation technologies and multiple types of loads, the
electric power system has been evolving during the last
years. The new electric grid topology that is gaining more
and more supporters is based on decentralized generation
with high penetration of renewable energy sources as
well as the apparition of microgrids and Smart Grids [1].
This new topology allows reducing, among others, the
electric power transportation losses, as it has already
been demonstrated by some authors [2]. Smart Grids will
play an important role in maintaining reliability of the
supply by continuously monitoring and controlling the
grid as well as the local generators’ production and the
local loads’ demand [3]. This functionality is important
because in such a scenario, the power quality can be
noted as one of the most important issues worldwide due
to its influence on the nation’s economies.
One of the most important elements to make Smart
Grids technically viable is the so-called Shunt Active
Power Compensator (SAPC). This type of converter, for
which an example of structure and control is defined in
Fig. 1, is the one in charge of supplying to the Smart Grid
all those non-efficient currents connected with the local
reactive power, harmonic distortion, unbalances, etc…
preventing the electrical grid from transporting them [4].
vsA vsB vsC
uA
i*A
i*B
i*C
iA iB iC
uB
uC
SPWM
Key words
In this sense, the SAPC transforms the whole Smart Grid
into an ideal generator or resistive load (depending on the
sense of the power exchanged between the main grid and
the Smart Grid). However, depending on the SAPC rated
power and energy capacity, it can happen that some
inefficiencies are not compensable [5]. When this is the
case, a selective SAPC, which only compensates some of
the inefficiencies, is desirable [6]. Also, the SAPC can
provide or store for a while the energy required by the
Smart Grid to perform the local generation-load balance,
if this is desired, to work isolated from the main grid.
Both functionalities obviously depend on the amount of
energy storage introduced in the SAPC, storage which is
normally connected to the dc bus of this power converter.
This is the key and interest of this work. Different types
of dc/dc topologies are already introduced in the
literature [7] to combine energy storage systems and
connect them to some kind of SAPC. A new one is
proposed and analysed in this paper providing successful
response results.
The organization of the paper is as follows. First,
section 2 presents the power management system
structure and summarizes the buck and boost operation
modes of the converter. In section 3 , the control of the
power management system (The current and voltage
controllers of boost and buck) is developed using the
frequency analysis. From the transfer function of the
boost and buck converters and the proposed current and
voltage controllers, the current control loop and voltage
control loop are analyzed. After that, the phase and gain
margins are adjusted in order to achieve good stability
and dynamic response of the converters. Also, the
parameters of current and voltage controller are obtained.
Thereafter, some simulation results representing the
performance of the system under different operation
conditions are introduced in section 3. Finally, some
conclusion remarks are discussed in section 4.
Controller
Abstract. This paper presents a power management system
developed to operate on the dc side of a SAPC allowing this
type of active filter to operate in smart grid applications and
integrating some type of energy storage system. The power
management system consists of a bidirectional dc-dc converter
which presents two boost cascaded stages in one sense and a
buck converter in the other sense. The two cascaded boosts are
used to raise the voltage from the 60V operation voltage level
of the batteries to the 300 V required at the input of SAPC (dc
bus) to enable it to deliver energy to the smart grid. Conversely,
the buck converter is used the other way round to reduce the
voltage to 60V and allow storing energy from the smart grid
into the batteries, and super-capacitors, when required. To
achieve a good performance of the power management system,
a cascaded control integrating a current and a voltage loop are
implemented. The frequency method is used to design the
regulators achieving a good trade-off between stability and
dynamic response. Finally, simulation results confirm the
goodness of the design which provides low current ripples and
stable dc voltages that assure proper charge and discharge
processes, the key to guarantee a long life for the batteries.
SA
L
viA RA A
SB
viB RB
LB
viC RC
LC
SC
iA
iB
iC
PCC
vsC
Vdc-Bus=300V
Bidirectional
DC/DC converter
(Buck and Boost)
vsB
vsA
125V
400V
POWER
MANAGEMENT
SYSTEM
Vdc=60V
S. Capacitor
Batteries
GRID
Fig. 1 Block diagram of the SAPC with the power management
system
2. Power management system
The power management system proposed in this work
and used to connect the energy storage unit with the
SAPC consists of two cascaded boost converters and a
buck converter. Its topology is represented in Fig. 2.
The first boost converter (boost 1) is formed by L1,
T3, D1, and the capacitor C1. This converter can raise the
60V operation voltage of super-capacitors and batteries
up to 120V, which is the input voltage to the second
boost converter (boost 2). This one comprises L2, T4, D2
and the capacitor C2. Boost 2 allows raising the 120V to
300V, which is the connection inverter’s input voltage.
Equation (1) shows the ideal transfer function of a boost
converter:
Vout =
Vin
1− D
(1)
where Vout is the output voltage, Vin is the input
voltage and D is the duty cycle (D = Ton/T). Considering
the voltage relations required in boost 1 and 2, the duty
cycles are fixed as D = 0.5 and D = 0.6, respectively.
These duty cycles guarantee the linearity of the transfer
function (1) for its entire operating range due to the effect
of the resistance of the input inductor [11].
iL
d
Vout
Iref
Fig. 3 Average Current-mode Control (ACC) of boost converter
Fig. 4 shows the control loop defined to control the
current in the inductor by means of the duty cycle.
Iref
d
iL
Fig. 4 Current loop control
ILDboost (s) is the transfer function described in (3)
[11]. The values considered in this transfer function for
each of the two boost converters are shown in TABLE I. Ri
is the current sensor gain and Fm is the gain of the PWM
modulator, whose values are also displayed at the bottom
of TABLE I.
Fig. 2 Proposed power management system’s structure
Conversely, a buck converter is used to reduce the dc
voltage from the inverter dc bus at 300V to the 60V
batteries’ voltage. Because the buck converter
configuration has no limitations on the duty cycle as the
boost converters do, there is no need to use the two buck
converters. Then, the buck converter used is formed by
T2, L2, L1, D4, D3, C1 and the storage system (supercapacitors and batteries). In this case, T1 remains “on”
continuously throughout the buck mode to allow the flow
of power from the input to the storage system. According
to the theoretical equation in (2), the duty cycle of the
buck converter is D = 0.2.
Vout = Vin ⋅ D
A.
(2)
Boost control
Two control loops have been used to control the
output voltage of the two-stage boost converter: a current
inner loop to control the average current in the input
inductor and an external loop to control the output
voltage of the converter. These loops are shown in Fig. 3.
With these two control loops, the system feedbacks the
two state variables of the power circuit and, in this way, a
better performance than with a single voltage loop is
achieved. This control method is called Average Currentmode Control (ACC) [9].
2Vin
RC 

1 + s

(1 − D ) LRC 
2 
ILDboost ( s ) =
R 
(1 − D ) 2
 1
s2 + 
+ (1 − D ) 2 c  s +
L
LC
 RC
(3)
Gcboost (4), is the transfer function of the ACC current
regulator used to control the boost converter proposed in
[11]. The regulator has an integrating factor ωi/s to
achieve an error signal equal to zero. It also presents a
zero to cancel the negative phase introduced by the
integrator and a high-frequency pole to immunize it from
the switching noise [10].
s
1+
ωic
ω zc
Gcboost ( s ) =
(4)
s 1+ s
ω pc
To make the current regulator design, the current loop
gain defined in (5) has been considered, since the
characteristics of the closed-loop converter depend on the
loop gain. Loop characteristics are determined by the
transfer functions ILDboost(s) and Gcboost(s), provided that
Fm and Ri are constants.
Ti ( s ) = Fm ⋅ Ri ⋅ ILDboost ( s ) ⋅ Gcboost ( s )
(5)
Fig 6 shows the bode diagram of the current loop
(open loop) obtained after adjusting the current regulator
Gcboost(s). The adjustment has been made seeking a
balance between the dynamic response of the system and
stability of the control loop. Equation (6) shows the
resulting current controller using a gain margin greater
than 50dB and a phase margin of 35°.
s 

1+

14000 
3030


Gcboost ( s ) =
s 
s 1+


 158730 
(6)
way, the zero does not affect the phase of the loop gain at
the crossover frequency. Finally, the values of ωi and ωzv
have been defined to achieve a phase margin of 50° (see
Fig. 6). Equation (10) shows the resulting expression of
the voltage controller.


10  3s + 150 

Gvboost ( s ) = 
s 1+ s 


 1500 
After setting the current loop, it was time for the
voltage loop definition. Fig. 5 shows the loop used to
control the output voltage of the converter by means of
the duty cycle. The inner current loop has been neglected
in this diagram because it is much faster (see Fig. 6) and
can be assumed to be a unity gain block.
d
TABLE I
Parameter values used for boost 1 and boost 2
vout
Parameter
Vin
Value
Description
60V
Imput Voltage
Vout
120V
Output Voltage
D
0.5
Duty Cycle
Boost 1
L
1.5mH
C
2200µF
Equation (7) shows the transfer function of the boost
converter used to control the output voltage by means of
the duty cycle Avboost(s) [11]. In this case, β is the gain of
the voltage sensor and assumes a value defined in TABLE
I.
Boost 2
(7)
ESR of capacitor
2.4 Ω
R
Fig. 5 Voltage loop control
Inductor
Output capacitor
100mΩ
Rc

s  
s  2
1 +
 ⋅ 1 −
 ⋅ w n
w
w
zv 2 
Av boost ( s ) = Kd ⋅  2 zv1  
s + 2 ⋅ ζ ⋅ wn ⋅ s + w 2 n
(10)
Load (Vout / Iout)
Vin
120V
Imput Voltage
Vout
300V
Output Voltage
D
0.6
Duty Cycle
L
7.5mH
C
2200µF
inductor
Output capacitor
100mΩ
Rc
ESR of capacitor
R
15 Ω
Load (Vout / Iout)
Fs
10kHz
Switching frequency
Gain of voltage sensor
where:
wzv1 =
1
Rc ⋅ C
Both
(1 − D) 2
w zv 2 =
⋅R
L
1
wn =
⋅ (1 − D )
LC
ζ =
1
Gain of current sensor
Fm
1
Gain of PWM modulator
150
Open current loop of Boost 1
Open voltage loop of boost 1
100
Vin
Kd =
(1 − D ) 2
Magnitude (dB)
50
The voltage regulator Gvboost, shown in (8), presents a
very similar structure to that of the current controller. In
this case, the pole of the voltage regulator compensates
the effect of the non-minimum phase zero (ωzv2) existing
in the transfer function of the boost converter (7).
Fc=36 kHz
0
-50
Fc=94.4 Hz
-100
-150
360
(8)
270
Phase (deg)
180
The voltage loop gain defined in (9) has been used to
adjust the voltage regulator. As it was the case for the
current loop, the voltage loop characteristics are
determined again by the transfer functions AVboost(s) and
Gvboost(s).
Tv ( s ) = β ⋅ FM ⋅ Avboost ⋅ Gvboost ( s)
0.0125
Bode Diagram
1
1
⋅
2 ⋅ wn R ⋅ C

s 
 1 +

w
wi 
zv 
Gvboost ( s ) =
⋅
s 

1 + s 
 w 
pv 

β
Ri
PM=252º
90
0
PM=35º
-90
-180
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
Frequency (Hz)
(9)
To define the voltage regulator, a crossover frequency
of less than one quarter of the frequency of the nonminimum phase zero (ωzv2) has been considered. In this
Fig. 6 Bode diagram of voltage and current loops for boost 1
To calculate the current and voltage regulators of the
boost 2 converter, the same procedure was completed.
Fig. 7 shows the bode plot of the voltage and current
loops of boost 1 and 2. The discrepancy in the bonds of
voltage and current for each of the converters, is because
the duty cycles do not coincide among boosts (D = 0.5
for boost 1and D = 0.6 for boost 2).
wzv1 =
1
Rc ⋅ C
wn =
1
LC
Bode Diagram
150
Open current loop of Boost 1
Open current loop of Boost 2
Open voltage loop of Boost 1
Open voltage loop of Boost 2
100
50
Magnitude (dB)
where:
Fc =22 kHz
ζ =
Fc =36 kHz
The values of the parameters used in the transfer
functions for the current (11) and voltage control (12) are
shown in TABLE II. Also note that the structure of the
current and voltage regulators defined for the buck
converter are those used for the regulators of the boost
converter, shown in (4) and (8) respectively.
0
-50
Fc =64.6 Hz
Fc =94.4 Hz
-100
-150
360
TABLE II
270
PM = 245º
Parameter values used for buck converter
PM = 252º
180
Phase (deg)
1  1 Rc 
⋅
⋅ 
2 ⋅ wn  R ⋅ C L 
90
0
PM = 50º
PM = 35º
Parameter
Vin
Value
300V
Description
Imput Voltage
Vout
60V
Output Voltage
D
0.2
Duty Cycle
-90
-180
-270
-1
0
10
1
10
2
10
10
3
4
10
5
10
6
10
10
Frequency (Hz)
Fig. 7 Bode diagram of voltage and current loops for boosts
Buck
1&2
B.
Buck control
Fig. 8 shows the ACC block diagram used to control the
output voltage of the buck converter. As in the case of
boost converter, this uses two control loops: an inner loop
to control the average current in the inductor and an
external loop to control the output voltage of the
converter.
Buck
d
T2
T1
iL
Vin
vout
L2
C2
D4
L1
C1
L
9 mH
C
4400µF
Output capacitor
Inductor
Rc
50mΩ
ESR of capacitor
R
0.6 Ω
Load (Vout / Iout)
Fs
10kHz
Switching frequency
β
0.0125
Gain of voltage sensor
Ri
1
Gain of current sensor
Fm
1
Gain of PWM modulator
The adjustment of the current and voltage regulators
of the buck converter has been made considering the
frequency characteristics of their corresponding current
and voltage loops. Poles of the regulators have been set
to eliminate the effect of the capacitor ESR zero. The ωi
values have been adjusted to find a balance between the
dynamic response and the control loop stability.
Super
Capacitor
Bode Diagram
200
Open current loop of Buck
D3
Open voltage loop of Buck
150
Batteries
100
Fc=92kHz
Tv(s)
Ri
Gcbuck(s)
+
Iref
Gvbuck(s)
Magnitude (dB)
Fm
Ti(s)
+ Vref
50
0
-50
Fig. 8 Average Current Control (ACC) mode of buck converter
Fc=170Hz
-100
ILDbuck ( s ) =
Vin (1 + sRC )
R LCs 2 + L s + 1
R

s  2
Vin 1 +
 w n
w
zv1 
Av buck ( s ) = 2 
s + 2 ⋅ ζ ⋅ wn ⋅ s + w 2 n
-150
-200
0
-45
-90
Phase (deg)
In order to calculate the current and voltage regulators
for each of the loops, the same procedure described in the
previous section for the boost converter has been
completed. To do so, the transfer functions used to
control current and voltage of the boost converter in
Figures 4 and 5 are replaced by those defined in
equations (11) and (12) for the buck converter.
-135
PM=58o
-180
(11)
-225
PM=260
-270
-1
10
(12)
0
10
1
10
2
10
3
10
4
10
5
10
6
10
Frequency (Hz)
Fig. 9 Bode diagram of the control loops of the buck converter


50  4000 + 1.33s 


Gcbuck ( s ) =
s
s  1+


160000 

(13)


30  100 + 2.5s 

Gvbuck ( s ) = 
s  1+ s 


1500 

200
Output Voltage of Boost 1 (V)
Fig. 9 shows the diagrams of the current and voltage
loop gains of the buck converter with which the
regulators shown in equations (13) and (14) have
obtained, respectively.
180
160
140
120
100
80
60
Output Voltage of Boost 2 (V)
1
g
1
2
+
-
[V 1]
v
+
1
g
g
1
[PWM1]
+
-
2
2
Bat
[A 2]
[A1]
num (s)
num (s)
den (s)
Pulses Duty
num (s)
[PWM1]
den (s)
Puls es Duty
den (s)
[V3]
den (s)
-K-
[V2]
V_Ref_Boost2
-K -
V _Ref_Boost1
[A 3]
num (s)
-K-
[V 1]
den (s)
num (s)
[PWM 3]
0
0.5
1
1.5
Time (s)
2
2.5
3
280
260
Pulses Duty
V_Ref _Buck
den (s)
Fig. 10 Model of the power management system in
Matlab-Simulink®
The upper part in Fig. 10 depicts the power
conversion stages of the converter while the lower part
represents the control schemes used to manage the
system. In this sense, the control of boost 1 measures the
current through the input inductor [A1] and the output
voltage [V2]. Then, it introduces these measures in the
regulators, introduced in the previous section, which
provide the control signals [PWM1]. Similarly, the
control of the boost 2 measures the current [A2], the
voltage [V3] and generates the modulated signal
[PWM2]. On other hand, the buck converter’s control
measures the current [A3], the voltage [V1], and
generates the pulses [PWM3]. In this operation mode,
given that the buck converter presents one single stage,
the another transistor remains always turned “on”.
The simulated results represented in Fig. 11 show the
voltage variations experienced by the two dc output
voltages produced by both boost stages (from 60V to
120V and from 120V to 300V) .
In order to analyze the dynamic response of the
converter, different load steps have been simulated. The
first one, in t=1s, changes from half load to full load
(50% step). Then, at t=2s the converter is forced to regain
the half load operation condition. Results for the boost
and buck responses under these casuistic are represented
in Fig. 12 and Fig. 13, respectively. The first of them
presents the boost 1 input current variations as well as the
boost 2 output voltage oscillations. The 98% response
time (ts98) turns to be 200ms and the overshoot equals
12.14%. In the same way, the input current ripple (being
drained from the batteries) at full load operation
conditions is equal to 1.4 A peak to peak, what just
represents 1.37% of the converter full load current.
150
Input DC current (A)
v
[V 2]
i
-
+
100
50
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
time (s)
2
2.5
3
340
Output DC voltage (V)
g
2
i
-
num (s)
3
Fig. 11 Output voltage of boost 1 (upper) and boost 2
(lower) responses for a 50% load step
[A1]
[PWM2]
2.5
[A 2]
i
-
[PWM2]
2
300
[V 3]
[On ]
+
1.5
320
240
[A3]
1
340
A set of simulations has been performed in order to
check the validity of the proposed power management
system. In Fig. 10 is shown the Matlab-Simulink®
software used to test the model of the energy
management system.
[PWM3]
0.5
(14)
3. Simulation results
+
v
-
0
320
300
280
260
240
Fig. 12 Input current (upper) of boost 1 and output dc voltage
(lower) of boost 2 responses for a 50% load step
To analyze the behavior of the buck converter, as in
the previous case, two load steps of 50% were simulated
(Fig. 13). In this case, the ts98 is 120ms and the output
current ripple (injected into the batteries) at full load is
0.4 Amps peak to peak, corresponding to 0.4% of the full
load current of the converter. Such a reduced value of the
output current ripple in the case of the buck converter is
achieved thanks to the series connection of the two
inductors used in boost converter. Moreover, no
overshoot is experienced in this case thanks to the
addition of the capacities of batteries and capacitors,
what allows damping the voltage variations.
Acknowledgement
This work was supported by project P1·1A2011-12 of the
Fundació Caixa Castelló-Bancaixa.
References
[1]
Jiyuan Fan and S. Borlase, “The evolution of distribution,”
IEEE Trans on Power and Energy Magazine, vol. 7, pp.
63-68, 2009.
[2]
E. Belenguer, H. Beltran and N. Aparicio, “Distributed
generation power inverters as shunt active power filters for
losses minimization in the distribution network” Power
Electronics and Applications, 2007 European Conference
on, 2007, pp. 1-10.
[3]
S. Bruno, S. Lamonaca, G. Rotondo, U. Stecchi and M. La
Scala, “Unbalanced Three-Phase Optimal Power Flow for
Smart Grids,” Industrial Electronics, IEEE Transactions
on, vol. 58, pp. 4504-4513, 2011.
[4]
S. Orts-Grau, F.J. Gimeno-Sales, A. Abellán-García, S.
Segui-Chilet, J.C. Alfonso-Gil, “Improved Shunt Active
Power Compensator for IEEE Standard 1459
Compliance,” IEEE Trans. Power Del., vol. 25, no. 4, pp.
2692–2701, Oct. 2010.
[5]
J. C. Alfonso-Gil, C. Ariño, H. Beltrán, E. Pérez,
“Comparative Study of Current Controllers for Shunt
Active Power Compensators used in Smart Grid
Applications”, International Conference on Renewable
Energies and Power Quality (ICREPQ’13), Bilbao
(Spain), 20th to 22th March, 2013
[6]
S. Orts-Grau, F. J. Gimeno-Sales, A. Abellán-García, S.
Seguí-Chilet, M. Alcañiz-Fillol, R. Masot-Peris, “Selective
shunt active power compensator applied in four-wire
electrical systems based on IEEE Std. 1459,” IEEE Trans.
Power Del., vol. 23, no. 4, pp. 2563-2574, Oct. 2008.
[7]
O. Laldin, M. Moshirvaziri and O. Trescases, “Predictive
Algorithm for Optimizing Power Flow in Hybrid
Ultracapacitor/Battery Storage Systems for Light Electric
Vehicles,” Power Electronics, IEEE Transactions on, vol.
28, pp. 3882-3895, 2013.
[8]
H. Beltrán, R. Vidal, J. C. Alfonso-Gil, C. Ariño, E. Pérez,
E. Belenguer “Influence of the State-of-Charge Control on
the Size of the Energy Storage Systems to be introduced in
PV Power Plants”, International Conference on Renewable
Energies and Power Quality (ICREPQ’13), Bilbao
(Spain), 20th to 22th March, 2013
[9]
Feng Yu ; Lee, F.C. ; Mattavelli, P., “A small signal model
for average current mode control based on describing
function approach”, Energy Conversion Congress and
Exposition (ECCE), 2011 IEEE, 17-22 Sept. 2011.
Output DC current (A)
150
100
50
0
0
0.5
1
1.5
2
2.5
3
Output DC voltage (V)
90
80
70
60
50
40
30
0
0.5
1
1.5
Time (s)
2
2.5
3
Fig. 13 Output current (upper) and dc voltage (lower) responses
of the buck converter for a 50% load step
4. Conclusion
This paper introduces the power management system
developed in order to enable the energy control of a
SAPC in microgrid or smart grid applications. The
proposed topology allows raising the dc voltage from the
60V level settled by the batteries used as energy storage
system to 300V, which is the dc input voltage used by the
SAPC to be able to drop energy into the microgrid. To do
so, the converter has a double configuration with a
double stage boost structure for the step up conversion
and a buck structure for the step down conversion, which
is active when some energy has to be stored in the
batteries. The two boost stages connected in series are
current and voltage controlled, successively, providing an
output dc voltage with low harmonic content in the
connection inductor. For the case of the buck
configuration, also a current and a voltage control loops
allow reducing the dc voltage with one single transistor
(one buck). The simulations performed and introduced in
this paper confirm the proper operation of such a
topology in both operation modes. For both of them, the
resulting full load current ripple values are particularly
low, what grants a good performance and protection of
the batteries.
[10] Sun pil Kim ; Jin-Sung Choi ; Feel-soon Kang, “Average
current mode controlled step-up converter employing
interleaved structure to obtain higher dc-link voltage”,
Vehicle Power and Propulsion Conference (VPPC), 2012
IEEE, 9-12 Oct. 2012.
[11] Garcera, G., Pascual, M., Figueres, E., “Robust average
current-mode control of multimodule parallel DC-DC
PWM converter systems with improved dynamic
response,” IEEE Transactions on Industrial Electronics,
vol. 48, no. 5, pp. 995-1005, Oct. 2001.