Download Study of the current±voltage characteristics in MOS capacitors with

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Solid-State Electronics 43 (1999) 555±563
Study of the current±voltage characteristics in MOS
capacitors with Si-implanted gate oxide
Etsumasa Kameda a, Toshihiro Matsuda b, Yoshiko Emura b,
Takashi Ohzone b, *
a
Department of Electrical Engineering, Toyama National College of Technology, Hongo-cho 13, Toyama 939, Japan
Department of Electronics and Informatics, Toyama Prefectural University, Kurokawa, Kosugi-machi, Imizu-gun,
Toyama 939-0398, Japan
b
Received 25 May 1998; received in revised form 31 August 1998
Abstract
The speci®c gate current density (JG) versus voltage (VG) characteristics of MOS capacitors with 50 nm thick,
implanted SiO2 (using various Si doses between 1013 and 3 1016 cmÿ2) have been studied under inversion and
accumulation conditions. From an analysis of dynamic resistance and current humps in the JG±VG characteristics of
the above devices, a qualitative model of the conduction mechanism has been proposed. Major current components
in the model are the following: a direct tunnel current of electrons and holes related to traps generated by Siimplantation, a charging current of electrons and holes to traps distributed a little inside the gate oxide, a trapassisted current and a Fowler±Nordheim tunnel current. The model can explain the JG±VG curves and the change
of the JG±VG characteristics on the basis of the Si atomic distribution in the gate oxide. # 1999 Elsevier
Science Ltd. All rights reserved.
1. Introduction
A MOS capacitor with heavy Si-implanted SiO2
exhibits hysteresis in the current±voltage (I±V) curve
and can be applied as a non-stacked EEPROM or
¯ash memory [1±10]. The memory e€ect of the Siimplanted SiO2 is believed to be due to a trap-like
behavior of excess Si atoms [2, 6]. Recently it was
reported that the Si-implanted MOS capacitor emits
visible electroluminescence and is useful as a light emitting device which has process compatibility with Si
LSI [11, 12]. In a series of I±V measurements of Siimplanted MOS devices, unusual I±V characteristics in
comparison with unimplanted MOS devices have been
observed in the low voltage region [1±4]. A negative
dynamic resistance is observed at a gate bias higher
than threshold voltage. Since direct tunneling of elec-
* Corresponding author. Tel.: +81-766-56-7500/501; fax:
+81-766-56-6172; e-mail: [email protected]
trons from the Si conduction band to the neutral trap
level above the Si conduction band edge in part of the
oxide occurs [1, 2], the neutral trap level generated by
the Si-implantation into the gate oxide may be responsible. A current hump dependent on the Si-dose and
the implantation energy is also observed [3, 4]. Under
accumulation conditions, n-type Si shows a dynamic
negative resistance due to direct tunneling from the Si
conduction band to neutral traps [1, 2], and p-type Si
produces a current hump dependent on the Si-implantation condition [3, 4]. In the high voltage region, several current humps, which depend on the Siimplantation condition, appear under both accumulation and inversion. Although the unusual I±V
characteristics of the Si-implanted SiO2 have not been
studied extensively until now, a basic study of the I±V
characteristics is necessary to understand the conduction mechanisms in SiO2 as well as to develop superior
memory devices and electroluminescent devices.
In this paper, unusual I±V characteristics of MOS
capacitors with a 50 nm thick SiO2 with a Si-implan-
0038-1101/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved.
PII: S 0 0 3 8 - 1 1 0 1 ( 9 8 ) 0 0 2 9 9 - 8
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E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
tation dose higher than 1 1016 cmÿ2 at 20, 25 and 50
keV have been studied to analyze the conduction
mechanisms under both accumulation and inversion.
2. Test devices
The Si-implanted MOS capacitors were made
according to the description in Ref. [4]. Five kinds of
Si-implanted MOS capacitors are summarized in
Table 1 [12]. The MOS capacitors for inversion
measurements are surrounded by n +-regions to form
the inversion layers under the MOS capacitors, while
those for accumulation measurements have no n +regions [4]. The area of the MOS capacitor is 0.48
mm2 for the accumulation condition (i.e., under negative gate voltages ÿVG), and 0.13 mm2 for the inversion condition (i.e., under positive gate voltage +VG).
I±V characteristics were measured using a micromanipulator probe station in the shield box and a precision semiconductor parameter analyzer HP4156A.
Each I±V measurement was performed using a new
device to avoid stress e€ects associated with the preceded bias sweep especially for high VG supply over 5
V. A boron channel-dose of the measured devices was
6 1011 cmÿ2 unless otherwise mentioned.
3. Experimental results and discussion
3.1. Transient I±V characteristics
Fig. 1 gives the JG±VG curves of MOS capacitors
under (a) accumulation and (b) inversion. The VG
ramp rate was 0.07 V sÿ1. In contrast to the devices
without Si-implantation, the Si-implanted devices have
a distinct JG±VG characteristics with a region of negative dynamic resistance and current hump. A current
¯ow model will be extracted with an analysis of the
unusual characteristics.
The transient current characteristics measured
during the application of a VG pulse from 20.5 to 240
V for 100 s to a typical sample from #25-2 are given in
Fig. 1. JG±VG characteristics of MOS capacitors under
(a) accumulation and (b) inversion. The VG ramp rate was
0.07 V sÿ1.
Fig. 2 under (a) accumulation and (b) inversion. The
charging current has three kinds of time dependent
components depending on VG. The ®rst charging current decays faster than t ÿ1 (where t is time) at VG less
than ÿ0.5 (+4) V, and the second charging current
decays nearly proportional to t ÿ1 at VG between ÿ2
and ÿ15 V (+5± + 10 V) for accumulation (inver-
Table 1
Summary of the test MOS capacitors
Sample No.
Implantation energy (keV)
Dose of Si ion (1016 cmÿ2)
Position of projected range Rp
0
25-1
25-2
25-3
20-1
50-1
none
25
25
25
20
50
none
1
2
3
1
1
none
center of gate oxide
center of gate oxide
center of gate oxide
shifted to poly-Si side from the center
near Si and gate oxide interface
E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
557
3.2. The ®rst and the second charging current at low VG
Fig. 2. Transient charging current characteristics of a MOS
capacitor (#25-2) under (a) accumulation and (b) inversion.
sion). When the charging voltage for the t ÿ1 current
decay has been removed, a transient discharge current
with t ÿ1 decay, in a direction opposite to that of the
charging current, is observed [13±17]. Therefore the
second charging current may be a trap charging and
discharging current [13±16]. The third charging current
at a voltage higher than ÿ15 (+15) V is almost constant, indicating that a d.c. current such as a Fowler±
Nordheim (FN) tunnel current is the dominant conduction mechanism [13, 17]. However a high 2VG
value induces a constant voltage±stress for the capacitors and thus the currents decrease gradually [18]. The
sudden current decrease observed in Fig. 2(a) at
VG= ÿ 15 V is reproducible and may correspond to a
change of conduction mechanism from a FN current
to a charging current into traps in the SiO2 (to be
described in Fig. 6(a)). The three kinds of charging
currents will be discussed in more detail in the following sections.
Fig. 3(a) and (b) give the JG±VG characteristics of
fresh MOS capacitors for accumulation and inversion,
respectively, at VG below 25 V. VG ramp rates were
0.1, 0.01 and 0.001 V sÿ1. The charging current
decreased signi®cantly with a slower VG ramp rate.
Concerning the ®rst charging current with a decay faster than t ÿ1, a clear negative dynamic resistance
characteristics is observed as shown in Fig. 3(b) for
samples #25-1, 2 and 3 under inversion at VG ramp
rates of 0.1 and 0.01 V sÿ1. These characteristics correspond to those reported in Refs. [1, 2], in which a
negative dynamic resistance was observed at a VG
ramp rate of 0.4 V sÿ1 and which have been explained
by a current reduction due to a decrease of the neutral
trap level below the Si conduction band edge with
increasing VG. To con®rm the current conduction
mechanism, the threshold voltage VT dependence of
the JG±VG curves is given in Fig. 4 for devices with a
boron channel dose of 4 1011 cmÿ2 (VT=0.4 V),
6 1011 cmÿ2 (VT=0.7 V), 8 1011 cmÿ2 (VT=0.85
V) and 10 1011 cmÿ2 (VT=1.0 V). The currents start
to decrease near a VG value corresponding to each VT.
Consequently, electrons in the inversion layer begin to
tunnel into the neutral traps in the SiO2 close to the
Si±SiO2 interface, and a tunnel current ¯ows until the
traps are full. The total tunnel current depends on the
trap density generated by the Si-implantation, owing
to the fact that for the same Si-dose the current shows
a similar shape as given in Fig. 4 and becomes broader
with an increase of the Si-dose as shown in the upper
or the middle ®gures of Fig. 3(b). In addition
Refs. [1, 2] reported another dynamic negative resistance observed in a MOS capacitor on n-Si under accumulation. The negative resistance was attributed to
electron direct tunneling from the Si conduction band
to neutral traps. In our experiments under accumulation, two kinds of negative dynamic resistance are
observed typically for sample #50-1 as presented in
Fig. 3(a); one at VG below ÿ1 V, which as shown in
Fig. 2(a) decays faster than t ÿ1, and another at VG
around ÿ2 V.
Fig. 5 gives a schematic energy-band diagram (a)
[(c)] of a MOS capacitor [19] to explain the conduction
mechanism, and the current components (b) [(d)] corresponding to each current mechanism at low VG under
accumulation [inversion]. The Fermi level EF and the
energy bandgap Eg of the n +-polysilicon gate are
assumed to be at the conduction-band edge EC [20]
and to be about 1.1 eV which corresponds to that of
single-crystalline Si. The trap level Ete represents a
trap level caused by an oxide de®ciency of SiO2 or by
Si-implantation, which is located 2.0±2.5 eV [21] or
about 3.0 eV [2] below the SiO2 conduction-band, respectively. However which Ete level contributes to the
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E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
Fig. 3. VG ramp rate dependence of the JG±VG characteristics at 0.1, 0.01 and 0.001 V sÿ1 under (a) accumulation and (b) inversion.
conduction mechanism is not clear. Implanted Si pro®les with a dose of 1 1016 cmÿ2 at 20, 25 and 50
keV, which pro®les are closely related to the trap densities, are indicated in the lower part of the SiO2 region
of Fig. 5(a) and (c).
The experimental results given in Fig. 3(a) under accumulation can be explained by a combination of
three current components indicated in Fig. 5(b); a current A, B and C corresponding to a VG value of about
ÿ1 V, ÿ2 V and beyond about ÿ3 V, respectively.
E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
Fig. 4. Threshold voltage VT dependence of JG ±VG characteristics for #25-2 at a VG ramp rate of 0.01 V sÿ1 under inversion.
559
Current A decays faster than t ÿ1 and its shape
becomes broader as the Si-dose becomes higher; typically with #25-3>#25-2>#25-1. Current A of device
#20-1 is larger than that of #25-1/#50-1 at VG=0 V
and decreases steeply at about ÿ2 V. These characteristics suggest that current A is related to the Si-dose
with a conduction mechanism due to the polysilicon±
SiO2 interface. Therefore a direct tunnel current of
electrons from the n +-polysilicon gate into Ete is proposed as indicated in Fig. 5(a). However current A
cannot explain the relatively high JG of sample #50-1
around VG= ÿ 0.5 V, which current may be caused by
another conduction mechanism near the Si±SiO2 interface. Current B observed in sample #50-1 is larger
than for #25-3/2, and is scarcely observed in #25-1 and
#20-1. It suggests that current B is closely related to
the Si-dose with a conduction mechanism near the Si±
Fig. 5. Schematic diagrams of conduction mechanisms in a MOS capacitor under low gate bias for (a) accumulation and (c) inversion. EC, EV and EF refer to conduction band, valence band and the Fermi level energy of Si, respectively. Energy values are indicated in eV. (b) and (d) show current components ¯owing under accumulation and inversion, respectively.
560
E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
SiO2 interface. The proposed conduction mechanism of
current B is a direct tunnel current of holes from the
accumulated p-Si surface into a hole trap level Eth,
which is located close to the Si±SiO2 interface, especially for #50-1, as shown in Fig. 5(a). Though we
have no evidence of Eth, the fast erase/write characteristics support the existence of both Ete and Eth [6].
Furthermore, it has been reported that both electron
and hole traps are existing in a Si3N4 ®lm [22]. Current
C increases in the order of #25-3>#25-2>#50-1>#251>#20-1 (i.e., current C is related to the Si-dose and
its pro®le). Current C has a characteristic similar to a
low-level leakage current through a thin oxide induced
by the excess high voltage stress (i.e., a charging and
discharging current which decays proportional to t ÿ1,
eventually drops to zero, and depends on the VG ramp
rate) [13±16]. Consequently, current C may be a charging current of electrons and holes into Ete and Eth,
respectively. In contrast to the traps related to the
direct tunnel currents A and B, the traps contributing
to current C are distributed a little away from the
interface of the polysilicon±SiO2 and the Si±SiO2 as
shown in Fig. 5(a).
The currents given in Fig. 3(b) and Fig. 4 under
inversion are schematically divided into two current
components; a current A 0 around VG=1 V, which
decays faster than t ÿ1, and a current C 0 beyond about
3 V, which decays nearly with t ÿ1. Current A 0
increased with the Si-dose (i.e., #25-3>#25-2>#25-1)
and was scarcely observed in #20-1. The shape of current A 0 becomes broader as the Si-dose increases.
Furthermore VG at the beginning of current A 0
depends on the VT value as described in Fig. 4.
Consequently current A 0 is closely related to the Sipro®le with a conduction mechanism due to the Si±
SiO2 interface. The proposed current A 0 mechanism is
a direct tunnel current of electrons in the inversion
layer into Ete located close to the Si±SiO2 interface.
Although current C 0 increased according to #253>#25-2, it was hardly observed in device #25-1/#501, and was scarcely measured in #20-1. Current C 0
may be caused by a charging current of electrons in
the inversion layer into Ete located a little distant from
the Si±SiO2 interface as shown in Fig. 5(c). Although a
tunnel conduction mechanism between the Si-substrate
and nano-crystals formed by heavy Si-implantation
into SiO2 [10, 23] is not discussed in this paper, this
mechanism may a€ect the current conduction especially at low VG for the heavily implanted MOS capacitors. In our electroluminescence measurements, the
samples #25-2/3 showed infrared light emission which
might be related to the Si nano-crystals [11].
Consequently, there may be a possibility that currents
A/B/A 0 are related to the nano-crystals, which are
Fig. 6. Schematic diagrams of conduction mechanisms in a MOS capacitor under high gate bias for (a) accumulation and
(b) inversion.
E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
located near the Si±SiO2 interface and which can trap
both electrons and holes.
3.3. The third d.c. current at high VG
Current JG at VG beyond ÿ15 V (accumulation) and
beyond +10 V (inversion) which are almost independent of VG charging time as shown in Fig. 2, will be
discussed making use of a schematic diagram of a
MOS capacitor given in Fig. 6 for (a) accumulation
and (b) inversion. FB is the barrier height between the
Si conduction-band and the SiO2 conduction-band.
Three current mechanisms are possible in the high VG
region; currents a/a 0 represent FN tunneling of electrons from the polysilicon/inverted p-Si into the SiO2
conduction-band, currents b1/b2 represent trap-assisted
electron tunneling from the conduction band/valence
band of the polysilicon into the SiO2 conductionband [19, 22, 24±34], the b1 0 /b2 0 currents are similar to
b1/b2 currents except that electrons come from the conduction band/valence band of the p-Si substrate, and
current c represents trap assisted hole tunneling from
the accumulated p-Si to the SiO2 valence-band.
However, FN tunneling of holes to the SiO2 valenceband may be negligible due to the higher barrier-height
of 4.6 eV for holes compared to 3.6 eV for electrons as
shown in Fig. 5(a).
Regarding accumulation, the JG±VG curves of
sample #0 can be explained by current a [4]. The JG±
VG curves of the Si-implanted MOS capacitors can be
roughly explained by a FN current with lower FB
dependent on the Si-dose and the implantation
energy [4]. The FB lowering has also been observed in
SILC (stress induced leakage current), in which the FB
lowering was attributed to a trap-assisted tunnel
current [33, 34]. The VG value corresponding to a steep
JG increase from current C to a FN current observed
around ÿ20 V depends on the Si-dose. These data
suggest that FB is e€ectively lowered by the trapassisted tunnel current b which is related to the trap
distribution generated by the Si-implantation as indicated in Fig. 6(b). The VG value of sample #50-1 is a
little higher than for #20-1, and thus current b may be
mainly determined by electron tunneling from the gate,
and a trap-assisted hole current c may scarcely contribute. The saturating JG curves of #25 and #20 around
VG= ÿ 10± ÿ 20 V in Fig. 1(a) may be related to an
electric ®eld lowering near the gate as indicated by a
dotted line in Fig. 6(a). It is caused by the trapped
electrons around the center SiO2 region due to current
C. The curves of samples #20-1 and #50-1 crossing at
VG around ÿ40 V are also explained by the higher
electric ®eld of #50-1 near the gate, which is modulated by hole traps near the Si±SiO2 interface as indicated by a dashed line for #50-1 in Fig. 6(a).
561
At inversion, the JG±VG curve of #0 is a current of
type a 0 and those for Si-implanted samples are also
given by the FN currents with variable FB [4] as is the
case under accumulation. The steep JG increase at VG
values around +10 V, which depends on the Si-implantation condition, is also explained by the current
of type b 0 as shown in Fig. 6(b). The experimental
result that in contrast to the accumulation condition
the VG value of #50-1 is lower than for #20-1 can be
explained by the higher trap density near the Si±SiO2
interface for #50-1. The saturating curves of Siimplanted samples which are more gentle in comparison with the steep JG increase of #0 are explained by a
lowering of the electric ®eld near the Si±SiO2 interface
modi®ed by the trapped electrons as indicated by a
dotted line (#25-1) and a dashed line (#50-1) of
Fig. 6(b). Samples #25-2/3 show clear two current
humps around +20 and +40 V under inversion, compare Fig. 1(b). The ®rst hump current may be related
to current b 0 . Current b 0 begins to ¯ow from the lower
trap density region when VG becomes sucient to support the trap-assisted current, and steeply increases
until the trap density reaches the peak density. Then
the increasing rate of current b 0 becomes gentle owing
to the fact that the trap density decreases, and ®nally
current b 0 gives a saturating curve due to the disappearance of the traps. However a curve of the second
current hump c 0 cannot be explained; it may also be
related to the distributed traps induced by the Si-implantation which causes another electron tunneling
mechanism such as a multi-trap path [29, 33]. The Siimplanted MOS capacitors show very complicated JG±
VG curves, particularly for sample #50-1 under both
accumulation and inversion. To understand the JG±VG
characteristics quantitatively, a computer simulation
may be useful. The ®rst JG±VG simulation for a Siimplanted MOS capacitor has been reported in
Refs. [1, 2], which did not contain trap-assisted tunneling. An improved computer simulation, which includes
all conduction mechanisms described in this paper,
may be useful to further understand the detailed conduction mechanisms in SiO2 as well as to describe the
JG±VG characteristics of MOS capacitors for applications of nonvolatile memory and light emitting
devices.
4. Conclusion
Fig. 7 gives a survey of the proposed conduction
mechanisms for Si-implanted MOS capacitors under
(a) accumulation and (b) inversion; the related current
contributions are as follows:
. At A: a direct tunnel current of electrons ¯ows from
the n +-polysilicon gate into Ete traps generated by
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E. Kameda et al. / Solid-State Electronics 43 (1999) 555±563
from the Si±SiO2 interface than the traps related to
A 0 current.
. At a 0 : a Fowler±Nordheim electron tunnel-current
from p-Si.
. At b 0 : a Ete trap-assisted tunnel current of electrons
from the inversion layer and the valence band of pSi.
. At c 0 : an electron tunnel-current assisted by a multitrap path or other tunnel current?
Though the real JG±VG curves are relatively complex in comparison with those given in Fig. 7, the currents ¯owing in the above MOS capacitors can be
qualitatively explained by a combination of the currents mentioned above. A computer simulation which
contains all conduction mechanisms described above
may be useful for a quantitative analysis of the JG±VG
characteristics of the MOS capacitors.
Acknowledgements
The authors would like to thank Dr. T. Takemoto,
K. Kagawa and Dr. T. Hori of the Semiconductor
Research Center, Matsushita Electric Ind. Co., Ltd.
for their continuous encouragement and providing the
experimental devices.
References
Fig. 7. A summary of proposed conduction mechanisms for
Si-implanted MOS capacitors under (a) accumulation and (b)
inversion.
.
.
.
.
.
.
Si-implantation, which exist in the SiO2 close to the
polysilicon±SiO2 interface.
At B: a direct tunnel current of holes ¯ows from the
accumulated p-Si surface into Eth traps, which are
close to the Si±SiO2 interface.
At C: a charging current of electrons and holes
¯ows to Ete/Eth traps distributed a little further
from the polysilicon±SiO2 and the Si±SiO2 interface
than the traps related to A/B currents.
At a: a Fowler±Nordheim electron tunnel-current
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At b: a Ete trap-assisted tunnel current of electrons
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At A 0 : a direct tunnel current of electrons in the
inverted p-Si ¯ows into Ete traps closely located near
the Si±SiO2 interface.
At C 0 : a charging current of electrons in the inverted
p-Si ¯ows to Ete traps distributed a little further
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