Download Design optimizations of phase noise, power consumption and

Vol. 34, No. 9
Journal of Semiconductors
September 2013
Design optimizations of phase noise, power consumption and frequency tuning
for VCO
Chen Nan(陈楠), Diao Shengxi(刁盛锡)Ž , Huang Lu(黄鲁), Bai Xuefei(白雪飞),
and Lin Fujiang(林福江)
Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027, China
Abstract: To meet the requirements of the low power Zigbee system, VCO design optimizations of phase noise,
power consumption and frequency tuning are discussed in this paper. Both flicker noise of tail bias transistors and
up-conversion of flicker noise from cross-coupled pair are reduced by improved self-switched biasing technology,
leading to low close-in phase noise. Low power is achieved by low supply voltage and triode region biasing. To
linearly tune the frequency and get constant gain, distributed varactor structure is adopted. The proposed VCO is
fabricated in SMIC 0.18-m CMOS process. The measured linear tuning range is from 2.38 to 2.61 GHz. The
oscillator exhibits low phase noise of –77.5 dBc/Hz and –122.8 dBc/Hz at 10 kHz and 1 MHz offset, respectively,
at 2.55 GHz oscillation frequency while dissipating 2.7 mA from 1.2 V supply voltage, which well meet design
specifications.
Key words: VCO; flicker noise; tuning characteristics; low power
DOI: 10.1088/1674-4926/34/9/095009
EEACC: 2570
1. Introduction
Wireless communication systems including wireless sensor networks lead to a huge market of RF CMOS circuits, and
the circuits with less power consumption are more competitive.
The Zigbee transceiver aims at low power applications, whose
operation frequency range is 2.4–2.485 GHz. The voltage controlled oscillator (VCO) performs frequency modulation in the
transmitter and the local oscillator (LO) in the receiver, whose
power dissipation is limited by 3.6 mW in our Zigbee project,
and the phase noise at 10 kHz and 1 MHz could not be larger
than –70 dBc/Hz and –120 dBc/Hz, respectively. When VCO
is used in the frequency synthesizer for the receiver, the frequency tuning is expected to be linear. It is challenging to design such low phase noise VCO with low power, while the area
could not be too large for cost consideration.
Among various studies of VCO in the last ten years, LC
VCO has been widely adopted in Giga Hz frequency and
beyond for its better noise performance than ring oscillator and others. Figure 1(a) shows the conventional LC VCO
with tail current source. The current source NM0 is biased
by fixed voltage and operates in the saturation region. The
current is well controlled, but noise coupled in through the
gate of NM0 and the current source becomes a main contributor of phase noise. Obviously it also reduces voltage
headroom, which is not good for low voltage supply application. To reduce phase noise, current source is removed, as
shown in Fig. 1(b), and the voltage headroom is maximized.
However, the power consumption increases, and the absence
of high impedance in the tail leads transistors in the triode
region to load the resonator. Reference [1] proposed a filtering technique to lower phase noise effectively by adding
an LC tank oscillating in second harmonic at the tail node,
but the additional inductor and capacitor consume a large
area.
The main sources of phase noise in VCO are thermal
noise and flicker noise of MOSFETs. To reduce close-in phase
noise, people pay more attention to flicker noiseŒ2 5 . Especially in deep submicron or nano-scale CMOS process, flicker
noise plays a significant role in phase noise as device size reduces significantlyŒ6 . It is straightforward to reduce flicker
noise by large transistor size and small transconductanceŒ7 .
However, large size transistors limit the frequency tuning
range, and the start-up condition is difficult to meet for small
transconductance. So, further study for flicker noise reduction
is needed.
Flicker noise of the transistor can be reduced by switching on and off periodically, as shown in Fig. 2, which will
lessen “long-term memory” physicallyŒ2; 3 . This switched biasing technology is applied to differential VCOŒ4 and quadrature VCOŒ5 , which reduces phase noise effectively at the cost
of more than two times power consumption.
The varactors in VCOs shown in Fig. 1 usually leads to
non-linear frequency tuning characteristics and variation of
gain, which could not fit our design requirement, thus additional technology should be used.
In this paper, self-switched biasing technology and a decoupling capacitor are used to reduce flicker noise from tail
bias transistors and suppress noise up-conversion from the
cross-coupled pair, which also helps to produce a low power
design by exploiting its operation feature. Linearized tuning characteristics are achieved by distributed biasing varactors.
* Project supported by the National Science and Technology Major Project, China (No. 2009ZX03006 009) and the USTC and IMECAS
Jointed Lab Micro-/Nano-Electronic System Integration R&D Center (MESIC).
† Corresponding author. Email: [email protected]
Received 3 February 2013, revised manuscript received 19 March 2013
© 2013 Chinese Institute of Electronics
095009-1
J. Semicond. 2013, 34(9)
Chen Nan et al.
Fig. 1. Conventional LC VCOs. (a) With tail current source. (b) Without tail current source.
Fig. 3. Proposed VCO with phase noise reduction.
Fig. 2. Cycling switched MOSFET.
2. Circuits design and optimizations
2.1. Phase noise reduction
Based on previous discussions, a differential LC VCO with
low phase noise is proposed as shown in Fig. 3. Complementary differential typology is adopted, where cross-coupled pairs
NM1, NM2 and PM1, PM2 supply negative resistance; NM3,
NM4 work as tail bias transistors.
Coupling capacitors C1 , C2 provide AC path for switched
biasing, by which the oscillation output voltage VOC, VO
inject into the gate of tail current transistors NM3, NM4, thus
the gate voltage of NM3, NM4 varies according to oscillation
voltage, and they are switched on and off periodically. DC bias
of the gate voltage is given by VB , which is used to set the operation state of tail bias transistors. From noise contributions of
Cadence Spectre simulation, intrinsic flicker noise in tail bias
transistors is reduced significantly.
Up-conversion of flicker noise from the cross-coupled pair
also impacts phase noise, including indirect FM by nonlinearity of the transistorŒ7 , AM–PM conversion by nonlinearity of
the varactorsŒ8 , and second harmonic modulation at the tail capacitorŒ9 . To suppress flicker noise up-conversion, decoupling
capacitor C0 is inserted between source nodes of NM1, NM2.
According to Ref. [9], C0 will create a fundamental frequency
component, whose amplitude would be comparable with the
second harmonic component at the source if it is with proper
capacitance. This can decouple the fluctuating offset voltage
across the source of the cross-coupled pair, thus flicker noise
no longer modulates the second harmonic at source node, and
the up-conversion of flicker noise from the cross-coupled pair
will be suppressed.
C3 , C4 are parallel with Cgs of NM3, NM4, which perform
low pass filtering with R1 , R2 , and the noise from the bias path
Fig. 4. Simulated phase noise of conventional VCO and proposed.
is filtered out, leading to better phase noise at 1 MHz offset. The
capacitance should not be too large, otherwise the impedance
of the tail bias transistor would decrease, and the quality factor
Q of the resonator would be degraded as cross-couple transistors in triode regionŒ1 .
Simulated phase noise of conventional VCO (Fig. 1(a))
and proposed (Fig. 3) are shown in Fig. 4. For fair comparison, they work at the same oscillation frequency and dissipate
the same power. There is about 11 dB improvement of phase
noise at 10 kHz offset by the proposed, and 4 dB improvement
at 1 MHz offset. The significant improvement of close-in phase
noise, which is dominated by flicker noise, confirms the positive effect of proposed VCO for flicker noise reduction.
2.2. Power consumption optimization
For self-switched biasing oscillator (shown in Fig. 3), the
gate-source voltage of the tail current transistor is a summation
of DC bias VB and oscillation signal,
095009-2
Vgs3 .t/ D VB C A cos !o t;
(1)
J. Semicond. 2013, 34(9)
Chen Nan et al.
Fig. 5. Model of transistor in triode region with two saturated transistors.
Fig. 7. (a) LC tank with traditional single biasing. (b) Its conceptual
C –V characteristic.
region with the same size, as shown in Fig. 5. The current of
NM3 in the triode region is given by
0
.t/ D Ia .t /
Id3
Ib .t/;
(5)
where Ia .t/ and Ib .t/ are current of transistors in saturation:
Ia .t/ D
D
Ib .t / D
Fig. 6. Simulated average drain current of NM3 for saturation and
triode region.
D
1
ˇŒVB C A cos.!o t/
2
Vth 2 ;
(2)
. The average current generated in NM3
where ˇ D n COX W
L
is derived as
Z
1 T
1
1
Id3 D
Id3 .t/dt D ˇ.VB Vth /2 C ˇA2 :
(3)
T 0
2
4
The second term contributes additional current dissipation, thus the total power consumption increases significantly
with large switching amplitude A. However, sufficient switching of the tail current transistor between strong inversion and
accumulation is useful to reduce intrinsic flicker noise effectivelyŒ5 . Thus trade-off between phase noise and power consumption is the main limitation of self-switched biasing technology.
To get lower power, supply voltage is pulled down, resulting in the tail bias transistor operating in the triode region rather
than the saturation region. The current of NM3 in the triode region is given by
0
Id3
.t / D
1
ˇVds3 Œ2.VB C A cos.!o t/
2
Vth /
Vds3 :
(4)
In Ref. [6], a long channel transistor in the triode region
is modeled by two back-to-back transistors in the saturation
Vth /2
1
ˇŒVB C A cos.!o t /
2
1
ˇ.Vgd3
2
Vth 2 ;
(6)
Vth /2
1
ˇŒVB C A cos.!o t /
2
The average value of Ia is
Z
1 T
1
Ia D
Ia .t/dt D ˇ.VB
T 0
2
where A is amplitude of switching signal of NM3, which is determined by oscillation amplitude and capacitor ratio, and !o is
oscillation frequency. Firstly, we assume the tail bias transistor
operates in saturation region, and the current dissipation is
Id3 .t / D
1
ˇ.Vgs3
2
Vds3
Vth 2 :
1
Vth /2 C ˇA2 :
4
(7)
(8)
As the variation of Vds3 is small when NM3 is in the triode
region, and for the sake of simplicity, suppose Vds3 is constant,
then use its average value Vds3 to derive the average value of
Ib as
Z
1 T
1
1
Ib D
Ib .t /dt ˇ.VB Vth Vds3 /2 C ˇA2 : (9)
T 0
2
4
Thus the average current of NM3 in the triode region is
0
Id3
D Ia
Ib
1
ˇ.VB
2
Vth /2
1
ˇ.VB
2
Vth
Vds3 /2 :
(10)
Although the estimation of Eq. (10) is based on not so strict
assumption, the results could help us to inspect the power consumption. Compared to Eq. (3), the current dissipation for triode operation in Eq. (10) does not depend on switching amplitude A, thus power consumption should be reduced. The simulated average current of NM3 in saturation and triode region
are illustrated in Fig. 6, where the different switching swing
2A is realized by a different proportion of capacitors, while
keeping constant oscillation amplitude and the same oscillation frequency. Obviously, the current in saturation is much
larger than that in the triode region, and the strong dependence
on switching swing almost vanishes as depicted in Eq. (10).
095009-3
J. Semicond. 2013, 34(9)
Chen Nan et al.
Fig. 9. Switched capacitor array.
Fig. 8. (a) LC tank with distributed biasing. (b) Its conceptual C –V
characteristic.
2.3. Tuning characteristics linearization
Frequency tuning characteristic is another important feature when VCO is used in PLL. The loop gain of PLL will
change with the variation of VCO gain, which may deteriorate
the stability and phase noise performance of PLL.
VCO gain is given by
KVCO D
@!o
@!o @Cvar
D
;
@Vctl
@Cvar @Vctl
(11)
where Cvar is capacitance of varactor, Vctl is control voltage,
and !o is oscillation frequency as
1
!o D p
;
L.Co C Cvar /
Fig. 10. Micrograph of proposed oscillator.
(12)
where L is inductance of tank, and Co is fixed capacitance of
tank. Thus VCO gain can be written as
KVCO D
1
!o
@Cvar
:
2 Co C Cvar @Vctl
(13)
Obviously, VCO gain is determined by C –V gain of varactor @Cvar /@Vctl .
Usually, the varactor is biased by a single reference voltage
Vref1 as shown in Fig. 7(a), and its C –V curve is exhibited in
Fig. 7(b). Since the C –V curve of the varactor is linear in limited range LR , and flat in rest control voltage range, the VCO
gain is non-linear according to Eq. (13) in the whole voltage
tuning range.
To solve the problem, distributed varactor biasingŒ10 is
used in this design. As shown in Fig. 8(a), two single biased
varactors of the same size are parallel connected, and biased
by different references, Vref1 and Vref2 . The corresponding C –
V characteristics are shown in Fig. 8(b), where C1 and C2 are
capacitance of two single biasing varactors, and the total capacitance C is a summation of C1 and C2 . If Vref1 and Vref2 are
set properly, the linear range of the distributed biasing varactor, denoted as LR, will be about the summation of two single
biasing range LR1 and LR2. Since the C –V gain of varactor
@Cvar /@Vctl is linear in doubled range for distributed biasing, the
resulting frequency tuning characteristic would be linearized in
extended voltage control range, with smaller variation of gain,
which is confirmed by measurement results shown in Section
4.
Fig. 11. Measured frequency tuning characteristics.
3. Measurement results and discussion
To widen the tuning range with small gain, a binary
weighted capacitor array is used as in Fig. 9. The proposed
VCO is fabricated in SMIC 0.18-m CMOS process. Figure
10 shows the micrograph of the fabricated VCO with a chip
area of 650 m 510 m (excluding pads).
Figure 11 shows the measured frequency tuning characteristics of the proposed oscillator. The tuning range is from 2.38
to 2.61 GHz, which is divided into 8 bands, each with control
voltage from 0.1 to 1.1 V. Good linearity of frequency tuning
characteristics in each band is achieved by distributed varactor biasing technology as expected. Another beneficial result
is the minimized VCO gain. The maximum and minimum gain
is 56.5 and 46.6 MHz/V, and the average gain of all bands is
51.4 MHz/V, thus the maximum variation of oscillation gain is
095009-4
J. Semicond. 2013, 34(9)
Parameter
Ref. [5]*
Ref. [11]
Ref. [12]*
Ref. [13]
Ref. [14]
This work
Chen Nan et al.
Table 1. Comparison of performance with prior works.
fC (GHz) Freq. range (GHz) VDD
Power
Phase
noise
(V)
(mW)
(dBc/Hz)
2.0
1.86–2.2
1.8
36
134:5 @ 1 MHz
2.0
1.8–2.0
1.8
4.8
103 @ 100 kHz
1.57
1.4–1.64
1.8
3.06
120 @ 1 MHz
1.84
1.76–1.93
1.8
1.35
126 @ 1 MHz
2.51
1.78–3.24
1.8
5.4
122 @ 1 MHz
2.55
2.38–2.46
1.2
3.2
122:8 @ 1 MHz
Tech.
(m)
0.18
0.18
0.18
0.18
0.18
0.18
Area
(mm2 /
N.A.
0.30
0.40
0.54
0.59
0.33
FoM
(dBc/Hz)
185
182
180
190
183
186
Quadrature output.
Ref. [13] achieved the highest FoM for low phase noise and low
power consumption, but to meet the rigorous start-up condition
of Colpitts VCO, additional boosted circuits are needed. VCO
with enhanced quality factor and linearized C –V curve of varactors for wide frequency rangeŒ14 is also compared. Compared to other works, our design exhibits low phase noise with
low power dissipation by proposed technology, thus achieving
higher FoM than other works exceptŒ13 . Additionally, our chip
occupies a small area, only larger than Ref. [11] in table.
4. Conclusion
Fig. 12. Measured phase noise at 2.55 GHz.
less than ˙10%.
The phase noise is measured using Agilent signal analyzer
N9030A, as shown in Fig. 12, which reach 77:5 dBc/Hz,
97:5 dBc/Hz and 122:8 dBc/Hz at 10 kHz, 100 kHz and
1 MHz offset, respectively, while consuming current of 2.7 mA
at a supply voltage of 1.2 V. Elimination of 1=f 3 dependency
of close-in phase noise proves the reduction of flicker noise.
The measured frequency range, phase noise and power dissipation well fit the project requirements as mentioned in Section 1.
The commonly used figure of merit (FoM) is defined as
FoM D 20 lg
fo
f
10 lg
P
1mW
PN;
(14)
where fo is the oscillation frequency, f is the offset frequency, P is power dissipation in mW, and PN is the
phase noise in dBc/Hz. The proposed oscillator gets FoM of
186 dBc/Hz at 1 MHz offset. The main results are compared
with relative work in Table 1, which are all implemented in
0.18 m technology. Self-switched biasing is used in Ref. [5]
for QVCO, which achieves surprisingly low phase noise with
the penalty of huge power consumption, while our design reduced power consumption significantly by triode region biased
tail transistors. Reference [11] presented optimization of phase
noise and power consumption for differential output by setting the differential pair to operating at the boundary between
the saturation and triode regions, while Reference [12] adopted
current reusing VCO and divider for quadrature output; however, their improvement of FoM is limited by the quality factor of the LC tank, which determines phase noise and power
if without additional effective technology. Colpitts VCO in
A 2.38 to 2.61 GHz differential VCO is presented, whose
low phase noise, low power and linearized frequency tuning
characteristics are achieved by design optimizations with effective techniques. The improved performance makes the proposed VCO fit for the requirements of our Zigbee transceiver.
References
[1] Hegazi E, Sjoland H, Abidi A A. A filtering technique to lower
LC oscillator phase noise. IEEE J Solid-State Circuits, 2001,
36(12): 1921
[2] Bloom I, Nemirovsky Y. 1/f noise reduction of metal–
oxide–semiconductor transistors by cycling from inversion to accumulation. Appl Phys Lett, 1991, 58(15): 1664
[3] Klumperink E A M, Gierkink S L J, Wel A P, et al. Reducing
MOSFET 1/f noise and power consumption by switched biasing. IEEE J Solid-State Circuits, 2000, 35(7): 994
[4] Boon C C, Do M A, Yeo K S, et al. RF CMOS low-phase-noise
LC oscillator through memory reduction tail transistor. IEEE
Trans Circuits Syst II: Express Briefs, 2004, 51(2): 85
[5] Huang G H, Kim B S. Low phase noise self-switched biasing LC
quadrature VCO. IEEE Trans Microw Theory Tech, 2009, 57(2):
344
[6] Hegazi E, Rael J, Abidi A A. The designer’s guide to high-purity
oscillator. New York: Springer, 2005
[7] Jerng A, Sodini C G. The impact of device type and sizing
on phase noise mechanisms. IEEE J Solid-State Circuits, 2005,
40(2): 360
[8] Levantino S, Samori C, Zanchi A, et al. AM-to-PM conversion in
varactor-tuned oscillators. IEEE Trans Circuits Syst II: Express
Briefs, 2002, 49(7): 509
[9] Ismail A, Abidi A A. CMOS differential LC oscillator with
suppressed up-converted flicker noise. IEEE International Solid
State Circuits Conference, 2003: 98
[10] Mira J, Dival T, Ramet S, et al. Distributed MOS varactor biasing
for VCO gain equalization in 0.13 m CMOS technology. IEEE
095009-5
J. Semicond. 2013, 34(9)
Chen Nan et al.
Radio Frequency Integrated Circuits Symposium, 2004: 131
[11] Young D J, Mallin S J, Cross M. 2 GHz CMOS voltage-controlled
oscillator with optimal design of phase noise and power dissipation. IEEE Radio Frequency Integrated Circuits Symposium,
2007: 131
[12] Park K G, Jeong C Y, Park J W, et al. Current reusing VCO and
divide-by-two frequency divider for quadrature LO generation.
IEEE Microw Wireless Compon Lett, 2008, 18(6): 413
[13] Hong J P and Lee S G. Gm -boosted differential drain-to-source
feedback colpitts CMOS VCO. IEEE Trans Microw Theory
Tech, 2011, 59(7): 1811
[14] Yin X, Ma C Y, Ye T C, et al. A low-phase-noise LC-VCO with an
enhanced-Q varactor for use in a high-sensitivity GNSS receiver.
Journal of Semiconductors, 2012, 33(5): 055002
095009-6