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ISSN 2319-8885 Vol.05,Issue.12 May-2016, Pages:2479-2484 www.ijsetr.com Implementation of Low-Dropout Regulator with Efficient Power Supply Rejection Ratio K. NARSIMHA REDDY1, POLISETTY PRAVEEN KUMAR2, C. SRINIVASAMURTHY3 1 2 Assistant Professor, Vardhaman College of Engineering, Shamshabad, Hyderabad, India, E-mail: [email protected]. Assistant Professor, QIS College of Engineering and Technology, Ongole, AP, India, E-mail: [email protected]. 3 Assistant Professor, QIS College of Engineering and Technology, Ongole, AP, India, E-mail: [email protected]. Abstract: As demand rises for electronic devices to be smaller, faster, and more efficient, increasing importance is placed on well designed voltage regulators for power supplies. When space is limited, as in the case of portable devices, circuitry for multiple functions requires multiple voltage levels on the same chip. Voltage regulators are needed to protect the rest of the circuitry from fluctuations in the power supply, which can occur due to crosstalk or digital switching. Large variations in the power supply are extremely detrimental. voltages that are too high can damage sensitive semiconductor devices, while voltages that are too low may disrupt biasing or even prevent the circuitry from working at all. So need of Voltage regulators come into picture. In this paper the architecture of Voltage regulator with good PSR is designed successfully. The results are verified using CADENDCE and LT-SPICE Software’s. By trading off PSRR with bandwidth and power, PSRR in the range of 40 to 60 dB was achieved. The LDO, without the load current, consumed 150 A of current or less under all conditions simulated. The dropout voltage was 500 mV, and the output voltage of 1.3 V could be sustained for a wide range of load currents above a certain minimum. This project demonstrates the flexibility the designer has within topology. Small adjustments to various component values can allow the design to meet a wide range of specifications and loading conditions. Keywords: LDO, PSR, CADENDCE and LT-SPICE. I. INTRODUCTION The low drop-out nature of the regulator makes it appropriate for use in many applications, namely, automotive, portable, industrial, and medical applications [1]. The automotive industry requires LDOs to power up digital circuits, especially during cold-crank conditions where the battery voltage can be below 6 Volts. The improving demand, however, is mainly apparent in mobile battery operated products, such as cellular phones, pagers, camera recorders, and laptops [2]. In a cellular phone, let us consider an event like, switching regulators are used to enhance the voltage but LDOs are cascaded in series to suppress the inherent noise associated with switchers. LDOs benefit from working with low input voltages because power consumption is reduced accordingly, P = I Load * Vin. Low voltage and low quiescent current are intrinsic circuit characteristics for increased battery efficiency and longevity [3]. Low voltage operation is also a consequence of process technology. This is because isolation barriers decrease as the component densities per unit area increase thereby exhibiting lower breakdown voltages [4, 5]. With the increasing sophistication of portable electronics, the demand for better power supplies is expanding. Supply systems must be precise and powerefficient to conserve energy and extend battery life, which is why inductor based converters are so accepted. Switching supplies, however, initiate controlled noise that state-of-the- art data converters, radio frequency radios, phase-locked loops, and others cannot sustain. So LDO linear regulators often post regulate a switched supply to suppress noise without dropping considerable power [1]–[6], [9]. What noise frequencies an LDO is capable of suppress depends on its bandwidth, which stability requirements under random loads (e.g., IL, RL, RESR) constrain to below 0.5–1 MHz [2], [7], [8].There is a great interest in efficient power management ICs. An important building block in power management is the LDO which often follows a DC-DC switching converter, as shown in Fig. 1. It is used to regulate the supplies ripples to provide a clean voltage source for the noise-aware analog/RF blocks. Designing a stable LDO for a wide range of load conditions, while achieving high power-supply rejection (PSR), low drop-out voltage, and low quiescent current, is the main intention using modern CMOS technologies. Recently, there has been an growing demand to incorporate the whole power management system into a sole system-on-chip (SoC) solution. Hence, operating frequencies of switching converters are growing to allow higher level of integration [5]. This movement increases the frequency of output ripples and therefore the subsequent LDO regulator should provide towering PSR up to switching frequencies. Conventional LDOs have poor PSR at high frequencies (above 300 kHz) Copyright @ 2016 IJSETR. All rights reserved. K. NARSIMHA REDDY, POLISETTY PRAVEEN KUMAR, C. SRINIVASAMURTHY .The main reasons for poor PSR are summarized as follows: conditions when current efficiency is low. For numerous 1) Finite output conductance of the pass transistor, 2) low DC applications, high load-current is usually a temporary gain and 3) finite bandwidth of the feedback path. condition whereas the opposite is true for low load-currents. Researchers have contributed to improve power-supply As a result, current efficiency plays a pivotal role in designing battery powered supplies. The two performance rejection techniques. specifications that predominantly limit the current efficiency Some of those techniques are: i) by means of simple RC of low drop-out regulators are maximum load-current and filtering at the output of the LDO [6]; ii) Cascading two transient output voltage variation requirements as shown in regulators [6]; iii) Cascading another transistor with the Fig.2. Typically, more quiescent current flow is necessary for pMOS pass transistor along with RC filtering, with special improved performance in these areas. technologies such as drain-extended FET devices, and/or charge-pump techniques to bias the gate of one of the transistors [7]–[9]. Simple RC filtering reduces the voltage (1) ripple at the input of the LDO. Fig.1. Block Diagram of typical power management system. However, this procedure increases the drop-out voltage in LDO regulators that supply high current due to the high voltage drop from corner to corner the resistance. Using an nMOS or pMOS transistor to cascade with the pMOS pass transistor can achieve high power supply rejection more than a large frequency range. This method increases the area and leads to a high drop-out voltage [7]. Charge pump techniques increase difficulty and lead to higher power consumption because a clock is essential along with RC filtering to remove clock ripples [9]. In summary, the main idea at the back all previously proposed techniques is to offer more separation between the input and output along the high-current signal path. Hence, the area consumption and drop-out voltage are huge, which is not proper for low-voltage technologies. In addition, these methods provide high PSR at low frequencies, but are not capable to provide sufficient PSR (better than 50 dB) at frequencies up to quite a few MHz. II. PARAMETRIC ANALYSIS OF THE PROPOSED LV-LDO REGULATOR A. Current Efficiency Current efficiency is an significant characteristic of battery powered products. It is defined as the ratio of the load-current to the total battery drain current, which is comprised of ILoad and the quiescent current (Iq) of the regulator. Current efficiency determines how much the lifetime of the battery is tainted by the mere existence of the regulator. Battery life is limited by the total battery current drain. During conditions where the load-current is much greater than the quiescent current, operation lifetime is mainly determined by the loadcurrent, which is an predictable characteristic of linear regulators. On the other hand, the effects of quiescent current on battery life are most common during low load-current Fig. 2. Conceptual block diagram of the proposed LDO regulator. B. Dropout Voltage Dropout voltage is the input-to-output differential voltage at which the circuit ceases to control against further reductions in input voltage; this point occurs when the input voltage approaches the output voltage. Fig 3 shows a typical LDO regulator circuit. In the dropout region, the PMOS pass element is simply a resistor, and dropout is expressed in terms of its on-resistance (Ron). Fig. 3. Typical Application Circuit of LDO Regulator. International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.12, May-2016, Pages: 2479-2484 Implementation of Low-Dropout Regulator with Efficient Power Supply Rejection Ratio For example, Fig. 4 shows the input/output characteristics current since the device is a voltage-driven device. The only of the TPS76733 3.3-V LDO regulator. The dropout voltage things that contribute to the quiescent current for MOS of the TPS76733 is typically 350 mV at 1 A. Thus, the LDO transistors are the biasing currents of band±gap, sampling regulator begins dropping out at 3.65-V input voltage; the resistor, and error amplifier. In applications where power range of the dropout region is between approximately 2-V consumption is critical, or where small bias current is needed and 3.65V input voltage. Below this, the device is in comparison with the output current, an LDO voltage nonfunctional. Low dropout voltage is essential to maximize regulator using MOS transistors is crucial. the regulator efficiency. D. Standby Current Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal. The reference and the error amplifier in an LDO regulator are not loaded during the standby mode. Fig. 4. Dropout Region of TPS76733 (3.3 V LDO). C. Quiescent Current Fig.5. Quiescent Current of LDO Regulator. Quiescent, or ground current, is the variation between input and output currents. Low quiescent current is needed to maximize the current efficiency. Fig. 5 shows the quiescent current and generally that is defined by (2) Quiescent current consists of bias current (such as bandgap reference, sampling resistor, and error amplifier currents) and the gate drive current of the series pass element, which do not contribute to output power. The value of quiescent current is generally resolute by the series pass element, topologies, ambient temperature, etc. For bipolar transistors, the quiescent current increases proportionally with the output current, because the series pass element is a current-driven device. In addition, in the dropout region the quiescent current can enhance due to the additional parasitic current path between the emitter and the base of the bipolar transistor, which is caused by a lower base voltage than that of the output voltage. For MOS transistors, the quiescent current has a near constant value with respect to the load III. LDO REALIZATION To accomplish the essential goals of compact and lowvoltage operation while achieving a fast transient response, low IQ and high PSR, four aspects of the projected LDO regulator are optimized. The circuit schematic is shown in Fig. 6. We first apply the simple symmetric OTA as the EA, composed of MEA1–MEA9, where gmi|i=1−9, rOi|i=1−9, and λi|i=1−9 represent the corresponding trans conductance, output resistance, and the channel length modulation coefficients, respectively. The OTA-type EA requires no compensation capacitor, and operates at a minimum supply voltage (VDD, min) equal to one threshold voltage plus twice the overdrive voltage (VDD, min =VT + 2 × VOV). Thus, the EA can control with a low supply voltage (≤1 V). The symmetric structure of the EA also has a low input offset voltage for the regulator to achieve an accurate output. Furthermore, the impedances at node vx and vy are low enough to push the non dominant pole (px) to a sufficient high frequency so as not to influence the system stability. The EA achieves a rail-to-rail output swing at node vG by the output stage (MEA7 and MEA9); therefore, the size of the MP can be reduced for a specific load current constraint. Reducing the size of the MP significantly reduces the circuit area and contributes to a smaller gate capacitance. This allows the EA to drive the MP by a huge enough slew rate with a relatively low biasing current. The AEAO is too small to achieve a fast transient response and high PSR. Therefore, we apply the current splitting method to improve the gain by maintaining gm2 and increasing rO9. The transistors Mgb1 and Mgb2 can trim down the bias current being mirrored to the second stage of the EA. Thus, the gain of the modified EA (AEAM) is boosted by a factor of 1/B.A p-type device is chosen to construct the power MOS transistor MP, because of the low supply voltage and low dropout voltage necessities. The gainboosted OTA-based EA improve the loop gain of the LDO regulator, which in turn enhances the PSR performance. In addition, we create a reproduction of the power noise at the gate terminal of the MP to cancel out the power noise at the source terminal of MP. This further improves the PSR performance. To trim down the area and IQ, we use the existing EA to duplicate the power noise as an alternative of using an auxiliary circuit. The two comparable resistors between the output nodes (vx and vy) of the first stage of the International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.12, May-2016, Pages: 2479-2484 K. NARSIMHA REDDY, POLISETTY PRAVEEN KUMAR, C. SRINIVASAMURTHY EA (stage1_EATA) and the ground have a low resistance We have to design the current mirror circuitry by value (1/gm4 and 1/gm5); therefore, the power supply noise appropriate biasing the voltage values. We have to test the of stage 1_EATA can be attenuated at nodes vx and vy. Only circuitry with and without load to check the parameters like a tiny level of power supply noise can be coupled to nodes vx vout, iout, load regulation, current efficiency, PSR value. The and vy, as they appear in the form of a common mode input resistance values of R1 and R2 has to maintain in such a way (vicm in Fig. 7) to the output stage of the EA (stage 2_EA). that the current it has to pass equal amount. The vdd and vss This is due to the symmetric structure of stage 1_EATA. The are collectively called as power rails. In the pmos section the common mode gain of stage 2_EA can be derived using the 4th terminal has to connect vdd and in the nmos section the low-frequency small-signal model, shown at the bottom of 4th terminal has to connect vss. The EA achieves a rail-to-rail Fig. 7, with an assumption of (rO6 _ 1/gm6). We first assume output swing at node vG by the output stage (MEA7 and that the power noise is propagated by stage 1_EATA through MEA9). Therefore, the size of the MP can be minimized for a specific load current requirement. A p-type device is chosen the common mode signal vicm and causes a variation on vg6. to build the power MOS transistor MP, because of the low supply voltage and low dropout voltage necessities as shown in Fig.8. To reduce the area and IQ, we use the EA to replicate the power noise as an alternative of using an auxiliary circuit. Fig. 6. Circuit schematic of the proposed LDO regulator. Fig. 8. Transistor level representation of proposed design in LT-SPICE. The first stage of the EA and Mta1–Mta8 constitutes the TA that reduces the slew time of the gate terminal of MP by rising the dynamic discharging/charging current during the load transient. The first stage of the EA is reused as a part of the output variation detector of the TA to diminish the circuit density. Furthermore, to shun a significant boost in IQ and to avoid the breaking of perfect replication of the power noise at the gate terminal of MP, Mta3, and Mta8 are biased at the cutoff region in the steady state. A large load alters causes a variation in both the output voltage (vOUT) and feedback voltage (vFB). The vFB variation is then enlarged by the output variation detector of the transient accelerator, generating vX1 and vY1. Fig.7.Low-frequency, small-signal model of the EA output stage (stage2_EA) for ripple cancellation analysis. International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.12, May-2016, Pages: 2479-2484 Implementation of Low-Dropout Regulator with Efficient Power Supply Rejection Ratio IV. RESULTS AND DISCUSSION The proposed LDO is designed with a 90nm and 180nm technology using LT-SPICE and CADENCE software. The waveforms which are shown in the fig.9 and fig.10 give the information about the output voltage with the applied VDD. In this paper particularly for the 90nm technology the output which should be getting as 0.86v with the applied 1v. The current drawn at the instant of M17 is 60uA. For the 180nm technology the output which should be getting as 0.88v with the applied 1v. The current drawn at the instant of M17 is 60uA.The horizontal axis represents the time whereas the vertical axis represents the voltage and the corresponding current values in the volts and uA units. Initially we have to apply 1 volt to the LDO. The corresponding voltage has to Fig. 11. Efficiency report of the proposed design. pass all the stages like Transient accelerator, bias circuitry, and power stage and error amplifier. The objective of the paper is to design an LDO which has a capability to drive the circuitry by maintaining the constant voltage as shown in Figs.11 and 12. Here we have to design the MOSFETS with appropriate threshold voltages to maintain the W/L ratio. Fig. 9. VDD vs VOUT in 90nm technology. Fig.12.power-supply rejection (PSR) of the proposed design. V. CONCLUSION This paper presented an LDO regulator using a simple EA plus an adaptive transient accelerator, which can achieve operation below 1 V as a fast transient response, low IQ, and high PSR under a wide range of operating conditions. The proposed LDO regulator was designed using a 90-nm and 180nm CADENCE and LT-SPICE Software’s and process to convert an input of 1 V to an output of 0.85–0.5 V, while achieving a PSR of ∼50 dB. This paper demonstrates the flexibility the designer has within topology. Small adjustments to various component values can allow the design to meet a wide range of specifications and loading conditions. VI. REFERENCES [1] Chung-Hsun Huang, Member, IEEE, Ying-Ting Ma, and Wei-Chen Liao. “ Design of a Low-Voltage Low-Dropout Regulator ” , IEEE Transactions On Very Large Scale Integration (Vlsi) Systems, Vol. 22, No. 6, June 2014. [2] F. Goodenough, "Off-Line and One-Cell IC Converters Up Efficiency," Electronic Design, pp. 55-64, June 27, 1994. [3] T. Regan, "Low Dropout Linear Regulators Improve Automotive And Battery-Powered Systems," Power conversion and Intelligent Motion, pp. 65-69,February 1990. Fig. 10. VDD vs VOUT in 180nm technology. International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.12, May-2016, Pages: 2479-2484 K. NARSIMHA REDDY, POLISETTY PRAVEEN KUMAR, C. SRINIVASAMURTHY [4] J. Wong, "A Low-Noise Low Drop-Out Regulator for Portable Equipment," Powerconversion and Intelligent Motion, pp. 38-43, May 1990. [5] M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing. New York: McGraw-Hill, Inc., 1994. [6] F. Goodenough, "Fast LDOs And Switchers Provide Sub5-V Power," Electronic Design, pp. 65-74, September 5, 1995. [7] “Application Note 883: Improved Power Supply Rejection for IC Linear Regulators,” Maxim Integrated Products, Inc., Sunnyvale, CA, Oct. 2002 [Online]. Available: http://www.maximic.com/appnotes.cfm/appnote_number/883 , accessed on Dec. 4, 2008 [8] J. M. Ingino and V. R. von Kaenel, “A 4-GHz clock system for a high performance System-on-a-chip design,” IEEE J. Solid-State Circuits,vol. 36, no. 11, pp. 1693–1698, Nov. 2001. [9] K.Wong and D. Evans, “A 150 mA low noise, high PSRR low-dropout linear regulator in 0.13 �m technology for RF SoC applications,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2006, pp.532–535. International Journal of Scientific Engineering and Technology Research Volume.05, IssueNo.12, May-2016, Pages: 2479-2484