Download Design of High-Speed Multi Bit Logic Decoder for Current Mode

International Journal of Electrical and Electronics
Engineering Research (IJEEER)
ISSN 2250-155X
Vol. 3, Issue 2, Jun 2013, 147-152
© TJPRC Pvt. Ltd.
DESIGN OF HIGH-SPEED MULTI BIT LOGIC DECODER FOR CURRENT MODE
SWITCHING
PRASHANT SINGH1 & NARENDRA BAHADUR SINGH2
1
Senior Project Fellow at CSIR-CEERI, Pilani, India
2
Chief Scientist, MEMS, MS & RF ICS Design, Central Electronics Engineering Research Institute (CSIR-CEERI),
Pilani, India
ABSTRACT
Circuit Design for high-speed multi bit logic decoder for input current mode switching has been presented in this
paper, Its functionality has been verified for 180nm TSMC CMOS foundry‟s parameters for eldo spice level 53 on Mentor
Graphics and tspice level 49 on TANNER EDA platforms. Similarly, its functionality has been also verified for 1.2µm
SCL Chandigarh CMOS Technology model parameters on both design platforms. Maximum pulse mode operation‟s speed
of the circuit for 180nm TSMC foundry is 1GHz and 20MHz for 1.2µm SCL Foundry. It uses minimum circuit elements
with respect to other similar circuit‟s functionality, low power consumption and faster conversion time to decode logic
from the input current.
KEYWORDS: CMOS Analogue Circuits, Multi Valued Logic, Binary Logic, Encoder and Decoder Digital Circuit
INTRODUCTION
As per prior art, such components are very much useful in semiconductor memories, like current sensing in
memory. Researchers were worked on current mode cmos multi valued logic decode using sense amplifier, current mode
quaternary threshold logic full adders, current mode analog to quaternary converter, current to voltage converter, etc. The
beauty of such circuit is faster speed with minimum circuit elements to implement such type of functionality.
THEORY
The presented work relates to high-speed multi bit logic decoder‟s design for current mode switching. CMOS
transistors‟ circuit has been designed to decode the logic based on input current to the circuit. The purpose of this circuit is
to generate logic on the basis of input current to the circuit, therefore if the current generation is based on logic pattern then
further to decode the logic from the current, such circuits could be used. It would be applicable in efficient flash memories
logic decoder or similar other decoders, as well as current sensing devices. Here, the quantizer module, as shown in Figure
1, composed of multi valued logic circuit based on input current amplitude and it generates the outputs correspond to multi
valued logic level which goes to the encoder assembly through the inverter [1-5], to produce the logical pattern needed by
the logic decoder assembly [8-10], to generate the binary outputs on the basis of instantaneous input current magnitude.
The circuit is designed completely either on mos transistor basis or resistance at input with mos transistors. Circuit idea
has been verified by the semiconductor industry grade circuit design tools using device grade foundry‟s Hspice model
parameters for 1.2µm SCL and 180nm TSMC CMOS Technology data. Circuit performance is superior on the basis of
lower power consumption and faster speed due to purely logic function and minimum circuit elements with respect to other
similar circuit‟s functionality. Logic voltage level „1‟ depends on the technology, in case for TSMC 180nm technology, it
is 1.8V and 5V in SCL 1.2 µm Technology, the input current is in mAmp range, its magnitude also depends on technology.
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Prashant Singh & Narendra Bahadur Singh
CIRCUIT’S DESCRIPTION
A high-speed multi bit logic decoder for input current mode switching has been designed and verified its
functionality using 180nm TSMC CMOS foundry, level 53 parameter for eldo spice simulation on Mentor Graphics and
mos model level 49 in tspice simulation under TANNER EDA platforms, the circuits is also verified using 1.2µm CMOS
SCL Chandigarh Foundry‟s mos model parameters for tspice level 13 simulation. Maximum pulse mode operation speed of
the circuit for 180nm TSMC foundry is 1GHz and 20MHz for 1.2µm SCL Foundry. System architecture is realized in such
a way that it uses maximum seventy one circuit elements with different versions like all seventy one mos transistors or
seventy mos transistors with single resistor or sixty seven mos transistors with four resistors. It has five level of
quantization with 3-bit outputs that can be extended as per requirement. Encoding module has been added in the design
with suitable decoder to generate the logic on the basis of current switching. Its maximum power consumption during
decode operation is less than 1mW (TSMC), 15mW (SCL) and 542pW in steady state analysis. Simulation result agrees in
eldo and tspice circuits‟ simulators for the same targeted technology model parameters having same operating conditions.
The circuit has numerous applications and least number of circuit elements for such type of functionality.
Figure 1: Block Diagram of Current Mode Logic Decoder for 5 Quantization Level Here, in1 is the Input
Current and inp is the Bias Voltage
V-C Source block diagram in Figure 2, is used to generate input current (in1) and bias voltage (inp), is the part of
Logic Quantizer, it is included in the same block.
Figure 2: Block Diagram of Current Generator and Logic Quantizer
V-C Source in Figure 2, produces current output based on eight different referenced input voltages and the
quantizer block produces its corresponding five digit outputs, whose inverted signals are fed to encoder assembly.
Design of High-Speed Multi Bit Logic Decoder for Current Mode Switching
149
SIMULATION’S RESULTS
Various simulation runs are carried out for the circuit shown in Figure 1 and 2.
Figure 3: Input Current (X-Axis) Vs. Supply Current (Y-Axis) for the Output in Figure 4,
Simulated Using TANNER EDA
Figure 3, shows the plot between input current produced from the V-C source where its input is from eight
different voltage sources verses the supply current for the input to five level logic quantizer.
Figure 4: Input Current Vs Output Bit Pattern of Logic Decoder for 1.2µm SCL Technology in Steady State
Analysis for 5 Quantization Level
Figure 5: Input Current (X-axis) Vs. Supply Current (Y-Axis) for the Output in Figure 6,
Simulated Using TANNER EDA
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Prashant Singh & Narendra Bahadur Singh
Figure 6: Input Current Vs Output Bit Pattern of Logic Decoder for 1.2µm SCL Technology in Steady State
Analysis for 5 Quantization Level
Figure 7: Transient Analysis for Input Current (Iics) and Supply Current (iv1)
for the Output Presented in Figure 8, Simulated Using TANNER EDA
Details for applied input pulse of Peak Current 4.5mA is,
Pulse Period = 50ns, Pulse Width =45ns, Rise Time = 4ns and Fall Time =1ns.
Figure 8: Transient Analysis of Output Bit Pattern of Logic Decoder for
1.2µm SCL Technology for 5 Quantization Level
Design of High-Speed Multi Bit Logic Decoder for Current Mode Switching
151
Figure 9: Input Current vs Output Bit Pattern of the Logic Decoder for 180nm TSMC
Technology Using Mentor Eldo & Ezwave SW for Steady State Analysis.
I (V1) is the Current through Power Supply (1.8V) to the Circuit
Figure 10: Output Bit Pattern of Decoder for 180nm TSMC Technology in Transient
Analysis, Input 1.5mA Pulse Duration 1ns with Rise and Fall Time 15ps/5ps
CONCLUSIONS
System architecture is realized in such a way that it uses maximum seventy one circuit elements with different
versions like all seventy one mos transistors or seventy mos transistors with single resistor or sixty seven mos transistors
with four resistors. It has five different current switching points for 3-bit outputs that can be extended as per requirement.
Encoding module has been added in the design with suitable decoder to generate the logic on the basis of current
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Prashant Singh & Narendra Bahadur Singh
switching. Its maximum power consumption during decode operation is less than 1mW (for 180nmTSMC), 15mW (for
1.2µm SCL) and 542pW in idle case in steady state analysis. The circuit has numerous applications. It uses minimum
circuit elements with low power consumption and maximum conversion speed.
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