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Rex Li
English 202C
Technical Description
Complementary MOSFET (CMOS) Digital Logic Design
The purpose of this paper is to describe how simple logic gates work and what electronic
components they are made of. Before I begin describing how basic logic gates are created, I will
first review logic gates and the CMOS device which will be the primary building block for our
logic circuits. The simple gates like AND, OR, and their negations NAND and NOR, you can see
their logic in truth tables as shown below.
Aligning with convention so that 1 is ON and 0 is OFF, these tables describle the
function of these two basic logic gates with their negation being determined by inverting
(swtiching 0 for 1 and vice versa) all logic states. A simple use of these logic gates can be switch
applications like turning on lights in a two story house. If the house has one switch on either
floor, use of a combination of these logic circuits could design an implemation so that when
either switch is on, the light are on and if the light is on, either switch could turn the lights off.
For now, we can see that an AND gate requires both inputs to be ON
for the output to be ON, while for an OR, the output is ON if either or
both inputs are ON.
Now to review the CMOS inverter device. As shown to the
right, the CMOS device is made up of two stages in conjunction, a p
channel MOSFET and an n channel MOSFET. The device function
can be simplified for our purposes and functions as once the input
voltage crosses a certain theshhold, the output voltage will be
logically inverted compared to the input voltage. In digital logic, all
logic elements are assigned to a voltage range with those below the
voltage threshold assigned to logic 0 and those above the threshold
assigned to logic 1. Now that we have review the basic building
block for digital logic, I will show how combination of these devices
can be used to create the same basic truth tables as shown above.
The most simple logic implemenation using CMOS devices would be the NAND gate.
The schematic and truth table are shown below. You can see that this gate would function with
ON as a default and only when both inputs are ON would the output be OFF. I will describe the
schematic in 5 parts: the voltage bias (Vdd) and groud, the input, the output, and the two stages
above the output line (the pull up network and the pull down network). To start, the voltage bias
(Vdd) modulates the threshold with which the device will be ON or OFF. As shown in the
CMOS inverter design, the voltage biases of +5V defines all voltage signals below 2.5V to be
logic 0 or OFF, while all voltages above 2.5V are defined to be logic 1 or ON. Further specifics
such as voltages near the 2.5V threshold range are out of the scope of this descrption and would
depend on the design of the device and its own parameters. For now, the assumption that the
voltage bias divided by two gives the the threshold for which logic 0 and logic 1 are defined.
Unlike the light switch application described previously where logic 1 and 0 can be described as
ON/OFF or open/closed, it is important to note that in digitial logic such as computers all logic
elementary are just voltage levels and it is the bias of that particular device or circuit element that
determins how that voltage level is interpreted. Opposite of the voltage bias is the common
ground is defined to be 0V or logic 0.
Next the pullup network is elements above the output while the pulldown network is
below the output reference. More specifics of the pulldown and pullup network related to how
the combination of various MOSFETs can be combined to created more complex logic circuits,
but those concepts are outside of scope of this paper as we will mainly be discussing single stage
implementation of the basic logic elements.
The input and output stages should be self explantory now that the voltage bias was
describled. The input and output stages can be described in voltage levels or logic levels from
now on I will be using logic levels to decribe the input/output relationship. The two input
directly affect the 4 MOSFET labeled Q1-4. An imporant design factor of this circuit is that Q1
and Q3 are both controlled by the same input signal, in this case input A; similarly, Q2 and Q4
are controlled by input B. The way the CMOS devices work is that given a pair of MOSFETs,
such as Q1 and Q3, if the input crosses the voltage threshold, Q1 and Q3 will be of reverse logic
levels. So if Q1 is ON, then Q3 will be OFF. More specifically, if the input voltage is above the
voltage threshold, then the pullup network will be in the OFF or logic 0 stage.
Now we can finally see how all these compenents work together and create logic
elements. Imagine electrical current as water flowing through these components and the state of
the components will determine if the water can flow through with logic 1 as a valve being
opened and logic 0 being a valve being closed. Now if we trace the various input combinations
from the truth table we can see how the desired output is achieved. If input A and input B are
both at logic 0, then Q1 and Q2 will be ON while Q3 and Q4 will be off. The output will be the
voltage bias (Vdd) minus some small voltage lost in the devices, but this final output voltage will
be above the voltage threshold so the output will be interpreted as logic 1. If you trace through a
similar process with the other input cases you can see how the CMOS NAND circuit implements
the truth table besides it.
Finally, you might be wondering why NAND instead of AND was used as the first
example since AND is a more basic logic concept and so you might assume that it has the most
simple implementation. However, due to the device characteristics of MOSFETs, a logic low
input will generate a logic high output, NAND is simplier to implement than AND. Yet since
NAND and AND are inverses of each other we can add the CMOS inverter that we discussed
previously as a second stage to invert the output to create the AND implementation from the
NAND circuit as shown below. To create an OR or NOR implementation, you just need to
change the components in the pullup and pulldown networks to be the logic duel (AND/OR or
series/parellel). For instance, you can see in the pullup network of the NAND implenation, Q1
and Q2 are parallel, meaning that either Q1 or Q2 can be on for the output to be logic 1, but for
the output to be logic 0 both Q3 and Q4 need to be on so that the output is directly connected to
ground or using the analogy before, no current is flowing from the voltage bias to the output and
the output is directly connected to the drain of the pipes. Another topic to emphasize again is that
the components in the pullup and pull down networks are logically duels of each other, so all
three components connected to the same input cannot be of the same logic state. So for the NOR
implementation, both Q1 and Q2 need to be ON for the output to be logic 1; otherwise, the
output will be directly connected to ground which is defined as logic 0.
.
This paper covers the basics for MOSFET logic circuits and additional information can
be found at the following two links below, especially logic truth tables which wasn’t the focus of
this paper. Hopefully, this paper laid the groundwork in understanding how much of the digital
logic in our technology works.
Additional Reading
http://www.allaboutcircuits.com/textbook/digital/chpt-3/cmos-gate-circuitry/
http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/gatesfunc/